LC83010N SANYO | Alldatasheet
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~ LSI functions 1) Dual Harvard Architecture: Enables simultaneous processing (multiply and addition) of stereo signals in a single instruction cycle. The LC83010N,LC83010NE processor has the following two independent units: ~ Multiplier ; 24 bits x 16 bits (fixed-point decimal) - ALU : 32-bit arithmetic calculation, 24-bit arithmetic and logical operations - ACCumulator (ACC) : 32 bits - Temporal Registers (TMPO to TMP7) : 32-bit for each - Internal Memory Data RAM 128 x 24 bits Coefficient RAM 256 x 16 bits Constant ROM 256 x 24 bits 2) Program Memory Capacity (RAM) : 320 x 32 bits 3) A variety of I/O interfaces - Audio signal 1/0 1 channel for input (applicable to various formats) 3 channels for output (applicable to up to 4 types of data format) - Surround DRAM access signal 16 accesses/CH Max. (within 1 fs) Up to 2 256K (64K x 4 bits) DRAMs or 1M (256K x 4 bits) DRAMs can be directly connected to this chip, ~ Uses external DRAMS with RAS access times of 120 ns or lower ~ Serial input/Output interface with a microcomputer Synchronous 8-bit serial input : 1 (Mail box (16 bits x 8) function. available] Synchronous 8-bit serial output : 1 4) Interrupt function (Vectored interrupt with the INT pin) 5) Stack Nesting Levels : 4 6) On-chip Interval Timer : 12 bits (timer clock = sampling frequency) 7) Cycle time : 108ns (sampling frequency = 48kHz) 8) Single 5V power supply 9) Package : 64-pin DIPs (LC83010N) 80-pin QFPs (LC83010NE) Note) When soldering QFP devices, do not use the solder dip method. 10) Evaluation chip : LC83EVO10N (PGA100) - Applications - Graphic Equalizer - Power calculation for spectrum analyzer display - Sound filed creation (using external DRAMs) - 4 Speakers + REC output SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N251JN KI No. 3945-1/20
LC83010N, 83010NE = SSS Development Environment . - Software Tools 1) Assembler 2) Debugger with simulation - Hardware Tools 1) IBM PC-AT compatible machines or AX personal computers 2) In Circuit Emulator (ICE) Package Dimensions 3071 Package Dimensions 3174 (unit:'mm ) tLesso1ony — (unit! mm) (LC83010NE] a O15 6 a gl ‘ * a } Ay lid Lao (1 $e =e = =4 | 3 S| = = sl = = en mei i7s ES EP 3] 57.2 q| EB ES =a | i rs be ES =a = =| SP q = = s q ve = Ee =p | | s: aa eT ETHER AD YY) Te” SANYO: pireas 1] FUE ESTE EUUEUEBUUEBEY |, 1 3 22 a Qt 3 SANYO: QIP80E Pinout and Block Diagram Block Diagram Lbus Rous [aa reve Ff ae won gees te ef owe | { [econst. ][ coors. |] data |? [data | [coert. | const | i i:TT TE TE) EET TT Ty: : Pty [TTT i : Ace | E= : i TMPOto7 a TMPO to7 i Sequence oe SSSSSSSSSSSSSSSSSSSSSSSSSSSSsSsSsSsSseessesssseseeeeee No, 3945-2/20
LC83010N, 83010NE — SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSOeee Pinout (DIP64S) Pod 4 64 SADY Pig 2 63h SIAK P2q 3 62 p SIRO Paq 4 61P sick Pad 5 60p si PB 6 69D SOAK AOTDF1Y 7 58 p SORO AOTDF24 8 57 p SOCK Seek e109 Bsb Ao q P AOWCK RAS 11 54H aso ASG 12 53p AOBCK DREAD q 52PTEST4 BWAT q 14 51H TESTS Voot g 15 50p TesT2 98C1q16 LCB3010N 49) TEsT1 osc2 q 17 48 P Vss2 Vsst 18 47 BINT F$3840 q 19 46 PRES 00q20 45 B Vop2 Dida 44 BFS640/TS D2 422 436 SELC D3q 23 42 B LACK! D4q24 41 LRCKO DS das, 40 bP asi2 06026 39 ASI1 D727 33 BCK2 A0q 28 37 PBCK1 A129 36 PAB A2q30 35 PA7 A3q31 abbas A432 33 AS {QIP80E) $ ¥er_ ee Bose xn g Srroakrog angel? Xaw Pos SSFPPESRSIE BES ER ESSE NOOO ono AnoM 64 63 62 61 57 56 55 54 53 52 51 50 49 48 47 4 SURG (ght © & 61 G0 9 58 BEM BAA L ney SOAK C66 39] 8CK2 si Qe 38[7) 6CKT sick [68 370 48 ‘SRO Ceo 36) 47 SiR (70 35[9) (NC) SROY (j71 34[D AG (ne) (72 33[9 AS po 3 L.C83010NE 32 aa pro 3 43 p2 75 30[7) (no) p3 ()7s 290 az (wo) 77 2D at pa (78 27) ao ps C]79 26[7) 07 OF ng 4 5 67 8 9 0 1213 415 16 17 18 19 1 21 Ze 23 UE OUUUUUOUDOUUDUDOUDOUUDOUUOUo Top View sox xX Sronrcseensanrs 5) 8 gs B S IS z mo No, 3945-3/20
LC83010N, 83010NE $e SSSSSSSSSSSSSSSSSSSSSSSSSSSS Pin Description | __ Pia Name] VO Functional Description Vopl2 +5V power supply pins (These pins should be connected to the positive power source.) Vsgt,2 GND power supply pins (These pins should be connected to the ground level.) asi 1 | Audio data serlal input 1 ASI2 1 | Audio data serlal Input 2 BCKI (| Bit clock Input pin for ASI1 data | BCK2 (/O | Bit clock input pin for ASI2 data (I/O selectable by CR) 8 | LRCKI 1 | Input pin for L/R channel distinguish signal (H: L channel data ; L: R 5 channel data) | LRCKO | © | Input pin for L/R channel distinguish signal (H: L channel data ; L: R L channel data) S| aso © | Audio data seria! output g| AOBCK | O | Bit clock output pin for ASO data (for 32fs and 48fs) 3] Aowck | © | Word clock output pin for ASO data <J| AOTOF1 | © | Serial output pin for audio data (for high presence 1) AOTDF2 | © | Seria! output pin for audio data (for high presence 2) OFBCK | O | Bit clock output pin for AOTDF1 and AOTDF2 data (for 32fs and 48fs) DFWCK | © | Word clock output pin for AOTDF1 and AOTDF2 data RAS © | Output pin for RAS signal to external DRAMs CAS © | Output pin for CAS signal to external DRAMs u| DREAD | © | Output pin for data read signal to external ORAMs =| DWRT © | Output pin for data write signal to external DRAMs Z|} A0 tos | O | Output pins for address signals to external DRAMs (64K x 4 bits: AO to rs AT, 256K x 4 bits: AO to A8) ©| Do to 7 | 1/0 | input/output pins for data transfer with external DRAMs. in the single DRAM configuration mode, pins DO to D3 are used. In the double DRAM configuration mode, pins DO to D7 are used, si Input pin for serial data from contro! microcomputer (8-blt serial data) sick Serlal clock input pin for SI data SIRQ. Request signal input pin for serial data Input & | SIAK Output pin for Acknowledge response to the Input request signal from a 5 microcomputer =| SRDY Input pin for a Ready signal from a controlling microcomputer Indicating é the end of a data transfer 8] so Output pin for serial data to a controlling microcomputer (8-bit serial i data) $| sock Serial clock input pin for SO data SORO Request signa! input pin for seria! data output SOAR Output pin for Acknowledge response to the output request signal from a microcomputer | [rors | vo General-purpose Input/Output ports (with on-chip pull-up resistor) osc1 Pin for connection with a crystal oscitlator or for clock Input from an external source, (384fs) osc2 Pin for connection with a crystal oscillator (should be left open in external clock Input mode) [saeco | of aaets ext in jer [| Interrupt request input pin (with on-chip pull-up resistor) Py & [Res | | Reset input pin (with on-chip pull-up resistor) £| sete L/R channel signal select input pin with on-chip pull-down resistor: L: 8 external (LRCKI), H: internal (Internal divider outout) TesT Test signal input pins. Normally, these pins should be connected to the 1to4 ground level. FS640/TS Test signal output pins. 64fs clock output/test output. FS640/TS functions as a test output In test mode and as a 64fs clock output for external A/D converters during normal operation, eee No. 3945-4/20
LC83010N, 83010NE SSW $SSSSSSSSSSSSSSSSSSsSSS Pin configuration types ASO,AOBCK AOWCK, TTL level output LRCKO,AOTOF 1, AOTOF2, DFWCK, AO to A8,FS3840, < RAS,CAS, DREAD, DWRT, FS640/T5 CMOS medium level SO,SOAK,SIAK current output > ‘Output data Schmitt input SOCK,SI,SICK,SORQ, SIRQ,SRDY C+» input data L level Schmitt BCK1,AS!1,ASI2,LRCKI input Normal input TEST1 to 4 O——Do—— input aata Input with RES,INT internal pull-up < resistor Input data Input with SELC internal Input data pull-down resistor TTL level BCK2,D0 to D7 output 7a Low level Schmitt Input data input I
5 Input/Output
Normal input < Input data ee No, 3945-5/20
LC83010N, 83010NE ee SSSSSSSSSSeSSSeSSSSSSSSFSSSSSSSSSSSSSSSSSEeeFeFeFeFeFeeee Electrical Specifications Maximum Absolute Ratings/Ta=250, Vsg=0V [reser [even [ree [eon [tems [ot [| Maximum Supply |Vppmax 0.3 to +7.0 v Voltage Output Voltage vot OSC2 output Up to the voltage Vv produced by oscillation vo2 Pins except -0.3 to Vpp+0.3 v ' for the OSC2 Peak Output Audio 1/F -2 to +4 mA Current DRAM I/F Microcomputer -2 to +10 mA VF Average Output |igat Audio 1/F mA Current loa2 Audio /F Per pin -2 to +4] mA DRAM I/F load Microcomputer Per pin -2 to +10 mA VF oe _fees [wm | aero) mp | Eloa2 | Audio I/F Total DRAM I/F E1943 | Microcomputer | Total 4 to +15} mA VF foe eee [ee [eel Allowable Power Tas-30 to +70C mw Dissipation Operating Ambient | Topg -30 to +70} Temperature Range] Storage Tstg c temperature range 3% When soldering QFP devices, do not use the solder dip method, eee No. 3945-6/20
LC83010N, 83010NE a SSSSSSSsSeSSsSsssesSSSSSSssSssSSSSSSSsSSSSSSSSSSSSSS Allowable Operating Conditions (Ta=-300 to +700, VpD=4.75V to 5.25V, Vsg=OV, unless otherwise noted) Parameter Symbol Pins and Conditions unit Note [ae [ve] mm | Operating Supply | VoD 4.75 v Voltage Input Voltage seinen " “mee Pf of fe Input Voltage ViL3 RES,INT,Microcomputer 1/F ae a Operating fop Up to 1% crystal oscillation 12.17 18.62 MHz Frequency (TCYC) | error is allowed, (165) (107)ns (ns) (instruction max:48kHzX384X 1,01 Cycle Time) Pa) See Figure 1. B3| Pulse width text | (OSC1 : input, OSC2: Open) 20 3d tEXTL 2 81 Rise Time texTR P| Fall Time tEXTF § Oscillation fEXT OSC1,0SC2 See Figure 2. 18.62 MHz |S | | Frequency Ba 8 |<'5| | Oscillation fEXTS See Figure 3. es} Qj Stabilizing
6 Period
| Transfer Bit |tacyc | Applies to the BCK1 and 325 BS Clock Cycle BCK2 pins, 5 See Figure 4. ©| Transfer Bit | tacw 4 | Clock Pulse 2 width g Date Set up ts 75 ns ©} Time Continued on the next page. oS No. 3945-7/20
LC83010N, 83010NE er Continued from the preceding page. Standard Values Parameter Symbol Pins and Conditions unit Note | in| ve | max | g | Serial Clock tscyc Applies to the microcomputer & | Cycle interface. See Figure 5. FS (Applies to the SICK, SOCK 8 and SI pins.) © | serial Clock | tsow
3 Pulse Width
(3) Data setup | tgg 75 Q = | Time 5 | Data Hold tsH 15 8 | time Be Date Set up Applies to the data input £ §| Time from external DRAM. se See Figure 6, € 8| Oata Hold toH (Timings between RAS, GG] Time CAS and DO to D7) ee No. 3945-8/20
LC83010N, 83010NE a SeSeeeeSeSeesesSesssSsSsssssssSeeeeee Electrical Characteristics (Ta=-30C to +70 C. Vpp=4.75V to 5.25V. Vsg=OV, unless otherwise noted) Standard Values Parameter Symbol Pins and Conditions Note [me [ve | mon | Input Current | High Level iw SELC, Input pin with 250 uA Input Current pull-down resistor Output Voltage Output Voltage Input Leakage ViN=Vss to Vpp LA Current Output-of f lorF Vo=Vss.VDD uA Leakage Current Input/Output oF Capacitance Output Data | tow Applies to audio data output. SE] Hold Time See Figure 7. Sr lo Zloutput Data | top 18 5| Delay ILO
53 Applies to serial data
output. es 338 Output Data tsp See Figure 8. 8 3| Delay EES Continued on the next page. INo products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. WM Anyone purchasing any products described or contained herein for an above-mentioned use shall: © Accept full responsibility and indemnify and defend SANYO ELECTRIC CO, LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally, WM Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production, SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. See No. 3945-9/20
LC83010N, 83010NE eS | Continued from the preceding page. Parameter Symbol Pins and Conditions unit. Fan [oe [no | RAS "H" Pulse | tre Data output timing for ns Width external DRAM. See Figure 9. RAS "LU" (Note) DRAM which has Wah Pulse |tRas RAS access time ' below 120ns CAS "H" Pulse | tcp soul be Width . CAS "L" Pulse | tcas
2 Width
©|RAS Address |trs
3 Set up Time
5 RAS Address |tRH
_ | Hold Time | CAS Address tcs ns | Set up Time | GAS Address |tcH | Hold Time *|DWRT Pulse [tw Width CAS-before- two WRITE Set up Time Data Set up tsD Time Data Hold tHD Time Crystal Oscil- C1,C2 oSc1,0SC2 See Figure 2, pF lation Current Vp01,2 18,62MHz external Dissipation clock (Note 1) TTL level output pins: ASO, AOBCK, AOWCK, LRCKO, BCK2, AOTDF1, AOTDF2, DFBCK, DFWCK, DO to D7, AO to A8, FS3840, RAS, CAS, DREAD, DWRT and FS640/TS (Note 2) CMOS medium current outputs: SO, SOAK, and SIAK (Note 3) Pu MOS medium current outputs: PO to P5 (Note 4) TTL level outputs (first group): ASO, AOBCK, AOWCK, LRCKO, AO to A8, DO to D7, FS3840 and BCK2 {Note 5) TTL level outputs (second group): AOTDF1, AOTDF2, DFWCK, RAS, CAS, DREAD, DWRT, and OFBCK (Note 6) L level Schmitt inputs pin: BCK1, BCK2, ASI1, ASI2, LRCKI, and DO to D7 (Note 7) Schmitt input pins: RES, INT, SOCK, SI, SICK, SORQ, SIRQ, and SRDY (Note 8) The maximum load capacitance of RAS, CAS, DREAD, DWRT, DO to D7 and AO to A8 is S0pF. SSeS No, 3945-10/20
LC83010N, 83010NE a SSSSSSSSSSsSSSSSSsSSSSSSSSSSSSSsSSSSSSSSSSSSSSSSSSSSSSSSSS Program load to the LC83010N - Boot procedure - Programs must be loaded (boot strap) into the LC83010N (D?SP) from an external control unit (microcomputer) because its internal program memory consists of RAMs. The capacity of the program memory is 320 words x 32 bits. The procedural flow to load a 320-word program into the DSP from a controlling microcomputer is shown in Figure A-1, (1) Reset the entire system (microcomputer and D2SP) or reset the D?SP from the controlling microcomputer. After the D?SP is reset, it then enters the Boot mode. {2) Transfer the program to the DSP from the microcomputer. The program is transferred to the D2SP in 8- bit synchronous serial communication mode. The program data of 8 bits x 16 data (equal to 4 instructions) is transferred to the D2SP continuously from the microcomputer, and followed by the SRDY signal. The D2SP stores that program data of 4 instructions to the internal mail box. The program data is then moved to the program RAM at the moment. when the SRDY signal reaches the D?SP, {3) The operations discussed in (2) are repeated 80 times until the program data transfer of 320 instructions from the microcomputer to the D?SP is complete. (4) The O?SP automatically starts the program execution when the program loading of 320 instructions is complete. The program is transferred to the D?SP from the microcomputer in that manner. : fe : Reset the D2SP, i i Synchronous ) i ; B-bit sertal H i ! Boot mode communtcetlo H : : i i 8 bits x 16 data } : i H (4 Instructions) i : Program RAM ——mail box i +] Ready signal (every 4 instructions) i i [No i i no} } H 320 Instructions: 7 H : 320 instructions : ? Hi i YES i YES : ' ‘ ‘ 1 : Program execution H i Next job ' Figure A-1, Example. Program Boot flow (D2SP «— Microcomputer) eee No. 3945-13/20
LC83010N, 83010NE oo SSSSSSSSSSSSssSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS Figure A-2 gives the outline of an example program Boot system. DO? SP Controlling microcomputer Handshake signals for Program RAM: serial communication Program 32 bits x 320 \\ D2SP program | data ROM mait box |_| StRa NN STAK J | Ls! |Toce TT <2 | System reset Figure A-2. Outline of an example program Boot system Development tool system - Program development flow - Development tools are provided to help the user to easily develop application programs for the D?SP. These Code a source <<, development tools are divided into two groups: software application program. : support tool group and hardware support tool group. H The software support tool group consists of an 1 assembler, debugger and simulator. Check the pr 7 " : The hardware support tool group is realized as an In- pans th Alia on ax ‘ Circuit Emulator (ICE). HED tite e assem jer > i Figure A-3 shows the apptiations development flow for e generation : the D2SP system. Software H (1) Write an application source program. support i (2) Check the source program for syntax errors with the | tool : assembler. if every syntax error is corrected, the Debugger i assembler generates a HEX program file. : (3) Check the HEX file for operational errors with the Program evaluation ‘ simulator, tf the desired operations are not with the simulator : successful, start the debugger to find what caused ‘ logical errors. t (4) If program operations are checked successfully, use | WO ig! co ece cee eececeeeet the ICE to evaluate the audio signal output. : First, evaluate sound signals only with the ICE. In Evaluation of audio : this evaluation process, the delay memory and Hardware outputs with the ICE ! microcomputer of the ICE are used. support (a)Evaluation with the ICE [77 Second, start the total evatuation on an tool only. application system. In this evaluation stage, the (b)Evaluation with the user AD/DA converters, microcomputer, and delay memory | application system on the user application system are used. Figure A-4 shows the entire program development Figure A-3. Applications Development Flow tool system for the D2SP, f The software tools such as the assembler, debugger, | simulator can be run on an IBM PC-AT compatible machine or an AX personal computer. The ICE Is also controlled by such a host personal computer. eee No, 3945-14/20
LC83010N, 83010NE SSeS IBM PC-AT compatible computer User application board or AX personal computer ‘AD/DA converters MBC995, 174, 18J Microcomputer (eeepc Delay memory > Simulation debugger —sF — LJ LOA ZT rua chip <> —— rz L~ x TTI — Audio signal source ZO 7 gta CT Fates CD, DAT, BSC AMP Figure A-4, Entire support tool system for microprogram development. (1) Debugger The debugger is a software support tool designed to realize virtual D2SP functional circuits. In this virtually emulated O?SP environment, user application programs can be evaluated as if they were executed on the real chip. The debugger is used mainly for logics analysis and detailed data analysis. Major functions of the debugger are listed in the table below, with brief explanation for each. - Display and Edit instructions These instructions can be used to display the contents of memory and registers on a screen and to update them. - Memory Fill instruction This instruction is used to fill a specified memory address range with a desired value. - Move instruction This instruction is used to transfer the data in a specified memory address range to another range. - Memory Load and Save instructions These instructions are used to transfer data between memory and disk. The memory load instruction enables the data transfer from a disk file to memory while the memory save instruction allows the data transfer from memory to a disk file. - Assemble and Unassemble instructions The assemble instruction is used to convert mnemonics into machine codes. The unassemble instruction is used to convert memory data back to mnemonics. - Emulation instruction control instruction and Break point instruction These instructions are used to execute the D2SP program and trace its operations. The break point instruction is used to set a point where the program execution stops. Table Major debugger functions ee No. 3945-15/20
LC83010N, 83010NE ss SSSSsSsSSSSSSSSSSSSsSSSSSSSSSSSSSSSSSSSSSSSSS (2) Outline of the simulator functions The application programs can be tested in the following sequence: - Inputting digital audio signals to the D2SP chip, ~ Executing a program, - Converting the audio output into analog signals, and - Measuring the analog signals with an oscilloscope or frequency characteristics meter (or sweep meter). The simulator enables the above operations on a personal computer. Figure A-5 shows the signal waveform measurement. This simulator has the following three measurement functions: 1) Audio output waveforms (sine waves) with respect to audio input waveforms (sine waves) 2) Frequency characteristics of audio output (AOUT) 3) Impulse response characteristics of audio output AIN L-channel AIN R-channel AOUT L-channel AOUT R-channel 24bit date mode “TTT eo WT HEHEHE os ETT BAER Er Lat | Hee HE Eo e PANNA TN TEN LT) 3 oo ANN NNT RTT RT A HENCE NEEL AEA & HRP REHASH NDT INTE HABE REHEAT os FLT Meh TSAO PE HOE PP ve LETT TTT TP Pr ° 100 200 300 400 500 600 Sampling - (times) Figure A-S. Display of various waveforms No. 3945-16/20
LC83010N, 83010NE —SSSSSSSSSSSSSSSSSSSSSSFFSSSSee 4008 | TT Tit TrTT rT TT Ter PTT try Teer yy | TP tt? TP rr Pre Peo a PtP rey yy er PtP tr Pry rr Nee ow | | [TT Peer tT Swe | g | TE tty Prey ry Per © PtP try Tir P| P Tt tty Pry ere -oel|—_| T TTT TP tr rT Pr Ltt Tt Perry rr | TT tTty try ry try | TTT) Terry rey -o«t_t tT TTT fT tt ry Tr a | TT Tir PP rr a A 0 2 3°57 10 2 3 5 7 100 2 3 § 7 10000 (Hx) Frequency ~ (Hz) Figure A-6. Display of frequency characteristics Aout-L. Aout-R DFM--L DFM--R OFS--L OFS--R 0.0 ee a wa | | A | tf 0.034 0.02 y 5 00 Y ww crim : BAe eee 008 rp J 0 1 2 3 4 5 Time - (msec) Figure A-7, Impulse response waveforms (limit cycle characteristic) No. 3945-17/20
LC83010N, 83010NE ——SSSSSSsSSSSSSsSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS (3) ICE outline The In-Circuit Emulator (ICE) provides an operating environment where the application program already checked by the simulation debugger is executed and then outputs audio signals. The ICE functions can be divided into two: One Is the program evaluation by outputting audio signals only on the ICE. In this ; evaluation method, delay can be produced by the DRAM in the ICE system. The other is the final program evaluation by connecting a user application board to the ICE system. In this test method, the interfaces to the controlling microcomputer and other various peripheral LSIs on the application board can be evaluated, Figure A-8 shows the ICE system configuration for the entire evaluation using a user application board, IBM PC-AT personal computer or AX personal computer Amplifier L = L le) ——V RG = 7 OC ZA err RS232¢ Application board [ L, & Z| Audio source XA ZT o. Po 0 ™_ Figure A-8, Final evaluation system configuration with an application board and ICE ICE functions - The ICE has debugging functions. - The ICE consists of unique hardware functions specifically designed as the ICE for audio DSP. (a) ICE debugging functions (1) Execution command : Allows the program execution to continue until a break point is detected. It also enables the program execution in the step mode or in the trace mode. (2) Break function : Enables the user to set a desired break point. (3) The edit dump command is useful in displaying the conditions of a specified memory area after the break of program execution. The register edit command is used to convert the contents of a present specified register. (4) The memory dump command Is useful in displaying the contents of a specified memory area when the Program execution breaks. On the other hand, the edit command is used to edit the contents of a specified memory area when the program execution breaks. (5) Program modification and confirmation ; Enables the user to modify part of the program and to check how it works. (6) Other functions : Memory management facility and so on. For details, refer the sections following section 8-3. (b) Unique ICE hardware configuration (1) Audio data input/output : Digital Interface Receiver (DIR). This function allows direct input of audio digital data. Digital Interface Transmitter (DIT). This function allows direct output of 3-channel digital audio data. (2) DRAM : Delay DRAM for audio signal, 256k (64K x 4 bits) x 2. 1M (256K x 4 bits) x 2 {3) Evaluation function of serial input/output : Z80 microcomputer for evaluating seria! input/output. This control unit makes an access to the D2SP instead of any controlling microcomputer to adjust the serial input/output operations. eee No. 3945-18/20
LC83010N, 83010NE ee Example application system Cc — a | — a’a Ey oa SE bes | 8 =. 6°38 e [s) Ke} | ale 5 | | eee a|Slele Tlvlole. re ee ee ee a Ofiyacyes <[o]a}ie “OTe bd SSsssRsseegneers z o co ° a8 a 22 2. 85e $8 3 85 ENReTAR i ¥| oe a a aisle} «6 sls] § 8 Lisette aegis agi g else Ey is By 4 2 a 55) |2 | [a] 2 2 7 al re) 4 ey s = 2
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LC83010N, 83010NE Instruction Bit Map The instruction bit map is shown below, bob bbb bbb bbbbb bb bb bb b 3129 28 26 25 24 23 22 19 1816 15 141312 1110 6 5 0 ora fom] ws [8] oe | aww [orfor]or [a] see [oor | (Normal instruction) bb 5 4 wn leRel © PoE N= ({Vectored address jump instruction) ~ feleRt=|< [loli] La | (Return instruction) ver Lede [8] | aw [orforfo |e] sxe [oor | (Loop return instruction) bb b 24 23 19 ov [ele Bil = felee[ = [=] (Shift instruction) bbb bob b 28 27 26 22 21 11 (Jump instruction) (Call instruction) b b 28 5 (Load immedi- ate instruction) Instruction Bit Map diagram a eSSSSSSSSSSSSSSSSsSSSSSSSSeSS No, 3945-20/20