LC82221L SANYO | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 7
Technical content
Features
- High image quality image expansion using the JPEG system
- Superlative cost performance achieved by only providing decoding functions.
- Two built-in quantization tables.
- High-speed processing achieved by using fixed Huffman tables. Application do not have to set up these tables.
- Two Huffman tables, one for luminance data and one for chrominance data, are provided.
- Supports scaling factor parameters that allow the quantization factor to be changed.
- DRAM for code data buffering and image data playback can be connected directly.
- Applications can use either 2Mb or 4Mb DRAMs based on the sizes of the image handled and the structure of the system. However, 16-bit data path DRAMs must be used.
- Image data is output in synchronization with an image display synchronizing signal.
- Color structure of the code data is Y:U:V=4:1:1.
- Dedicated code data input bus provided to avoid loading the host bus. DMA transfers are also supported.
- Users can select either RGB or YUV for image data output.
- Built-in YUV to RGB color conversion circuit
- The LC82221L supports image sizes up to 1024 pixels in the horizontal direction. The range of vertical sizes handled can be set up arbitrarily, since it is limited by the size of the DRAM provided.
- 3.3-V single-voltage power supply. Low power.
- The display position and display size can be set.
- SOI and EOI marker support
- Horizontal and vertical scrolling display functions
- Support for overwrite display, in which the next data for expansion is displayed by overwriting the previously expanded image data Package Dimensions unit: mm 3214-SQFP144 CMOS IC 62698RM (OT) No. 5846-1/7 Preliminary SANYO: SQFP144 [LC82221L] SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN Motion JPEG Decoder LC82221L Ordering number : EN *5846
No. 5846-2/7 LC82221L
No. 5846-3/7 LC82221L Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD –0.3 to +4.6 V Input and output voltage VI, VO –0.3 to VDD +0.3 V Input and output current II, IO –20 to +20 mA Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Absolute Maximum Ratings at VSS = 0 V Specifications
Electrical Characteristics
Parameter Symbol Conditions Ratings Unit min typ max Supply voltage VDD 3.0 3.3 3.6 V Input voltage VIN 0 VDD V Allowable Operating Ranges at Ta = –30 to +70°C Parameter Symbol Conditions Ratings Unit min typ max Input high-level voltage VIH1 CMOS level inputs: (1)
0.7 VDD V
Input low-level voltage VIL1 0.2 VDD V Input high-level voltage VIH2 CMOS level Schmitt inputs: (2)
0.75 VDD V
Input low-level voltage VIL2 0.15 VDD V Input high-level current IIH VIN = VDD ; All input pins (including bus pins)–10 +10 µA Input low-level current IIL1 VIN = VSS : (3) –10 +10 µA IIL2 VIN = VDD ; Pins with pull-up resistors: (4)–100 –10 µA Output high-level voltage VOH IOH = –6 mA; All output pins VDD – 0.8 V(including bus pins) Output low-level voltage VOL IOL = 6 mA; All output pins
0.4 V(including bus pins)
Output leakage current IOZ When set to high-impedance output: (5) –10 +10 µA Pull-up resistance R UP (6) 70 140 280 kΩ DC Characteristics at Ta = –30 to +70°C, VDD = 3.0 to 3.6 V, VSS = 0 V Applicable Pins (1) CTLCPU, CTLA, CTLD, CLKSEL, CLK, CDD, TEST, MD, DG, DB, DR, ZPXEN, ZHSYNC, ZVSYNC, PXCLK (2) ZCTLCS, ZCTLRD, ZCTLWR, ZRESET, ZCDCS, ZCDWR (3) CTLCPU, CTLA, CTLD, CLKSEL, CLK, CDD, TEST, DG, DB, DR, ZPXEN, ZHSYNC, ZVSYNC, PXCLK, ZCTLCS, ZCTLRD, ZCTLWR, ZRESET, ZCDCS, ZCDWR (4) MD (5) ZCTLRDY, CTLD, ZCDRDY, MD, DG, DB, DR (6) MD
No. 5846-4/7 LC82221L Pin Number Pin Name Type Description
1 VSS Ground
2 ZCTLINT O Control bus interrupt request
3 ZCTLCS I Control bus select
4 ZCTLRD/RW I Control bus read or R/W select
5 ZCTLWR/DS I Control bus write/data strobe
6 ZCTLRDY O Control bus ready (tri-state output)
7 CTLCPU I Control bus CPU type selection
8 VDD +3.3-V power supply
9 VSS Ground
12 CTLA5 I
13 CTLA4 I
14 CTLA3 I
15 CTLA2 I
16 CTLA1 I
17 CTLA0 I
18 VDD +3.3-V power supply
19 VSS Ground
20 CTLD7 I/O
21 CTLD6 I/O
22 CTLD5 I/O
23 CTLD4 I/O
24 CTLD3 I/O
25 CTLD2 I/O
26 CTLD1 I/O
27 CTLD0 I/O
28 VDD +3.3-V power supply
29 VSS Ground
30 CLKSEL0 I Clock divisor setting
31 CLKSEL1 I CLKSEL1:0 = 00: No divisor, 01: Divisor = 2, 10: Divisor = 3.
32 CLK I System (decode) clock input
34 ZRESET I Hardware reset
36 VSS Ground
37 VDD +3.3-V power supply
38 ZCDCS/ZCDACK I Code bus select/code bus DMA acknowledge
39 ZCDINT/ZCDREQ O Code bus interrupt/code bus DMA request
40 ZCDWR I Code bus data write signal
41 ZCDRDY O Code bus ready (tri-state output)
42 CDD15 I
43 CDD14 I Code bus data
44 CDD13 I (CDD8 to CDD15 are unused in 8-bit mode.*)
45 CDD12 I
Continued on next page.Note: * These pins must be pulled up with a resistance of about 10 kΩ .
No. 5846-5/7 LC82221L Continued from preceding page. Pin Number Pin Name Type Description 46 VDD +3.3-V power supply
47 VSS Ground
48 CDD11 I
49 CDD10 I
50 CDD9 I
51 CDD8 I
52 CDD7 I
53 CDD6 I
54 VDD +3.3-V power supply
55 VSS Ground
56 CDD5 I
57 CDD4 I
58 CDD3 I
59 CDD2 I
60 CDD1 I
61 CDD0 I
62 VSS +3.3-V power supply
63 VDD Ground
67 TEST0 I
68 TEST1 I
69 TEST2 I Test pins *
70 TEST3 I
71 TEST4 I
72 VSS Ground
73 VDD +3.3-V power supply
74 ZOE O Memory output enable
75 ZWEL O Memory write enable (L)
76 ZRAS O Row address strobe
77 ZCASL O Column address strobe (L)
78 ZWEH/ZCASH O Memory write enable (H)/column address strobe (H)
79 VSS Ground
80 MD15 I/O
81 MD14 I/O
82 MD13 I/O
83 MD12 I/O
84 MD11 I/O
Frame memory interface data bus
85 MD10 I/O
86 MD9 I/O
87 MD8 I/O
88 MD7 I/O
89 MD6 I/O
90 VDD +3.3-V power supply Continued on next page.Note:* These pins must be tied to ground.
No. 5846-6/7 LC82221L Continued from preceding page. Pin Number Pin Name Type Description
91 VSS Ground
92 MD5 I/O
93 MD4 I/O
94 MD3 I/O
Frame memory interface data bus
95 MD2 I/O
96 MD1 I/O
97 MD0 I/O
98 VDD +3.3-V power supply
99 MA8 O
100 MA7 O
101 MA6 O
102 MA5 O
103 MA4 O Frame memory address signals
104 MA3 O
105 MA2 O
106 MA1 O
107 MA0 O
108 VSS Ground
109 VDD +3.3-V power supply
110 DG7 O
111 DG6 O
112 DG5 O
113 DG4 O
Pixel data bus G (U) *
114 DG3 O
115 DG2 O
116 DG1 O
117 DG0 O
118 VSS Ground
119 VDD +3.3-V power supply
120 DB7 O
121 DB6 O
122 DB5 O
Pixel data bus B (V) *
123 DB4 O
124 DB3 O
125 DB2 O
126 VDD +3.3-V power supply
127 VSS Ground
128 DB1 O
Pixel data bus B (V) *
129 DB0 O
130 DR7 O
131 DR6 O
Pixel data bus R (Y) *
132 DR5 O
133 DR4 O
134 VSS Ground
Continued on next page.Note: * These pins must be pulled up with a resistance of about 10 kΩ .
PS No. 5846-7/7 LC82221L This catalog provides information as of June, 1998. Specifications and information herein are subject to change without notice. n No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n Anyone purchasing any products described or contained herein for an above-mentioned use shall: À Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: \` Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. Continued from preceding page. Pin Number Pin Name Type Description
135 DR3 O
136 DR2 O
Pixel data bus R (Y) *
137 DR1 O
138 DR0 O
139 ZPXEN I Pixel data enable signal
140 ZBLANK O Blanking signal
141 ZHSYNC I Horizontal synchronizing signal
142 ZVSYNC I Vertical synchronizing signal
143 PXCLK I Pixel clock
144 VDD +3.3-V power supply Note:* These pins must be pulled up with a resistance of about 10 kΩ .