LC82141

LC82141 SANYO | Alldatasheet

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SANYO Facsimile Controller Prefiminary Overview Package Dimensions The LC82141 is a facsimile controller comprising a CPU, unit: mm CPU peripheral circuits, image processor, dot change detector for image data compression and expansion, ther- 3153-QFP160E mal print head interface, I/O ports and other facsimile [082144] functions on a single chip. It can be connected to a 9,600bps modem (LC8920, LC89201) or a 14,400bps te at as modem (C8921) and RAM, ROM, LCD controller and tes 1 ms >. _ oe other circuits to form a high performance, low cost facsim- she Tt] 8 lS iS [| ile system Lj soagom lati nest |: aa Features fe E ls * High-speed 16-bit CPU (65C816), 8MHz cycle = E ale fe * 16MB program space x E * 3-channel DMA controller (2.6MB/s max.) E * 6-channel 16-bit timer = = i" | * 4096 pels/line image processing | s PTET ETE TTT ———}—. i * 64-gradation half-tone processing (dither method, error { gle ° 2 diffusion method) 2] emo |= * Shading correction for all pels bls * AGC, 8-bit A/D converter SANYO : QFPI60E * Soft codec accelerator * TPH interface (1,2,4 strobe divisions, latchless head) + Transmit/receive stepping motor interface * 32/0 ports * Single 5V supply + CMOS process for low-power dissipation SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N1194TH (ID) No. 4914—1/9

ALN, ATAP, SH, RS, ASAMP, ICLK (PD3) ACLK1, ACLK2 $2,RES, VW TRG,VP.roy |. | cpu Image > re BE, NMi, VPA 65C816 Processing Tio WR VDA, EMU _— RD, WR, MSEL ROMCS, RAMCS TOTS, LESO, CPU CODEC Ttsi Interface Accelarator BREQ(PDO) BACK(PD1) EXRDY (PB7) PATO PC3-0 TCLKO(PC4) SPCLK (PD2) STB3-0(PF3-0) PCK(SCLK) INTO PDATA (TXD) 2 Interrupt INTIS CATCH RxD) + TPH UE Controller INT16(PC6) EXCLK (PF4) INTI7(PC7) HVON PROTECT TM3.0(PE3.0) ur DRAM RAS (PFs) RM3-0(PE7-4) « > Motor Controller TAS (PF6) CLKIN CLKOUT DT7.0 RESET A19-0 BACKUP ‘A23-20(PDT-4) TESTI-0 Pin Functions a [4 | ROMS | __O__| Program ROM chip selec signal eee No. 4914—2/9

a a ; 7 | two | o | External /O chip select signals ee a a i ee ee ee [=| [ee a ee a OO [2 men [=| wie | 8 | Address bus/Generat-purpose port D [= ron ee [ae [ee a a a A [Fit ip a a A a a a a a A a [sper ton ee a ee a a Address bus a a [ee a ig, 40188

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a ee a ee ee ‘Transmit motor phase signals/General-purpose port E [9 [ee [3 i [| rececin| a [rattan etiiaocex | A [| aero) | a denna a [| ser | assent ‘Thermal head strobe signals/General-purpose port F [8 [Sen [|e | a a a ee es a a a Image processor memory data bus ee ee a ee ee ee a ee : eee enemas a RD a Dc Psa [Battin cemererretrece tage pe Tass [Pin grondcemnesog a a a a a a ig, 4018

[__Nember Tame testo pe a a psa [96 [wD ~——«O | Image precessormemory address bus a a a pe Sn po Ms PP [Stunt csrectonpin [| we ser) 8 <= DRAM address strobes/General-purpose port F oe oe ee een ee a ee a ee Image processor memory address bus a a [=o a [2 [acre [8 rae reerenlcaciamaren | [8 [sara [8 | Sntreneaowninuraepn® ee i [| end os a a a a 1.1 input, B = bidirectional, O = output, P = power Specifications Absolute Maximum Ratings at Vss = 0V [Parameter Symbot | Conttons Tain ant [Aloabiepowerdsspaton | Pamax |nsmo Tw | Opeaingtempertwe | torr ft SS Soldering temperature Tsol [ecw | Samet — Allowable Operating Ranges at T, = —30 to +70°C, Vsg = OV [Parmeter [Sambo Conon in ve tee Tt] [Seni me a [Womotags wo PT 0, 491009

a DC Characteristics at T, = -30 to +70°C, Vpp = 4.5 to 5.5V [Parameter Sumbol_— [| Conctons in |p Tote : PCK (SCLK), Schmitt trigger Input high-level voltage Vive input Vv PCK (SCLK), Schmit ti a ua high evel votege a put eakapecurent [tox | Harimpesenco ouput | -100 | | etm Tm a Osc reuery foucroumorout [= fT Te [ts [ae [a | | Current dissipation Power-down, Vog = 2V, BACKUP = LOW w Function Outline CPU Peripheral Circuits * correction (user-definable curve) | __* Simple two-value processing (fixed threshold value, * Generates 80-series CPU compatible CS/RD/WR sig- —_density-adjusted threshold value) nals ; * Half-tone processing * Chip select signal outputs for program ROM, SRAM systematic dither method (64 gradations), dither and I/O device connections ; . threshold value adjustable * ROM, SRAM and DRAM sizes settable in 64KB units - Error diffusion method (64 gradations) * Inserts wait cycles when accessing ROM, SRAM and Image reduction (thinning out, black fine line hold, vo oo. white fine line hold) * Internal/external DMA controller bus arbitration func- tion Codec Accelerator Image Processor + Image data dot change detection, run-length or line start absolute address output * Number of processed picture elements. (pels) + Run-length image data coding - 2048 pels/line (uses 64K memory, with black and. \\fayimum 4K run-length processing white correction) . . * Image data DMA transmission capability - 4096 pels/line (uses 64K memory, with white correc- tion only) ; TPH Interface ~ 4096 pels/line (uses 256K memory, with black and | wis, onsets, IMHz and SO0kHLz transmission clock white correction) frequency * 500ns/pel max. processing rate + Switchable rising-edge/falling-edge clock phase * Lexternal, medium-speed memory + Strobe division: 1, 2, and 4 = 100ns access time at 500ns/pel rate > ‘Strobe widhy 3210 to 8.16ms * Various kinds of clocks ‘i tr , i . * Switchable strobe and latch pulse polarity - /8 ft internal clock mode, with 1, 172, U4, 1/8 frequency | ote and latch pulse can be generated manually and ivision capability . ional 1 clock treated as a general-purpose output port - External clock mode, with optional external cloc! + Head supply ON/OFF control input capability . . Head ion i i + AGC, &-bit A/D converter built-in (with delay adjust * Head prosection input pin OROVECT) setup ive function) 7 + . . * Thermal printer head temperature monitor function maevelge ts Jow-level input of approxi * Sensor drive circuit (CCD, various CIS types) - Mode 2: HVON and STBO to STB3 are set to inactive * Digi - at “ Digital clamp (dot clamp, even-odd clamp) state immediately after a low-level signal input. * Distortion correction (white, black, all pels) TO NG, 491479

Motor Interface DRAM Controller * Transmit/receive 2-channel stepping motor interface * 256K/1M/4Mb DRAM support, up to 120ns access time * 4-phase motor (excitation method: | phase/2 phases/1-2 supported phases) * CAS-before-RAS refresh * Forward/reverse-selectable control register + Employs early-write mode * Motor output polarity selectable * Internal refresh counter: 4ms refresh time for 256K, * 2 phase change triggers (register-selectable) for both 8ms for IM, 16ms for 4M transmit and receive + Register setting capability for 9 dummy refresh cycle - Transmit motor trigger execution Phase change by register bit ON/OFF Interrupt Controller Phase change by image processor-controlled motor phase advance trigger + 18-level interrupt control (internal: 14 levels, external: 4 - Receive motor trigger levels) Phase change by register bit ON/OFF * Individual level mask processing Phase change by timer 3 output * Interrupt vector address output DMA Controller RTC * 3-channel transmission, memory + I/O * Time function with alarm - Channel 0: Image processor > memory * 100-year calendar - Channel 1: Codec accelerator +» memory * 12-hour/24-hour time display, summer time set capabil- - Channel 2: Memory > TPH interface ity * Channel 2 supporting a latchless head + Leap year, short/long month auto-correction * 16MB addresses/64K transfer count * Selectable binary or BCD data for time, calendar and + 2.6MB/s max. transfer speed alarm + Individual DMA request permit/prohibit * 3 types of interrupts * Auto-initialization function - Alarm interrupt * Fixed precedence order: channel 0 > channel 1 > chan- - Periodic interrupt nel 2 - Update ended interrupt Timer General-Purpose Ports * 6 independent 16-bit counters on-chip * 20 to 32 input/output ports * 8-bit prescaler on-chip for each counter + Each port can be configured as an input or output * 244Hz to 15.6kHz speaker clock generator + Extendable up to 47 ports by switchover to dedicated * External clock inputs selectable for timer 0 and timer 1 pins No. 4914—8/9

Sample Application Circuit MODEM memory Lc89201 Lc8g2t Manuscript Public tine Fluorescent : Facsimile light controller Telephone Stepping Image motor Lens sensor j<>| RAM Motor driver 82141 >| Temperature sensor : Cutter CI . Thermal head & To LCD oo Steppi oo fepping motor Recording ool o paper To key-matrix oo IENo products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. M Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO,, LTD, its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO. LTD. its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Mi Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of : third parties. No. 4914—9/9