LC7940KD

LC7940KD SANYO | Alldatasheet

Document overview

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Technical content

Features

• 80 built-in LCD display drive circuits
• 1/8 to 1/128 display duty cycle
• Serial or 4-bit parallel data input
• Chip disable for low power dissipation for large-sized panels
• Bias supply voltage can be supplied externally
• Operating supply voltage and ambient temperature VDD (logic block): 2.7 to 5.5V/-20 to +85°C VDD-VEE (LCD block): 8 to 20V/-20 to +85°C
• CMOS process
• Package: QIP100D(LC7940KD)/QIP100DR(LC7941KDR) CMOS IC Dot-Matrix LCD Drivers Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated val ues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.

No.A0573-2/13 Package Dimensions unit: mm (typ) 3180 [LC7940KD] Package Dimensions unit: mm (typ) 3329 [LC7941KDR] SANYO : QIP100D(14X20) 21.6 0.8 2.45max 1.6 17.2 0.15 2.15 15.6 0.3 14.0 0.65 0.825 100 0.813 0 5180 1.6 0.575 20.0 23.2 0.65 20.0 0.1 14.0 17.2 23.2 0.8 13 0 5180 100 0.65 (0.58)(2.15) 2.45MAX 0.3 0.15 SANYO : QIP100DR(14X20)

No.A0573-3/13 Pin Assignment LC7940KD O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 O62 O63 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 81 NC CDO NC DISPOFF P/S VSS VEE NC VDD M DI1 DI2 DI3 SDI LOAD CDI CP Top view LC7941KDR VEE M LOAD VSS DISPOFF VDD P/S NC NC NC SDI DI3 DI2 DI1 CP CDO CDI O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 O31 O32 O33 O34 O35 O36 O37 O38 O39 O40 O41 O42 O43 O44 O45 O46 O47 O48 O49 O50 100 O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Top view

No.A0573-4/13 Block Diagram O79 O80 VEE M P/S CP CDO VSS VDD LOAD CDI Address Decoder 4 bits Data Bus Interface Level Shifter (80 bits) 2nd Latch (80 bits)

4 Level LCD Drive Circuit

(80 bits) 1st Latch (80 bits) 4 20 Address Counter (7bits) Chip Disable & Latch Control SDI DI3 DI2 DI1 SER/PAR Control DISPOFF

No.A0573-5/13 Pin Function Pin No LC7940KD LC7941KDR Symbol I/O Function 91 90 V DD 86 95 V SS 87 94 V EE Supply LCD panel drive voltage supplies VDD-VSS is the logic supply. VDD-VEE is the LCD supply. 92 89 V1 89 92 V3 88 93 V4 Supply LCD panel drive voltage supplies V1 and VEE are selected levels. V3 and V4 are not-selected levels. 100 81 CP I Display data input clock (falling edge trigger). 99 82 CDI I Chip disable. Data is read in When LOW, and not read in When HIGH. 98 83 LOAD I Display data latch clock (falling edge trigger). On the falling edge, the LCD drive signals set by the display data are output. 97 84 SDI I Serial data input.

85 DI3 I

86 DI2 I

87 DI1 I

4-bit parallel data input pins. Data input LCD driver output SDI O4 O8 O80 DI3 O3 O7 O79 DI2 O2 O6 O78 DI1 O1 O5 O77 In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW. 93 88 M I LCD panel drive voltage output alternation control signal. 85 96 P/S I Data input mode select. 4-bit parallel input when HIGH, and serial input when LOW. 82 99 CDO O Cascade connection pin fo r extension segment drivers. Data is read out when HIGH. Goes LOW after data is read out. Connected to the CDI input of the next chip. 1 to 80 80 to 1 O1 to O80 O LCD drive outputs. The output drive level is determined by the display data, M signal and DISPOFF input as shown below. M Q DISPOFF Output L L H V3 L H H V1 H L H V4 H H H V EE * * L V1 Note* don’t care (tied HIGH or LOW) 84 97 DISPOFF I O1 to O80 output control input pin. When LOW, V1 is output on the O1 to O80 outputs. See the truth table. 81 91 NC 83 98 NC 90 100 NC - No connection.

No.A0573-6/13 Specifications Absolute Maximum Ratings at Ta=25±2°C, VSS = 0V Parameter Symbol Conditions Ratings Unit Maximum supply voltage (logic) V DD max - -0.3 to +7.0 V Maximum supply voltage (LCD) V DD-VEE max *1 0 to 22 V Maximum input voltage V I max - -0.3 to VDD +0.3 V Operating temperature range Topr - -20 to +85 °C Storage temperature range Tstg - -40 to +125 °C Note *1 The following relations between elements should be maintained: VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V Allowable Operating Ranges at Ta = -20 to 85°C, VSS = 0V Ratings Parameter Symbol Conditions min typ max Unit Supply voltage (logic) V DD - 2.7 - 5.5 V Supply voltage (LCD) V DD-VEE *2, 3 8 - 20 V Input high level voltage V IH CP, CDI, DI1 to DI3, M, SDI, P/S, DISPOFF, and LOAD 0.8VDD - - V Input low level voltage V IL CP, CDI, DI1 to DI3, M, SDI, P/S, DISPOFF, and LOAD - - 0.2V DD V CP Shift clock frequency f CP CP - - 3.3 MHz CP pulse width t WC CP 100 - - ns LOAD pulse width t WL LOAD 100 - - ns DIn and SDI to CP setup time t SETUP DIn and SDI to CP 80 - - ns DIn and SDI to CP hold time t HOLD DIn and SDI to CP 80 - - ns tCL1 CP to LOAD 0 - - ns CP to LOAD time tCL2 CP to LOAD 100 - - ns LOAD to CP time t LC LOAD to CP 100 - - ns CP rise time t R CP - - 50 ns CP fall time t F CP - - 50 ns LOAD rise time t RL LOAD - - 50 ns LOAD fall time t FL LOAD - - 50 ns Note *2 The following relations between elements should be maintained: VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V *3 When the power is turned on, either the logic system power must be turned on before the LCD drive system power or else they must both be turned on at the same time. When the power is turned off, either the LCD drive system power must be turned off before the logic system power, or else both must be turned off at the same time.

No.A0573-7/13 Electrical Characteristics at Ta = 25±2°C, VDD = 2.7 to 5.5V Ratings Parameter Symbol Conditions min typ max Unit Input high level current I IH V IN = VDD: LOAD, CP, CDI, P/S, DI1 to DI3, SDI, M, and DISPOFF - - 1 µA Input low level current I IL V IN = VSS: LOAD, CP, CDI, P/S, DI1 to DI3, SDI, M, and DISPOFF -1 - - µA Output high level voltage V OH I OH = -400µA: CDO VDD-0.4 - - V Output low level voltage V OL I OL = 400µA: CDO - - 0.4 V Driver on resistance R ON V DD-VEE = 18V, |VDE-Vo| = 0.25V *4 - 0.7 2 k Ω Standby current drain I ST CDI = V DD, VDD-VEE = 18V, CP = 3.3MHz, Output unloaded: VSS - - 200 µA ISS *5 V DD-VEE = 18V, CP = 3.3MHz, LOAD = 5.156kHz M = 52Hz: VSS - - 1.0 mA Operating current drain IEE *6 V DD-VEE = 18V, CP = 3.3MHz, LOAD = 5.156kHz M = 52Hz: VEE - - 0.1 mA Note *4 VDE = one of V1, V3, V4 or VEE. V1 = VDD, V3 = 9/11(VDD-VEE), V4 = 2/11(VDD-VEE) *5 ISS is the current flowing from VDD-VSS. *6 IEE is the current flowing from VDD-VEE Switching Characteristics at Ta = 25±2°C, VSS = 0V, VDD = 2.7 to 5.5V Ratings Parameter Symbol Conditions min typ max Unit Output delay time t D CL=30pF: CDO - - 200 ns Switching Characteristics Diagram 0.8VDD 0.2VDD 0.8VDD 0.2VDD 0.2VDD 0.8VDD 0.8VDD 0.2VDD tR tWC t F tWC CP SDI DI1 to 3 tSETUP tHOLD tCL(1) tCL(2) tRL tFL LOAD tWL tLC tD tD CDO

No.A0573-8/13 Application Notes LCD Panel1

• • • • LCD Panel (240×100 Pixels) VDD + - VEE R R R R FLM M LOAD CP Serial Data 100 DIO1 O1 O36 M CP LC7942KD Controller V1 V2 V5 VEE V1 V3 V4 VEE LC7940KD-#3 LC7940KD-#2 LC7940KD-#1 M V1 V3 V4 VEE M V1 V3 V4 VEE V1 V3 V4 VEE M CDI CP SDI LOAD LOAD CP Serial Data 240 239 161 • • • • 160 159 81 • • • • 2 • • • • DIO1 O1 O64 DIO64 M CP LC7942KD V1 V2 V5 VEE CDI CDO CDO CDI + - + - + -

No.A0573-9/13 Application Notes LCD Panel2

• • • • LCD Panel (640×200 Pixels) VDD + - VEE R R R R 4bit Data FLM M LOAD CP 4bit Data DIO1 O1 O64 DIO64 M CP 100 DIO1 O1 O36 M CP Controller V1 V2 V5 VEE 6 V1 V3 V4 VEE LC7941KDR-#1 M CP LOAD LC7940KD-#8 M V1 V3 V4 V EE CDI CDO CDI CP LOAD 4bit Data V1 V3 V4 VEE LC7941KDR-#2 LC7941KDR-#8 2 4 2 2 4 2 4 LC7940KD-#2 4bit Data LC7940KD-#1 2 4 2 CDO LC7942KD-#1 LC7942KD-#2 4 2 4 2 Power supply circuit O1 O80 O1 O80

No.A0573-10/13 100×240-Pixel LCD Panel Application A100×240-Pixel LCD Panel requires the following drivers.

• 3×LC7940KD (or LC7941KDR) drivers
• 2×LC7942KD drivers An example using 1/100 duty cycle is shown below. (1) The LC7942KD chips are cascaded by connecting DIO64 on chip 1 to DIO1 on chip 2. For a 100-bit shift register, O37 to O64 on chip 2 are left open. (2) The LC7940KD (or LC7941KDR) chips are cascaded by connecting CDO on chip 1 to CDI on chip 2, and CDO on chip 2 to CDI on chip 3. CDI on chip 1 is tied to GND, and CDO on chop 3 is not used. This configulation allows the input of 240-bit serial data. 1,1 1,2 1,79 1,80 1,81 1,82 1,160 1,161 1,240 2,1 2,2 2,240 ∼ ∼ ∼ 63,1 63,2 64,1 64,2 65,1 65,2 66,1 66,2 64,80 64,81 65,80 65,81 64,160 64,161 65,160 65,161 64,240 65,240 100,1 100,2 100,79 100,80 100,81 100,82 100,160 100,161 100,240 O63 O64 DIO1 RS/LS CP M DIO64 LC7942KD O36 DIO1 RS/LS CP M DIO64 LC7942KD O1 O2 O79 O80 CDI CDO LC7940KD (LC7941KDR) #1 P/S DI1 DI2 DI3 SDI CP LOAD M O1 O2 O80 CDI CDO P/S DI1 DI2 DI3 SDI CP LOAD M O1 O80 CDI CDO P/S DI1 DI2 DI3 SDI CP LOAD M ∼ ∼ ∼ ∼ ∼ ∼ ∼ Frame signal 1,79 (m, n): Pixel address Segment line (n) Common line (m) O37 to 64 are open. Data latch clock Alternating signal Serial data Data shift clock LCD Panel (100×240 Pixels) LC7940KD (LC7941KDR) #2 LC7940KD (LC7941KDR)

No.A0573-11/13 100×240-pixel LCD Panel Timing Diagram 1,1 1,2 1,79 1,80 1,81 1,160 1,161 1,240 M LOAD CP SDI CDO Chip 1 data read Chip 2 data read Chip 3 data read ∼ ∼ ∼ 1 line (240 bits) M LOAD CP SDI 1,1 1,2 ∼ 1,239 1,240 2,1 ∼ 2,240 3,1 ∼ 100,240 1st line data read 2nd line data read 1 frame (100×240 bits) M #1 DIO1 LOAD O80 ∼ 1,1 1,2 1,80 1,81 1,160 1,161 2,1 2,2 2,80 2,81 2,160 1,240 2,161 2,240 98,1 98,2 98,80 98,81 98,160 98,161 98,240 99,1 99,2 99,80 99,81 99,160 99,161 99,240 100,1 100,2 100,80 100,81 100,160 100,161 100,240 1,1 1,2 1,80 1,81 1,160 1,161 1,240 99,1 99,2 99,80 99,81 99,160 99,161 99,240 100,1 100,2 100,80 100,81 100,160 100,161 100,240 O80 O80 ∼ ∼ LCD driver output data

No.A0573-12/13 Segment Data Not Multiples of 4 Example. If this timing data is sent, data elements (m, 229), (m, 230), (m+1, 229),(m+1, 230)… will not appear in the output (O69 and O70 on chip 3). This is because the LC7940KD (or LC7941KDR) converts serial/parallel data in 4-bit units, which also decrease power dissipation. For data that is not a multiple of 4, like 230, the following scheme is used. In this case, (m, 231) is output on O71 on chip 3, and (m, 232) on O72 on chip 3. However, these outputs are not connected to the panel and are, therefore, invalid. LOAD SDI ∼ O1 O80 LC7940KD O1 O80 LC7940KD O1 O70 LC7940KD LCD Panel (100×230 pixels) ,228 ,228 m+1,230 m,1 m,2 m,229 m,230 m,231 LOAD SDI ∼ ,228 m,232 Valid display data Dummy data Multiple of 4

No.A0573-13/13 PS This catalog provides information as of November, 2006. Specifications and information herein are subject to change without notice. Specifications of any and all SANYO Semiconductor pr oducts described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify s ymptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high- quality high-reliability products. However, any and all semiconductor products fail with some probabi lity. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property . When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor produc ts (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording , or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circui t parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semicondu ctor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.