LC79401KNE SANYO | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

Features

  • Incorporates LCD drive circuits for 80 bits of display.
  • Supports display duties from 1/64 to 1/256
  • The provision of a chip disable pin supports power reduction in large-scale panels.
  • Allows external provision of the bias power supply
  • Operating supply voltage/operating temperature VDD (logic block) : 2.7 to 5.5V/-20 to +85°C VDD-VEE (LCD block) : 12 to 32V/-20 to +85°C
  • Data transfer clock : 6.0MHz (max), bidirectional shifting supported
  • Data input : 4-bit parallel input
  • CMOS process
  • 100-pin flat plastic package (QIP100E) CMOS LSI Dot-Matrix LCD Drivers Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer 's products or equipment. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appli ances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliab ility and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use.

No. A1419-2/8 Specifications Absolute Maximum Ratings at Ta = 25±2°C, VSS = 0V Parameter Symbol Conditions Ratings unit Maximum supply voltage (Logic) V DD max -0.3 to +7.0 V Maximum supply voltage (LCD) V DD-VEE max *1 0 to 35 V Maximum input voltage V I max -0.3 to V DD+0.3 V Storage temperature Tstg -40 to +125 °C Note *1 VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V Allowable Operating Ranges at Ta = -20 to +85°C, VSS = 0V Parameter Symbol Conditions min typ max unit Supply voltage (Logic) VDD 2.7 5.5 V Supply voltage (LCD) VDD-VEE *2, 3 12 32 V Input high level voltage V IH DI1 to DI4, CP, LOAD, CDI, R/L, M, DISPOFF 0.8VDD V Input low level voltage V IL DI1 to DI4, CP, LOAD, CDI, R/L, M, DISPOFF 0.2V DD V CP Shift clock f CP CP 6.0 MHz CP pulse width t WC CP 50 ns LOAD pulse width t WL LOAD 50 ns Setup time t SETUP DI1 to DI4 → CP 30 ns VDD=2.7 to 4.5V 40 ns Hold time tHOLD DI1 to DI4 → CP VDD=4.5 to 5.5V 30 ns CP → LOAD t CL CP → LOAD 80 ns tLC1 LOAD → CP 110 ns VDD=2.7 to 4.5V 30 ns LOAD → CP tLC2 LOAD → CP VDD=4.5 to 5.5V 15 ns CP and LOAD rise time t R CP, LOAD *4 ns CP and LOAD fall time t F CP, LOAD *4 ns Note *2 VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V *3 When the power is turned on, either the logic system power must be turned on before the LCD drive system power or else they must both be turned on at the same time. When the power is turned off, either the LCD drive system power must be turned off before the logic system power, or else both must be turned off at the same time. *4 The CP and LOAD rise time (tR) and the CP and LOAD fall time (tF) must satisfy equations (1) and (2) below at the same time. (1) tR, tF < 1 2fCP - tWC (2) t R, tF < 50ns

No. A1419-3/8 Electrical Characteristics at Ta = 25±2°C, VDD = 2.7 to 5.5V Parameter Symbol Conditions min typ max unit Input high level current I IH V IN=VDD, LOAD, CP, CDI, R/L, DI1 to DI4, M, DISPOFF 1 μA Input low level current I IL V IN=VSS, LOAD, CP, CDI, R/L, DI1 to DI4, M, DISPOFF -1 μA Output high level voltage VOH I OH=-400μA, CDO V DD-0.4 V Output low level voltage V OL I OL=400μA, CDO 0.4 V RON(1) V DD-VEE=30V, ⎜VDE-VO⎜=0.5V: O1 to O80 *5 0.6 1.5 k Ω Driver on resistance RON(2) V DD-VEE=20V, ⎜VDE-VO⎜=0.5V: O1 to O80 *5 0.7 2.0 k Ω Standby current drain I ST CDI=V DD, VDD-VEE=30V, CP=6.0MHz, Output unloaded: VSS 200 μA Operating current drain ISS *6 V DD-VEE=30V, CP=6MHz, LOAD=14kHz, M=35Hz: VSS 4.0 mA I EE *7 V DD-VEE=30V, CP=6MHz, LOAD=14kHz, M=35Hz: VEE 0.5 mA Input capacitance C I f=6.0MHz ; CP 8 pF Note *5 VDE = one of V1, V3, V4 or VEE, V1 = VDD, V3 = 15/17 (VDD-VEE), V4 = 2/17 (VDD-VEE) *6 ISS is the current flowing from VDD to VSS *7 IEE is the current flowing from VDD to VEE Switching Characteristics at Ta = 25±2°C, VSS = 0V, VDD = 2.7 to 5.5V Parameter Symbol Conditions min typ max unit VDD=2.7 to 4.5V 100 ns Output delay time 1 t D1 Load=15pF: CDO VDD=4.5 to 5.5V 80 ns VDD=2.7 to 4.5V 100 ns Output delay time 2 tD2 Load=15pF: CDO VDD=4.5 to 5.5V 80 ns

No. A1419-4/8 Package Dimensions unit:mm (typ) 3151A Pin Assignment Top view SANYO : QIP100E(14X20) 20.0 23.2 14.0 17.2 0.15 0.8 (2.7) 3.0max 0.1 0.30.65 (0.58) 13 0 80 51 100 LC79401KNE O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 O62 O63 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100

81 CDI

M LOAD VSS DISPOFF VDD R/L NC NC NC DI4 DI3 DI2 DI1 CP CDO

No. A1419-5/8 Equivalent Circuit Block Diagram O79 O80 VEE M R/L CP CDO VSS VDD LOAD CDI Address Decoder 4 bits Data Bus Interface Level Shifter (80 bits) 2nd Latch (80 bits)

4 Level LCD Drive Circuit

(80 bits) 1st Latch (80 bits) 4 20 Address Counter (5bits) Chip Disable & Latch Control DI4 DI3 DI2 DI1 Shift Control DISPOFF

No. A1419-6/8 Pin Function Pin No Symbol I/O Function

90 V DD

88 V SS

85 V EE

Supply VDD-VSS : Logic power supply VDD-VEE : LCD drive circuit power supply 82 V1 83 V3 84 V4 Supply LCD drive level power supply V1,VEE : Selected level V3,V4 : Unselected level

99 CP I Display data acquisition clock (falling edge trigger)

87 LOAD I Display data latch clock (falling edge trigger)

The display data LCD drive signal is output on the falling edge. DI4 DI3 DI2 DI1 I Display data LCD drive output LCD display H Selected level On L Unselected level Off

91 R/L I

Control pin that inverts the data output destination Number of clock R/L Data input 1 2 3 • • • 18 19 20 DI1 O77 O73 O69 • • • O9 O5 O1 DI2 O78 O74 O70 • • • O10 O6 O2 DI3 O79 O75 O71 • • • O11 O7 O3 L DI4 O80 O76 O72 • • • O12 O8 O4 DI1 O4 O8 O12 • • • O72 O76 O80 DI2 O3 O7 O11 • • • O71 O75 O79 DI3 O2 O6 O10 • • • O70 O74 O78 H DI4 O1 O5 O9 • • • O69 O73 O77

86 M I LCD drive output alternation signal

81 CDI I

High level : Data is not acquired. Low level : Data is acquired 100 CDO O Connect to the CDI pin on the next chip when cascade connection is used. 89 DISPOFF I Input that controls the O1 to O80 output pins. During periods when this pin Is low, the O1 to O80 output pins output the V1 level. See the truth table. 1 to 80 O1 to O80 O LCD drive outputs The output level are determined by the combination of the output the data, The M signal, and The DISPOFF pin as shown in the table. M Q DISPOFF Output L L H V3 L H H V1 H L H V4 H H H V EE * * L V1 Note : don’t care (fixed at high or low) 92 NC 93 NC 94 NC - Must be left open.

No. A1419-7/8 R/L Seg318 Seg319 Seg320 Seg1 DIO1 DIO80 VDD VSS VEE Seg2 Seg3Com240 Com239 Com238 Com3 LCD PANEL 240×320 1/240 duty Power supply circuit Case of 1/n bias Com2 Com1LC79430KNE M RS/LS CP MODE DMIN DISPOFF DI1 to DI4 O1 to O80 O1 to O80 O1 to O80 O1 to O80O1 to O80 LC79401KNE LC79401KNE LC79401KNE M LOAD CP VEE VSS VDD CDI VEE VSS VDD CDI VEE VSS VDD CDI CDOCDOCDO R/L DISPOFF DI1 to DI4 M LOAD CP Controller FLM M LOAD GND VDD VEE R R CP DI1 to DI4 DISPOFF DISPOFF DIO1 DIO80 VDD VSS VEE LC79430KNE M RS/LS CP MODE DMIN DISPOFF R/L DISPOFF DI1 to DI4 M LOAD CP R (n-4)R R

No. A1419-8/8 Switching Characteristics Diagram PS SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. Regarding monolithic semiconductors, if you should intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a confirmation. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equ ipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of September, 2012. Specifications and information herein are subject to change without notice. 0.8VDD 0.2VDD 0.8VDD 0.2VDD 0.8VDD 0.2VDD 0.2VDD 0.8VDD 0.8VDD 0.2VDD tLC2 tR t WC t WC tF tSETUP t HOLD tR t WL t F tCL t LC1 tD1 tD2 CP DI1-DI4 LOAD CP CDO