LC7930N

LC7930N SANYO | Alldatasheet

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.Two channels of 20 output segment drivers .The configuration of 20 output segment drivers + 20 scanning terminal drivers available .A series data to connect with the microcontroller and three control signals .Able to be connected in series for large display .Built-in bidirectional shift register can be shifted in the direction that makes wiring easy .Operating supply voltage/ Operating temperature: V DD = 4.5 to 5.5 V / Topr = –20 to +75°C .Operating current drain : IDD = 1.0 mA max (Logic = 400 kHz, LCD = 1 kHz) .Package : Pin 60 Flat LC7930N : QIP60 Pin 64 Flat LC7930NW : SQFP64 Package Dimensions unit : mm 3055A-QFP60C [LC7930N] SANYO : QIP60C unit : mm 3190-SQFP64 [LC7930NW] SANYO : SQFP64 CMOS LSI LC7930N, 7930NW SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 13097HA(II)/12593JN/6031JN/6218TA,TS No.2778-1/7

Absolute Maximum Ratings a tT a=2 5± 2°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max –0.3 to +7.0 V VEE max V DD –13.5 to VDD +0.3 V Maximum input voltage V Imax –0.3 to VDD +0.3 V V1, V2, V3, V4, V5, V6 V EE to VDD +0.3 V Maximum output voltage V O max –0.3 to VDD +0.3 V Output transistor OFF, Y1 to Y40 V EE to VDD +0.3 V Allowable power dissipation Pd max 100 mW Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Note : Don’t soak the whole of IC into the tank filled with melted solder for soldering Allowable Operating Conditionsat Ta = –20 to +75°C, VSS =0V ,V EE =– 4t o– 6V Parameter Symbol Conditions min typ max Unit Supply voltage V DD VDD 4.5 5.5 V High-level input voltage V IH Note (1) 0.7V DD VDD V Low-level input voltage V IL Note (1) V SS 0.3VDD V Shift frequency f CL CLK SR 400 kHz High-level clock width t CWH CLK SR , CLKLA 800 ns Low-level clock width t CWL CLK SR 800 ns Data setup time t SU LDATA1, LDATA2, RDATA1, RDATA2 300 ns Clock setup time tSL CLK SR , CLKLA CLK SR → CLK LA 500 ns tLS CLK SR , CLKLA CLK LA → CLK SR 500 ns Clock transition time t ct CLK SR , CLKLA 200 ns Data retention time t DH LDATA1, LDATA2, RDATA1, RDATA2 300 ns Electirical Characteristicsat Ta = –20 to +75°C, VDD =+ 5V ± 10%, V SS =0V ,V EE =– 4t o– 6V Parameter Symbol Conditions min typ max Unit Input leakage current IIH Note (1) Vin = V DD 5µ A IIL Note (1) Vin = V SS –5 µA High-level output voltage V OH LDATA1, LDATA2, RDATA1, RDATA2 IOH = –0.4 mA V DD –0.4 V Low-level output voltage V OL LDATA1, LDATA2, RDATA1, RDATA2 IOL = 0.4 mA 0.4 V Vi to Yj voltage down Vd1 Y1 to Y40 Note (2) Ion = 100 µA, single output 1.1 V Vd2 Y1 to Y40 Note (2) Ion = 50 µA, all outputs 1.5 V Vi quiescent current IVH V1 to V6 Open output pins V i n=VDD 10 µA IVL V1 to V6 Open output pins V i n=VEE –10 µA Supply current IDD VDD Open output pins CLK SR = 400 kHz 1.0 mA IEE VEE Open output pins M=1k H z 10 µA Output propagation delay time tPD LDATA1, LDATA2, RDATA1, RDATA2 C L = 15 pF 500 ns Note (1): Applied to the pins; CLKSR , CLKLA , LDATA1, RDATA1, LDATA2, RDATA2, M, L/R1, L/R2, CH2-BP (2): The equivalent circuit between Vi to Yj (i=1t o6 ,j=1t o4 0 ) LC7930N, 7930NW No.2778-2/7

Internal Equivalent Circuit LCD driver (Channel 1) 20-bit latch 20-bit bidirectional shift register 20-bit bidirectional shift register 20-bit latch LCD driver (Channel 2) LC7930N, 7930NW No.2778-3/7

[LC7930N] Number Name Input/Output Number Name Input/Output Number Name Input/Output

1 Y30 Output 21 Y14 Output 41 RDATA1 Input/Output

2 Y31 Output 22 Y13 Output 42 LDATA2 Input/Output

3 Y32 Output 23 Y12 Output 43 RDATA2 Input/Output

4 Y33 Output 24 Y9 Output 44 N.C. —

5 Y34 Output 25 Y10 Output 45 M Input

6 Y29 Output 26 Y11 Output 46 L/R1 Input

7 Y28 Output 27 Y8 Output 47 L/R2 Input

8 Y27 Output 28 Y7 Output 48 CH2-BP Input

9 Y26 Output 29 V

DD — 49 V1 Input

10 Y25 Output 30 Y6 Output 50 V2 Input

11 Y24 Output 31 Y5 Output 51 V3 Input

12 Y23 Output 32 Y4 Output 52 V4 Input

13 Y22 Output 33 Y3 Output 53 V5 Input

14 Y21 Output 34 Y2 Output 54 V6 Input

15 Y20 Output 35 Y1 Output 55 Y40 Output

16 Y19 Output 36 V

EE — 56 Y39 Output

17 Y18 Output 37 CLK LA Input 57 Y38 Output

18 Y17 Output 38 CLK SR Input 58 Y37 Output

19 Y16 Output 39 V SS — 59 Y36 Output

20 Y15 Output 40 LDATA1 Input/Output 60 Y35 Output

[LC7930NW] Number Name Input/Output Number Name Input/Output Number Name Input/Output

1 V5 Input 23 Y6 Output 45 Y26 Output

2 V4 Input 24 V

DD — 46 Y27 Output

3 V3 Input 25 Y7 Output 47 Y28 Output

4 V2 Input 26 Y8 Output 48 Y29 Output

5 V1 Input 27 Y11 Output 49 N.C. —

6 CH2-BP Input 28 Y10 Output 50 Y34 Output

7 L/R2 Input 29 Y9 Output 51 Y33 Output

8 L/R1 Input 30 Y12 Output 52 Y32 Output

9 M Input 31 Y13 Output 53 Y31 Output

10 RDATA2 Input/Output 32 N.C. — 54 Y30 Output 11 LDATA2 Input/OUtput 33 Y14 Output 55 N.C. — 12 RDATA1 Input/Output 34 Y15 Output 56 N.C. —

13 LDATA1 Input/Output 35 Y16 Output 57 Y35 Output

SS — 36 Y17 Output 58 Y36 Output

15 CLK SR Input 37 Y18 Output 59 Y37 Output

16 CLK LA Input 38 Y19 Output 60 Y38 Output

17 V EE — 39 Y20 Output 61 Y39 Output

18 Y1 Output 40 Y21 Output 62 Y40 Output

19 Y2 Output 41 Y22 Output 63 V6 Input

20 Y3 Output 42 Y23 Output 64 N.C. —

21 Y4 Output 43 Y24 Output

22 Y5 Output 44 Y25 Output

LC7930N, 7930NW No.2778-4/7

VDD Logic circuitry power supply (+5 V±10%) VSS 0V VEE LCD driver power supply (–4 to –6 V) Y1 to Y20 Channel 1 LCD driver output pins Y21 to Y40 Channel 2 LCD driver output pins V1, V2 Reference voltage for selected driver outputs V3, V4 Reference voltage for non-selected driver outputs (channel 1) V5, V6 Reference voltage for non-selected driver outputs (channel 2) L/R1 Shift direction for channel 1 shift register L/R2 Shift direction for channel 2 shift register LDATA1 RDATA1 Serial data input/output pins for channel 1 shift register LDATA2 RDATA2 Serial data input/output pins for channel 2 shift register M Switching clock signal for LCD driver. CLK LA Latches channael 1 data on the falling edge. This also will latch channel 2 data on the falling edge if CH2-BP is low. CLK SR Shift channel 1 data on the falling edge. This also will shift channel 2 data on the falling edge if CH2-BP is low. CH2-BP Switches the mode of channel 2. Exchanges the latch signal for the shift signal of channel 2 and invert the M signal. Channel 2, then, can be used as a scan-line driver. L/R1 LDATA1 RDATA1 High-level Output Input Low-level Input Output L/R2 LDATA2 RDATA2 High-level Output Input Low-level Input Output CH2-BP Channel 2 M Latch Shift High CLK SR CLK LA M For scan-line driver Low CLK LA CLK SR M For signal line driver Functional Description LC7930N, LC7930NW are serial data transfer type LCD drivers. Data inputted serially from the data pin is shifted successively by the synchronizing clock (CLKSR ) and latched by the latch clock (CLK LA ) when the all data are shifted. .Segment terminal When CH2-BP goes to low, the data of channel 1 and channel 2 are shifted at the falling edge of CLK SR , and then latched at the falling edge of the CLKLA . The reference pulse will be switched to selected or unselected due to the latched data. .Scan terminal When CH2-BP goes to high, the data of channel 2 is shifted at the rising edge of CLK LA , and then latched at the rising edge of the CLKSR . When FLM signal, as a data, is inputted, the output will be scan terminal drive mode. Continued on next page. LC7930N, 7930NW No.2778-5/7

Continued from preceding page. Table 1. LCD Driver Output V oltages (V1 to V6) for Y1 to Y40

(Although the LCD divided voltage generator circuit is not shown here.) (1) 40-segment bar-graph display (static) (2) 6-digit, 7-segment + sign display. (1/3 duty cycle, 1/3 voltage bias) (3) 20 × 60 pixel graphic display. (1/20 duty cycle, 1/5 voltage bias) No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1997. Specifications and information herein are subject to change without notice. 4-bit micro- controller Output port4 lines 40 lines Drive controller 3 lines 4-bit micro- processor Output port 5 lines 3 lines 20 lines (3 lines/1 digit) Drive controller 20 lines 20 × 60 dots 20 lines 40 lines 8-bit microprocessor or dedicated controller 3 lines 3 lines 3 lines LC7930N, 7930NW No.2778-7/7