LC78684E

LC78684E SANYO | Alldatasheet

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Features

x MP3 Decoding Functions (MPEG audio standard [ISO/IEC 11172-3] layer 3) Decodes to a digital audio signal MP3 data decoded by the CD-ROM decoder and outputs that audio signal. Supports all bit rates, including variable bit rate operation. Supports the following sampling rates. MPEG1 (Fs = 32 K, 44.1 K, 48 K) MPEG2 (Fs = 16 K, 22.05 K, 24 K) MPEG2.5 (Fs = 8 K, 11.025 K, 12 K) Can read out the MPEG header and ancillary data. Automatically mutes the signal on CRC errors using an MP3 CRC check function. External MPEG serial data input function supports memory card playback. x CD-ROM Decoding Functions Supports CD-ROM modes 1 and 2 (forms 1 and 2) Faithfully reproduces data stored on CD-ROM discs using CD-ROM error correction functions. Header and sector management Supports playback speeds up to 4×. In addition to data buffering also supports C2 error flag buffering. Provides external serial output of decoded CD-ROM data. x CD-DA Playback Functions (Shockproof support) Shockproof operation for about 180 seconds (com- pressed mode) when 64M DRAM is used. Shockproof function supports compressed, uncom- pressed, and data through modes. VCEC (variable speed) supports up to 4×-speed play- back. x Audio Signal Processing Serial audio signal output using LRCK, BCK, and DATA signals. (I²S format, either 16-bit or 20-bit precision PCM output, data-slot supports 16-bit, 24-bit, and 32-bit modes) Digital bass boost function (4 modes), attenuator function, and muting (f, 12 dB) Provides a base clock (384 fs) output pin for use with external digital filters and D/A converters. x DRAM Interface Supports the use of from 1M to 64M of external DRAM (EDO, 2CAS, 16-bit data bus memory) Supports allocation of a user area in DRAM during CD-ROM (MP3) playback. Continued on next page. MP3 Decoder for Compact Disc Players LC78684E

No.7350-2/21 Continued from preceding page. x Package and Power Supply Voltage Specifications Supply voltage Internal power supply: 1.8 V (typical) I/O power supply: 3.3 V (typical) Analog system power supply: 3.3 V (typical) MPEG Layer3 audio coding technology licensed from Fraunhofer IIS and THOMSON multimedia Package Dimensions Unit: mm 3255-QFP80 (14 uuuu 14) [LC78684E] 14.0 14.0 17.2 17.2 0.15 0.1 3.0max 0.250.65 (0.83) (2.7) 0.8 1 20 4160 15.6 SANYO: SFP80

No. 7350-3/21 Block Diagram CD-DA shockproof (Compressed or uncompressed) CDROM decoder MP3 decoder M U X Audio I/F CPU-I/F CKIN VPRFR VCOC VPDO CKOUT INTB CMDOUT CMDIN CE CL MDATA[15:0] MADRS[12:0] RASB CASUB CASLB OEB WEB LRSY DATACK DATAIN C2FIN SFSY PW SBSY SBCK RESB ADLRCK ADBCK ADDATA WOK CNTOK OVF Data-I/F FSYNC CRCF STREQ STCK STDAT System clock- generator VCO PLL DRAM-I/F

No.7350-4/21 Pin Assignment LC78684 (Top view) CKOUT VSS PW SFSY SBSY AVDD SBCK ADDATA LRSY TEST2 ADBCK C2FIN ADLRCK CKIN TEST1 VCOC VPRFR DVDD1 VPDO AVSS DATACK DATAIN RESB INTB CE CL CMDIN CMDOUT OVF CNTOK WOK VSS DVDD6 CRCF FSYNC STDAT MADRS0 RASB MADRS2 MADRS1 MADRS4 MADRS3 DVDD4 MADRS5 MADRS9 MADRS8 MADRS12 MADRS10 CASUB OEB WEB CASLB MADRS11 VSS MADRS7 MADRS6 MDATA2 MDATA3 MDATA4 MDATA5 MDATA8 VSS MDATA9 MDATA10 MDATA11 MDATA7 DVDD3 MDATA6 MDATA13 MDATA14 MDATA15 DVDD2 VSS MDATA0 MDATA1 STCK STREQ VSS DVDD5 MDATA12

No.7350-5/21 Pin Functions Absolute Maximum Ratings at VSS 0 V, AVSS 0 V Parameter Symbol Conditions Ratings Unit Maximum supply voltage V DD max 0.3 to VSS 4.0 V Input voltage V IN 0.3 to VDD1 0.3 V Output voltage V OUT 0.3 to VDD1 0.3 V Allowable power dissipation Pdmax 400 mW Operating temperature Topr 30 to 75 qC Storage temperature Tstg 40 to 125 qC Allowable Operating Ranges at Ta 30 to 75qqqqC, VSS 0 V, AVSS 0V RatingsParameter Symbol Pin name Conditions min typ max Unit VDD1 DVDD1, DVDD3, DVDD4, DVDD6, AVDD 3.0 3.3 3.6 VSupply voltage VDD2D V DD2, DVDD5 1.62 1.8 1.98 V High-level input voltage V IH MDATA0 to 15, LRSY, DATAIN, DATACK, C2FIN, PW, SBSY, SFSY, STREQ, STCK, STDAT, WOK, CKIN, CE, CL, CMDIN, RESB 0.8 V DD1V DD1V Low-level input voltage V IL MDATA0 to 15, LRSY, DATAIN, DATACK, C2FIN, PW, SBSY, SFSY, STREQ, STCK, STDAT, WOK, CKIN, CE, CL, CMDIN, RESB, TEST1, TEST2 0 0.2 V DD1V Operating frequency range Fop CKIN 16.9344 MHz

No.7350-6/21 AVSS 0 V RatingsParameter Symbol Pin name Conditions min typ max Unit IDD (1) DVDD1, DVDD3, DVDD4, DVDD6, AVDD VDD1 3.0 to 3.6 V 10.0 20.0 mA Current drain IDD (2) DV DD2, DVDD5 VDD2 1.62 to 1.98 V 4.5 10.0 mA High-level input current I IH MDATA0 to 15, LRSY, DATAIN, DATACK, C2FIN, PW, SBSY, SFSY, STREQ, STCK, STDAT, WOK, CKIN, CE, CL, CMDIN, RESB V IN VDD11 0 PA Low-level input current I IL MDATA0 to 15, LRSY, DATAIN, DATACK, C2FIN, PW, SBSY, SFSY, STREQ, STCK, STDAT, WOK, CKIN, CE, CL, CMDIN, RESB, TEST1, TES2 V IN 0 V 10 PA VOH (1) MDATA0 to 15, STREQ, STCK, STDAT, MADRS0 to 12, RASB, CASUB, CASLB, OEB, WEB SBCK, ADDATA, ADLRCK, ADBCK, INTB, FSYNC, CRCF, CNTOK, OVF I OH 2 mA V DD1 0.6 V VOH (2) CKOUT I OH 4 mA V DD10.6 V High-level output voltage VOH (3) VPDO IOH 0.2 mA VDD10.6  VOL (1) MDATA0 to 15 STREQ, STCK, STDAT, MADRS0 to 12, RASB, CASUB, CASLB, OEB, WEB SBCK, ADDATA, ADLRCK, ADBCK, INTB, FSYNC, CRCF, CNTOK, OVF, CMDOUT I OL 2 mA 0.4 V VOL (2) CKOUT I OL 4 mA 0.4 V Low-level output voltage VOL (3) VPDO IOL 0.2 mA 0.4  IOFF (1) MDATA0 to 15, STREQ, STCK, STDAT, CMDOUT V OUT VDD11 0 PA Output off leakage current IOFF (2) MDATA0 to 15, STREQ, STCK, STDAT, CMDOUT V OUT 0 V 10 PA

No.7350-7/21 Microcontroller Interface Microcontroller Interface Timing Write Cycle T1 T2 T3 T6 T7 CE CL CMDIN Read Cycle T1 T2 T3 CE CL CMDOUT T10 RatingsParameter Symbol min typ max Unit CE/CL setup time T1 500 ns CE/CL hold time T2 250 ns Command wait time T3 1000 ns CL H-level pulse width T4 250 ns CL L-level pulse width T5 250 ns Data/CL setup time T6 150 ns Data/CL hold time T7 150 ns Data-read access time T8 0 240 ns Data-read turn-on time T9 0 150 ns Data-read turn-off time T10 0 240 ns : Pull-up resistor 1 K:, Output load 30 pF

No.7350-8/21 Command Input/Data Output Interface Input commands (i.e. write data to the LC78684E) in the order data first and then address. The data and address are LSB first. Output data is output (i.e. read data from the LC78684E) by first issuing a read mode setup command and then performing read access operations. Data write LSB MSB Data Address High (Held high with an external pull-up resistor) LSB MSB CE CL CMDIN CMDOUT Data read Data is read by first writing the register address to be read to location $61h and then setting up read mode by setting CE low temporarily. When CE is set high again, and the CL signal is issued, the contents of the specified register are output from CMDOUT, LSB first. The microcontroller must perform a read access if it sets up read mode. Read mode setup command Register address Read code (61h) LSB MSB LSB MSB LSB MSB CE CL CMDIN CMDOUT High (Held high with an external pull-up resistor) Read access

No.7350-9/21 Memory Interface Memory Interface Timing Read Cycle RASB CASUB/LB MADRS[12:0] WEB OEB MDATA[15:0] T10 Read data T6 T7 T8 T9 T12 T11 Read data Read data T2 T4 T5 T13 Row Column Column Column Write Cycle T3 T2 T4 T14 Write data T6 T7 T8 T9 T15 T16 T18 T19 T17 Write data Write data RASB CASUB/LB MADRS[12:0] WEB OEB MDATA[15:0] Row Column Column Column

No.7350-10/21 Refresh Cycle (CAS before RAS) RASB CASUB/LB MDATA[15:0] T24 T17 T22 T21 T20 T23 RatingsParameter Symbol min typ max Unit RASB width high T1 100 ns RASB CASB delay T2 80 ns CASB RASB delay T3 40 ns CASB width low T4 40 ns CASB width high T5 40 ns Row address setup time T6 15 ns Row address hold time T7 40 ns Column address setup time T8 15 ns Column address hold time T9 40 ns OEB ready time T10 30 ns OEB hold time T11 10 ns Read data setup time T12 30 ns Read data hold time T13 0 ns WEB ready time T14 30 ns WEB hold time T15 40 ns Write data turn on time T16 60 ns Write data turn off time T17 80 ns Write data setup time T18 15 ns Write data hold time T19 40 ns Refresh cycle T20 300 ns RASB low width (refresh) T21 200 ns RASB CASB delay (refresh) T22 50 ns CASB setup time (refresh) T23 40 ns CASB hold time (refresh) T24 100 ns : These values apply when the frequency of the clock input to the CKIN pin is 16.9344 MHz.

No.7350-11/21 CD DSP Interface CD DSP Interface Timing T1h LRSY DATACK DATAIN C2FIN T1l T2 T3 T4 T5 Fbck RatingsParameter Symbol min typ max Unit DATACK frequency Fbck 14.5 MHz DATACK H-level pulse width T1h 30 ns DATACK L-level pulse width T1l 30 ns LRSY setup time T2 30 ns LRSY hold time T3 30 ns DATA, C2FIN setup time T4 30 ns DATA, C2FIN hold time T5 25 ns : The figure above shows the timings when DATACK rising edge latch is used. If DATACLK falling edge latch is used, the timings are the same as those for the corresponding setup and hold signal.

No.7350-12/21 Subcode Interface Timing SBSY Subcode Frame SF97 SF0 SF1 SF2 SF3 T1l T1h Tssd SFSY PW SBCK SBCK PW Fsbck RatingsParameter Symbol min typ max Unit SFSY SBCK delay time Tssd 235 7150 ns SBCK frequency Fsbck 1.0584 MHz SBCK H-level pulse width T1h 450 ns SBCK L-level pulse width T1l 450 ns PW setup time T2 50 ns PW hold time T3 0 ns : These values apply when the frequency of the clock input to the CKIN pin is 16.9344 MHz.

No.7350-13/21 Audio Output Interface Audio Output Interface Timing T2 T3 ADLRCK ADBCK ADDATA CKOUT Fck The figure above applies when the 48-bit slot is used for the audio data output slot. RatingsParameter Symbol min typ max Unit CKOUT o ADLRCK delay time T1 0 35 ns CKOUT o ADBCK delay time T2 0 35 ns CKOUT o ADDATA delay time T3 0 35 ns CKOUT frequency Fck 16.9344 MHz : These values apply during MPEG1 data playback (fs 44.1 kHz) when the PLL circuit is locked normally. These values depend on the playback sampling frequency (fs). (CKOUT frequency fs u 384) Supplement: Output Timing for Full Through Mode Playback LRSY DATACK DATAIN ADLRCK ADBCK ADDATA CKIN CKOUT : Full through mode is the state where the THROUGH bit (60h: bit 6) is set to 1. RatingsParameter Symbol min typ max Unit INPUT o OUTPUT delay time T5 0 35 ns CKIN o CKOUT delay time T6 0 35 ns : These values apply when the signal input to the CKIN pin is directly output from the CKOUT pin.

No.7350-14/21 Serial Data I/O Interface DRAM Serial Data Output Timing Fsck T1 T2 STCK STDAT STREQ STCK STDAT CRCF : Performing a serial data output operation requires that a command to transfer data from DRAM be issued. If this command has not been issued, the STCK and STDAT pins will not output the clock and data signals, even if the STREQ goes high. Ratings Parameter Symbol min typ max Unit Transfer clock frequency Fsck 4.2336 MHz STDAT/STCK setup time T1 30 ns STDAT/STCK hold time T2 30 ns Data (1byte) transfer time T3 1.89 Ps Data transfer wait time T4 1.89 Ps Data transfer start time T5 1.89 15.2 Ps Data transfer stop time T6 0 15.2 Ps Enable flag turn off time T7 210 236.2 270 ns Notes: The typical values shown apply when the frequency of the clock input to the CKIN pin is 16.9344 MHz. x The fsck clock frequency can also be set to 2.1168 or 1.0584 MHz (typical). The values of T3 to T7 will be, in that case, 2 or 4 times the values shown. x When the STREQ pin is in input mode, the WOK, OVF, and CNTOK pins can be used instead of the STREQ, STCK, and SDAT pins. The timing specifications in this case are the same as those shown above.

No.7350-15/21 MP3 Serial Data Input Timing Fsck T2 T3 STCK STDAT STREQ (*Output from the LC78684E) STCK STDAT T1h T1l Performing a serial data input operation requires that a serial input command be issued. If this command has not been issued, the MP3 decoder will not operate, even if clock and data signals are applied to the STCK and STDAT pins. RatingsParameter Symbol min typ max Unit Transfer clock frequency Fsck 9.216 MHz STCK H-level pulse width T1h 45 ns STCK L-level pulse width T1l 45 ns STDAT/STCK setup time T2 30 ns STDAT/STCK hold time T3 30 ns : The table below lists the maximum frequencies for the transfer clock during serial input operations. MODE Fs (KHz) Maximum serial transfer clock frequency (MHz) MPEG1 48 9.216 44.1 8.4672 32 6.144 MPEG2 24 (12) 4.608 16 (8) 3.072 The transfer clock rate must be set to a speed less than or equal to the speed shown in the table so that the MP3 decoding processing will complete in time. Note that the table above applies when MP3DSET (register 41h, bit 0) is set to 1 (high-speed transfer mode). The timings shown below apply when MP3DSET is set to 0 (low-speed transfer mode). RatingsParameter Symbol min typ max Unit Transfer clock frequency Fsck 3.072 MHz STCK H-level pulse width T1h 150 ns STCK L-level pulse width T1l 150 ns STDAT / STCK setup time T2 125 ns STDAT / STCK hold time T3 125 ns

No.7350-16/21 System Clock Input CKIN pin input signal Fck Twh Twl RatingsParameter Symbol min typ max Unit CKIN Input frequency Fck 16.9344 18.0 MHz CKIN H-Level pulse width Twh 20 ns CKIN L-Level pulse width Twl 20 ns System Reset Input RESB pin input signal Trst RatingsParameter Symbol min typ max Unit System reset pulse width Trst 1 Ps : A system reset must be performed immediately after power is first applied. Design the system so that no noise appears on the reset line.

No.7350-17/21 Pin Functions Pin No. Pin Name I/O Block Function

1 LRSY I CD IF CD left/right clock input

2 ADDATA O Audio data output

3 ADBCK O Audio bit clock output

4 ADLRCK O

Audio left/right clock output

5 C2FIN I CD IF CD C2 error flag input

6 TEST1 I Test Test input 1 (This pin must be connected to ground during normal operation.) 7 CKIN I CLOCK System clock input (16.9344 MHz)

8 VSS Power supply Ground

9 CKOUT O CLOCK External digital filter and D/A converter clock (384 fs) output

10 TEST2 I Test Test input 2 (This pin must be connected to ground during normal operation.)

11 DV DD1 Power supply Digital I/O system power supply

12 PW I CD subcode data serial input

13 SBSY I CD subcode block sync signal input

14 SFSY I CD subcode frame sync signal input

15 SBCK O

CD subcode transfer serial clock output

16 AV DD Power supply Analog system (PLL) power supply

17 VPRFR VCO oscillator range setting

18 VCOC I VCO control voltage input

19 VPDO O

20 AVSS Analog system ground

21 DV DD2 Internal logic system power supply

22 VSS

23 MDATA0 I/O DRAM data bus 0

24 MDATA1 I/O DRAM data bus 1

25 MDATA2 I/O DRAM data bus 2

26 MDATA3 I/O DRAM data bus 3

27 MDATA4 I/O DRAM data bus 4

28 MDATA5 I/O DRAM data bus 5

29 MDATA6 I/O DRAM data bus 6

30 MDATA7 I/O

31 DV DD3 Digital I/O system power supply

32 VSS Power supply GND

33 MDATA8 I/O DRAM data bus 8

34 MDATA9 I/O DRAM data bus 9

35 MDATA10 I/O DRAM data bus 10

36 MDATA11 I/O DRAM data bus 11

37 MDATA12 I/O DRAM data bus 12

38 MDATA13 I/O DRAM data bus 13

39 MDATA14 I/O DRAM data bus 14

40 MDATA15 I/O DRAM data bus 15

41 RASB O RAS output (active low)

42 WEB O WE output (active low)

43 CASLB O CAS output (lower byte, active low)

44 CASUB O CAS output (upper byte, active low)

45 OEB O OE output (active low)

46 MADRS12 O DRAM address output 12

47 MADRS11 O DRAM address output 11

48 MADRS10 O DRAM address output 10

49 MADRS9 O DRAM address output 9

50 MADRS8 O

Continued on next page.

No.7350-18/21 Continued from preceding page. Pin No. Pin Name I/O Block Function

51 DV DD4 Digital I/O system power supply

52 V SS Power supply Ground

53 MADRS7 O DRAM address output 7

54 MADRS6 O DRAM address output 6

55 MADRS5 O DRAM address output 5

56 MADRS4 O DRAM address output 4

57 MADRS3 O DRAM address output 3

58 MADRS2 O DRAM address output 2

59 MADRS1 O DRAM address output 1

60 MADRS0 O

61 DV DD5 Internal logic system power supply

62 V SS Power supply GND

63 STREQ I/O MP3 data request flag output (active high)

/DRAM data request flag input (CD-ROM mode, active high)

64 STCK I/O MP3 data transfer clock input

/DRAM data transfer clock output

65 STDAT I/O

/DRAM serial data output

66 FSYNC O MP3-dec MP3 frame sync signal (active high)

/Data continuity point detection complete flag (CD-DA mode, active high)

67 CRCF O CD monitor CRC check result output (CD-ROM data/CD-DA subcode data)

/DRAM data output enable signal output (active high)

68 DV DD6 Digital I/O system power supply

69 V SS Power supply GND

70 WOK I DRAM write enable input (CD-DA mode, active high)

/DRAM data request flag input

71 CNTOK O Data continuity point detection complete flag (CD-DA mode, active high)

/SYNC error monitor flag (MP3 mode, active high)/DRAM serial data output

72 OVF O

and MP3 I/O DRAM write interrupt flag (CD-DA mode, active high) /Emphasis output flag (CD-DA and MP3 modes, active high) /DRAM data transfer clock output

73 CMDOUT O Serial command data output (n-channel open-drain output)

74 CMDIN I Serial command data input

75 CL I Serial command clock input

76 CE I Command enable input (active high)

77 INTB O Interrupt signal output (active low)

/DRAM write interrupt flag (CD-DA mode, active high)

78 RESB I

System reset (active low)

79 DATAIN I Serial CD data input

80 DATACK I CD IF CD bit clock input

Notes: 1. Notes on unused pins. Unused input pins must be connected to the ground level (0 V). Unused output pins must be left open. Do not connect anything to these pins. Unused I/O pins may either be connected to the ground level (0 V) or set to output mode and left open. 2. The corresponding power supply levels must be provided to all of the DV DD1, DVDD3, DVDD4, DVDD6, and AVDD pins. The corresponding power supply level must also be provided to DVDD2 and DVDD5. (See the Allowable Operating Ranges specifications for the supply levels.) 3. The TEST1 and TEST2 input pins must be connected to ground (0 V). 4. The I/O pins (MDAT0:15, STREQ, STCK, and STDAT) go to input mode after a reset. 5. After first applying the power supply levels, the RESB pin must be held low for at least 1 µs. 6. A 16.9344 MHz clock signal must be supplied to the CKIN pin by the CD DSP. The LC78684E does not support the implementation of an oscillator circuit using an oscillator element.

No.7350-19/21 Sample Application Circuit 3.3 V GND LRSY ADDATA ADBCK ADLRCK C2FIN VSS CKIN VSS CKOUT VSS DVDD1 PW SBSY SFSY SBCK AVDD VPRFR VCOC VPDO AVSS LC78684E MDATA15 MDATA14 MDATA13 MDATA12 MDATA11 MDATA10 MDATA9 MDATA8 VSS DVDD3 MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1 MDATA0 VSS DVDD2 MADRS0 MADRS1 MADRS2 MADRS3 MADRS4 MADRS5 MADRS6 MADRS7 VSS DVDD4 MADRS8 MADRS9 MADRS10 MADRS11 MADRS12 OEB CASUB CASLB WEB RASB DVDD5 VSS STREQ STDAT STDAT FSYNC CRCF DVDD6 VSS WOK CNTOK OVF CMDOUT CMDIN CL CE INTB RESB DATAIN DATACK To DRAM To Micro- controller 1.8 V To CD-DSP : The CKOUT, ADLRCK, ADBCK, and ADDATA pins must be connected to a CD DSP that supports external D/A converter input. An external D/A converter is required if the CD DSP does not provide that functionality.

No.7350-20/21 Application Design Notes While it goes without saying that strictly observing the absolute maximum ratings and allowable operating ranges (recommended operation conditions) stipulated for this IC is necessary to achieve reliability of the overall system, it is also necessary to take adequate care with respect to the mounting conditions and the operating environment, including the ambient temperature and the possibility of electrostatic discharges (ESD). This section presents notes on aspects of design and mounting that require special attention. Handling Unused Pins If this IC is operated with unused input pins left open, certain internal circuit operations may become unstable. Unused pins that are mentioned in the IC documentation must be handled as specified. Also, do not allow output pins to come in contact with any circuit lines, including power supply lines, ground lines, or other outputs. Latchup Prevention x The voltages stipulated in the IC specifications must be provided to the corresponding power supply pins. When the same voltage is stipulated for multiple pins, those pins all must be connected to the same potential. x Do not set I/O voltage levels to be either higher than the peripheral 3 V system block voltage, or lower than the ground level. This relationship must also be maintained during the power-on sequence. x Do not apply overvoltages or abnormal noise to this IC. x While in general, latchup is prevented by holding unused input pins at either the VDD or VSS potential, input pins to this IC must be handled as described in the pin descriptions. x Do not short the outputs. Interface Incorrect operation may result when different devices are connected if the input VIL/VIH and the output VOH and VOH levels do not match. Level shifters must be inserted between devices with differing supply voltages, such as those often used in dual power supply systems, to prevent destruction of the devices. Load Capacitance and Output Current x If a large load capacitance is connected, the resulting effective short of the outputs may continue for an extended period and lead to fusing of lines. Also, larger charge and discharge currents can cause noise, degrade device performance, and cause incorrect operation. The recommended load capacitance ratings must be observed. x Excessive output sink or source currents can lead to the same problems described in the preceding item. Once the allowable power dissipation rating has been met, the recommended current values must be observed as well. Notes on Power Application and Reset x There are several aspects that require care when power is first applied, during a reset, and when the reset state is cleared. Refer to the device specifications and design applications to match the product specifications. x In this IC, the register contents, pin output states, and pin I/O settings are not guaranteed after power is first applied. Ite ms that are defined by the reset operation or mode setting operations are guaranteed after these operations are performed. After power is first applied to this IC, the application must first perform a reset operation. Pin states and register values that ar e not defined are subject to change, both due to sample-to-sample variations in the product over the long term, and due to changes in device design from the initial design states. Thermal Design x Semiconductor device failure rates are greatly accelerated by inappropriate ambient temperature and power consumption conditions. To assure the highest possible reliability, the thermal design should provide ample margins considering all possible changes in the ambient conditions.

No.7350-21/21 Notes on PWB Pattern Design x In an ideal design, power supply and ground lines will be provided separately for each system to minimize the influence of shared impedances. x Power supply and ground lines must be made as wide and as short as possible, and the impedance to high frequencies must be made as low as possible. Decoupling capacitors (consisting of two capacitors: one about 0.01 to 1.0 µF and another about 100 to 220 µF) should be inserted between each power supply pin and ground. Note, however, that if this capacitance is too large, it may result in latchup problems. Other Notes If you have any questions or if anything is even slightly unclear, please contact your SANYO sales or technical representative during the design phase. This IC is a special-purpose device for use in CD players, and its specifications differ from those of standard logic ICs and other general-purpose products. Also note that, depending on the application, failsafe measures and/or system level debugging of the total system may be required as well. Q Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. Q SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. Q In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. Q No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Q Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Q Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 2003. Specifications and information herein are subject to change without notice.