LC78681E

LC78681E SANYO | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 23

Technical content

Features

• Compact and space-saving 64-pin QFP package
• Silicon-gate CMOS design (low power dissipation)
• Single 5 V power supply (suitable for portable sets)
• DEMO pin for improved operability in adjustment

unit: mm 3159-QFP64E No. 4521-2/23 LC78681E SANYO: QFP64E [LC78681E] Equivalent Circuit

No. 4521-3/23 LC78681E Top view Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Ratings Unit Maximum supply voltage V DD max V SS – 0.3 to 7 V Maximum input voltage V IN max V SS – 0.3 to VDD + 0.3 V Maximum output voltage V OUT max V SS – 0.3 to VDD + 0.3 V Allowable power dissipation Pd max 300 mW Operating temperature Topr –30 to +75 °C Storage temperature Tstg –40 to +125 °C

Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Electrical Characteristics at Ta = 25°C, VSS = 0 V , VDD = 5 V No. 4521-4/23 LC78681E Parameter Symbol Conditions Ratings Unitmin typ max Supply voltage V DD VDD 4.5 5.5 V VIH (1) TEST1 to 5, AI, FZD, HFL, DEMO, M/L, 0.7 VDD VDD VRES Input high level voltage VIH (2) SBCK, RWC, COIN, CQCK, CS 2.2 V DD V VIH (3) EFMIN 0.6 V DD VDD V VIH (4) TES 0.8 V DD VDD V VIL(1) TEST1 to 5, AI, FZD, HFL, DEMO, M/L, VSS 0.3 VDD VRES Input low level voltage VIL(2) SBCK, RWC, COIN, CQCK, CS V SS 0.8 V VIL(3) EFMIN V SS 0.4 VDD V VIL(4) TES V SS 0.2 VDD V Data setup time t set up COIN, RWC: Figure 1 400 ns Data hold time t hold RWC: Figure 1 400 ns High level clock pulse width t W øH SBCK, CQCK: Figures 1, 2 and 3 400 ns Low level clock pulse width t W øL CQCK, SBCK: Figures 1, 2 and 3 400 ns Data read access time t RAC Figures 2 and 3 0 400 ns Command output time t RWC RWC: Figure 1 1000 ns Sub-Q read enable time t SQE Figure 2, no RWC signal 11.2 ms Subcode read cycle t sc Figure 3 136 µs Subcode read enable t se Figure 3 400 ns Crystal oscillator frequency fX ’tal X IN, XOUT 16.9344 MHz Operating frequency range f op (1) AI 2.0 20 MHz f op (2) EFMIN: V IN ≥ 1 Vpp 10 MHz Parameter Symbol Conditions Ratings Unitmin typ max Current drain I DD 17 30 mA IIH (1) AI, EFMIN, FZD, TES, SBCK, COIN, 5µ A Input high level current CQCK, RES, HFL, RWC, M/L: VIN = VDD IIH (2) TEST1 to 5, DEMO, CS: 25 75 µAVIN = VDD = 5.5 V Input low level current I IL(1) AI, EFMIN, FZD, TES, SBCK, COIN, –5µ ACQCK, RES, HFL, RWC, M/L: VIN = VSS AO, PDO, EFMO, EFMO, CLV +, CLV–, VOH (1) FOCS, FSEQ, PCK, TOFF, TGL, THLD, VDD – 1VJP+, JP–, EMPH, EFLG, FSX, V/P: IOH = –1 mA Output high level voltage VOH (2) DOUT: I OH = –12 mA V DD – 0.5 V LASER, SQOUT, 16M, 4.2M, CONT, WCLK, TEST7, LRCLK, WRQ, C2F, VOH (3) DFOUT, DACLK, SFSY, LRSY, SBSY, V DD – 1V CK2, PW, ROMOUT, C2FCLK: I OH = –0.5 mA Continued on next page.

No. 4521-6/23 LC78681E No. Name I/O Description 1 TEST1 I LSI test input. Normally unconnected. 2A O O 3A I I

4 PDO O

SS — GND

6 EFMO O

7 EFMO O

8 EFMIN I

9 TEST2 I LSI test input. Normally unconnected.

10 CLV

+ O Disc motor control outputs.

11 CLV – O

12 V/P O Output is high with constant linear velocity rough servo, and low during phase control

13 FOCS O

14 FST O

15 FZD I

16 HFL I

17 TES I

18 PCK O 4.3218 MHz PCK monitor output. 19 FSEQ O High when SYNC (true frame sync) detected from the EFM signal matches SYNC from counter (interleaving frame sync). (Single-frame latch output.)

20 TOFF O

21 TGL O

22 THLD O

23 TEST3 I LSI test input. Normally unconnected. 24 V DD — +5 V

25 JP + O

26 JP – O

27 DEMO I Sound generation function for set adjustment. 28 TEST4 I LSI test input. Normally unconnected. 29 EMPH O Deemphasis required when high. 30 NC Not connected. 31 WCLK O Signal output to D/A converter. Outputs latch signal and signals for left-right switching and sample holding. 32 TEST7 O LSI test input. Normally unconnected. 33 LRCLK O Signal output to D/A converter. Outputs latch signal and signals for left-right switching and sample holding. 34 NC Not connected.

35 DFOUT O

Signal output to D/A converter. Outputs latch signal and signals for left-right switching and sample holding.

36 DACLK O

37 TEST6 O LSI test input. Normally unconnected. Continued on next page. LPin for input of the on-chip VCO output from the LA9210 (8.6436 MHz). Phase detector output (PDO) is phased output with the EFM signal, set so that frequency is raised by positive voltage. Inputs 1 to 2 VPP HF signal to EFMIN. Complementary EFM signal output is made from EFMO and EFMO via the amplitude limiter. These are used for slice level control. Focus servo is switched off when FOCS is high. Lens is lowered by FST and raised gradually when FOCS is high. Generation of FZD resets FOCS. Used for focus servo control. Generates kick pulse, JP+, or JP– according to track jump command. Jumps the specified number of tracks (1, 2, 4, 16, 32, 64, or 128). Generates kick pulse, JP+, or JP– according to track jump command. Jumps the specified number of tracks (1, 2, 4, 16, 32, 64, or 128). Generates kick pulse, JP+, or JP– according to track jump command. Jumps the specified number of tracks (1, 2, 4, 16, 32, 64, or 128).

Continued from preceding page. Functional Description HF Signal Input Circuit (pin 8: EFMIN, pin 7: EFMO and pin 6: EFMO) An EFM signal (NRZ) sliced at the optimum level is obtained when the HF signal is input on EFMIN. No. 4521-7/23 LC78681E No. Name I/O Description

38 LRSY O

39 CK2 O

40 ROMOUT O For output of CD-ROM interface signals.

41 C2FCLK O

42 C2F O

43 DOUT O Digital OUT output

44 SBSY O Subcode block synchronization output

45 EFLG O C1 and C2 single and double error correction flag.

46 PW O

47 SFSY O

48 SBCK I

49 FSX O 7.35 kHz synchronization signal output

50 WRQ O

51 RWC I

52 SQOUT O

53 COIN I

54 CQCK I

55 RES I Set to low at powerup. 56 M/L I Same as for pins 50 to 54. 57 LASER O Permits control via serial control from the microprocessor. 58 16 M O 16.9344 MHz output pin 59 4.2 M O 4.2336 MHz output pin. 60 CONT O Permits control via serial control from the microprocessor. 61 TEST5 I LSI test input. Normally unconnected. 62 CS I Chip select pin. The LC78681 is active when this pin is low (on-chip pull-down resistor). 63 X IN I 16.9344 MHz crystal oscillator connection pins.

64 X OUT O

SFSY is subcode frame synchronization signal. P, Q, R, S, T, U, V, and W subcodes are read out by sending clock eight times to SBCK. WRQ goes high when Q subcode data passes the CRC check. Through external connection and sending of CQCK, data is read from SQOUT. Set MSB-first/LSB-first to low when data in LSB-first format is desired. Command is generated by sending output synchronized with CQCK command data after setting microprocessor RWC to high.

PLL Clock Regeneration Circuit (pin 4: PDO, pin 3: AI, and pin 2: AO) A PLL comprising a VCO can be made with an LA9210. Output from the PDO pin goes positive when the VCO phase is lagging. VCO Half-Frequency Clock (pin 18: PCK) This pin monitors a signal generated by dividing the VCO frequency by two. This signal has an average frequency of 4.3218 MHz. Frame Synchronization Detector Monitor (pin 19: FSEQ) FSEQ is latched high for one frame when the frame sync (true synchronization signal) recovered from the EFM signal matches the sync timing generated by an internal counter. Servo Command Function (pin 51: RWC, pin 53: COIN, pin 54: CQCK and pin 62: CS) Commands can be input by setting RWC high and issuing the command synchronized to the CQCK clock from COIN. Focus start Track jump Mute control 1-byte commands Disc motor control Other control commands Track count 2-byte command 1. 1-byte Commands No. 4521-8/23 LC78681E

1. 2-byte Commands The commands are executed on the falling edge of RWC. Focus Servocontroller (pin 13: FOCS, pin 14: FST, pin 15: FZD and pin 57: LASER) 1. Laser Control 2. Focus Start When a Focus Start command (either 1 or 2) is issued, the pickup lens is first lowered as C1 discharges through FST and then raised gradually as C1 is recharged by FOCS. FZD goes low when the focal point is reached, and FOCS is reset and the focus servocontroller turned on when this signal is received. After issuing this command, the microprocessor checks the DRF signal from the LA9210 to verify that focus has been reached, and advances to the next step. If C1 recharges fully before focus has been reached, the Focus Start command should be reissued to repeat operation of the focus servocontroller. No. 4521-9/23 LC78681E MSB LSB Command RES = low

00001000 FOCUS START #1

10100010 F OCUS START #2

00001010 LASER ON

10001010 L ASER OFF /hwycircle

00000000 N O T H I N G

Note: If for Focus Start 2, the value in parentheses is in effect only when FST is low (unlike Focus Start 1). Notes: 1. The falling edge of FZD is not accepted when FST is low. 2. After a Focus Start command has been issued, the focus servocontroller is reinitialized when RWC goes high. For this reason, a new command should not be issued until the S-curve for the focus coil drive has been completed. 3. If focus cannot be reached (i.e., the FZD signal does not go low), the FOCS signal remains high and the lens remains raised. In this case, the Nothing command should be issued to reinitialize the servocontroller. 4. When the RES pin is set low, LASER is directly set high. 5. Focus start using the DEMO pin is in mode 1. Constant Linear Velocity Servocontroller (pin 10: CLV +, pin 11: CLV– and pin 12: V/P) The disc motor accelerates when CLV+ is high and decelerates when CLV– is high. These outputs are selected by the motor mode commands issued by the microprocessor (accelerate, decelerate, CLV, or stop). The CLV+ and CLV – outputs for each mode are shown in the following table. No. 4521-10/23 LC78681E MSB LSB Command RES = low

00000100 D I S C MOTOR START (accelerate)

00000101 D I S C MOTOR CLV (CLV)

00000110 D I S C MOTOR BRAKE (decelerate)

00000111 D I S C MOTOR STOP (stop) /hwycircle

Mode CLV + CLV – Accelerate High Low Decelerate Low High CLV ** Stop Low Low

Note: * For constant linear velocity servo control commands, the TOFF pin is low only in the CLV mode; otherwise it is high. Control of the TOFF pin by command is effective only in the CLV mode. 1. CLV Mode

• In the CLV (constant linear velocity) mode, the LC78681E detects disc speed from the HF signal and switches the internal DSP mode to perform various types of control for maintaining the correct linear velocity. The pulse-width modulation cycle is 7.35 kHz, and the 1/64 duty cycle is 1.114 s. V/P outputs high during rough servo and low during phase control. 2. CLV Control Gain Switching CLV control gain during rough switching for 8-cm discs can be set at 8.5 dB lower than for 12-cm discs. 3. Internal Brake Mode
• The internal brake mode is enabled when an Internal Brake On command (C5H) is input. Executing a Brake command (06H) in this mode allows the deceleration of the disk to be monitored at the WRQ pin.
• In this mode, the EFM signal density per frame can be counted to determine the status of disc deceleration. When there are fewer than four EFM signals, CLV – falls to low, and the WRQ pin simultaneously goes high to indicate that brakes is completed. The microprocessor issues a Stop command when it senses that the WRQ pin is high, thereby completing the stopping of the disc. No. 4521-11/23 LC78681E Internal mode CLV + CLV – V/P Rough servo (velocity too low) High Low High Rough servo (velocity too high) Low High High Phase control (PLCK locked) PWM PWM Low MSB LSB Command RES = low

10101000 D I S C 8 s e t

10101001 D I S C 1 2 s e t /hwycircle

MSB LSB Command RES = low

11000101 Internal brake on

11000100 Internal brake off /hwycircle

10100011 Internal brake control

Notes: 1. When EFM signal noise results in errors in deceleration state determination, it may be advantageous to use the internal brake control command (A3H) to change the EFM signal count from four to eight. 2. If focus is lost during execution of an internal brake command, it is necessary to first refocus and then input the internal brake command again. 3. Due to the possibility of state determination errors due to the EFM signal playback state (e.g., damaged disk or access in progress) we recommend that this product be used in conjunction with a microprocessor. Track Jump Circuit (pin 16: HFL, pin 17: TES, pin 20: TOFF, pin 21: TGL, pin 22: THLD, pin 25: JP+ and pin 26: JP–) 1. Internal Track Count The following two modes are available. The standard track count uses the TES signal without modification as the internal track count clock. In order to reduce counting errors due to noise on the rising and falling edges of the TES signal, the new track counter suppresses this noise through combination with the HFL signal, enabling an accurate track count. However, if the HFL signal is lost because of foreign matter or scratching on the disk, no track count pulse may be generated. For this reason, caution is required when using this mode. No. 4521-12/23 LC78681E MSB LSB Command RES = low

00100010 New track count (combination of TES and HFL) /hwycircle

00100011 S t andard track count (direct count of the TES signal)

1. Track Jump Commands When a track jump command is issued to the servocontroller, an acceleration pulse is generated (a period), followed by a deceleration pulse (b period) and braking (c period), completing the specified jump. TES and HFL input during braking detects the direction of beam slippage, and the portion of the TE signal that compensates for slippage is cut off by TOFF, which, together with boosting of the servo gain by TGL, supplements the destination track for the jump. Note: Of the disc motor control outputs, the TOFF pin is low in the CLV mode, and high in the Start Stop, and Brake modes. TOFF can also be independently switched on or off by the microprocessor. However, disc motor control is enabled only in the CLV mode. No. 4521-13/23 LC78681E MSB LSB Command RES = low

10100000 S tandard track jump /hwycircle

10100001 N e w track jump

00010001 1 TRACK JUMP IN #1 00010010 1 TRACK JUMP IN #2 00110001 1 T RACK JUMP IN #3 00010000 2 TRACK JUMP IN 00010011 4 T RACK JUMP IN 00010100 1 6 TRACK JUMP IN 00110000 3 2 TRACK JUMP IN 00010101 6 4 TRACK JUMP IN 00010111 128 TRACK JUMP IN 00011001 1 T RACK JUMP OUT #1 00011010 1 TRACK JUMP OUT #2 00111001 1 T RACK JUMP OUT #3 00011000 2 TRACK JUMP OUT 00011011 4 T RACK JUMP OUT 00011100 1 6 T RACK JUMP OUT 00111000 3 2 T RACK JUMP OUT 00011101 6 4 TRACK JUMP OUT 00011111 128 TRACK JUMP OUT 00010110 256 TRACK CHECK

00001111 T O F F

10001111 T O N /hwycircle

10001100 T RACK JUMP BRAKE

1. Track Jump Modes The relationship between acceleration pulses, deceleration pulses, and brake periods is shown in the following table. Notes: 1. The actuator drive signals are not generated for the 256-track Check. Instead issuance of a feed motor signal is required because the TES signal is in the track-count mode and the tracking servocontroller is off. 2. The servocontroller register is automatically reset after one a, b, and c track jump sequence. 3. When a new track jump command is issued while a previous command is still being processed, the new command is executed immediately. 4. Track Check Mode A Track Count In or Track Count Out command followed by a binary number between 16 and 256 can be used to start track counting for the specified number of tracks. No. 4521-14/23 LC78681E Standard track jump mode New track jump mode Command abcabc

1 TRACK JUMP IN (OUT) #1 233 µs 233 µs 24 ms 233 µs 233 µs 24 ms

1 TRACK JUMP IN (OUT) #2 0.5-track jump 233 µs 24 ms 0.5-track jump a period 24 ms 1 TRACK JUMP IN (OUT) #3 0.5-track jump 233 µs Does not occur 0.5-track jump a period Does not occur 2 TRACK JUMP IN (OUT) There are no a, b, or c periods. 1-track jump a period Does not occur

4 TRACK JUMP IN (OUT) 2-track jump 466 µs 24 ms 2-track jump a period 24 ms

16 TRACK JUMP IN (OUT) 9-track jump 7-track jump 24 ms 9-track jump a period 24 ms

32 TRACK JUMP IN (OUT) 18-track jump 14-track jump 24 ms 18-track jump 14-track jump 24 ms

64 TRACK JUMP IN (OUT) 36-track jump 28-track jump 24 ms 36-track jump 28-track jump 24 ms

128 TRACK JUMP IN (OUT) 72-track jump 56-track jump 24 ms 72-track jump 56-track jump 24 ms

TOFF goes high after 256 tracks are TOFF goes high after 256 tracks are 256 TRACK CHECK jumped. The a and b pulses are not 24 ms jumped. The a and b pulses are not 24 ms output. output. TRACK JUMP BRAKE There are no a or b periods. 24 ms There are no a or b periods. 24 ms MSB LSB Command RES = low

11110000 Track Count In

11111000 T rack Count Out

11111111 2-byte COMMAND RESET /hwycircle

Notes: 1. The fall of RWC when the desired number of tracks is input in binary format starts the track count. 2. During track counting, TOFF is high and the tracking servocontroller is turned off. For this reason, issuance of a feed motor signal is required. 3. The Track Count In and Track Count Out commands cause the WRQ signal to change from the Q subcode standby monitor when normal to the track count monitor. WRQ goes high at half the track count and low again at the end of the count. The microprocessor monitors WRQ to detect track count completion. 4. When a 2-byte Command Reset command is not issued, the track count starts again. For example, to advance 20,000 tracks, the microprocessor can set the track count number to 200 and wait 100 WRQ pulses. 5. The Brake command is used to bring the pickup to the track when counting is finished. Error Flag Output (pin 45: EFLG and pin 49: FSX) The 7.35 kHz FSX frame synchronization signal is divided down from the reference clock. The status of error correction in each frame is output on EFLG, as shown in the figure, where the number of high pulses in each FSX period indicates the quality of the replay signal. P, Q, and R through W Subcode Output Circuit (pin 46: PW, pin 44: SBSY, pin 47: SFSY and pin 48: SBCK) PW is the subcode signal output pin. The falling edge of SFSY starts the 136 µs period during which SBCK is clocked eight times, allowing all codes — P, Q, and R through W — to be read. The signals appearing at the PW pin change with the rising edge of SBCK. When SBCK is static, the P code is input to PW. SFSY is the signal output for each subcode frame, and the rising edge of this signal indicates standby status for output of the subcode symbols (P through W). Subcode data P if output simultaneously with the falling edge of this signal. SBSY is output for each subcode block. It is high during the S0 and S1 synchronization cycles. Its falling edge indicates the end of synchronization and the start of EIAJ-format data within the subcode block. No. 4521-15/23 LC78681E

(pin 50: WRQ, pin 51: RWC, pin 52: SQOUT, pin 54: CQCK, pin 56: M/L and pin 62: CS) Q subcode data can be read from the SQOUT pin by clocking the CQCK pin. Of the 8-bit subcode data, the Q signal is effective for operations such as song access and display. WRQ is high only when the block CRC is correct and the address in the Q subcode format is 1*.When the microprocessor senses that WRQ is high and issues CQCK, data can be read from SQOUT in the sequence indicated below. When CQCK is activated, the DSP disables internal register updating. When the microprocessor finishes reading data, it briefly sets RWC high to reenable data updating and resets WRC low. CQCK should start to oscillate in the 11.2 ms period during which WRQ is high. Data can be read in LSB-first format when M/L is low and in MSB-first format when it is high. Note: * This condition is ignored when the Address Free command is issued. (The Address Free command is used in CD-V applications.) No. 4521-16/23 LC78681E MSB LSB Command RES = low

00001001 ADDRESS FREE

10001001 ADDRESS 1 /hwycircle

INDEX (POINT)* MIN SEC FLAME ZERO AMIN (PMIN)*/PKMIN ASEC (PSEC) */PKSEC AFLAME (PFLAME) */PKFLAME LVM data/PKM data LVM data/PKM data The order of data output remains unchanged whether M/L is high or low. LVM/PKM 16-bit data Note: * Items in parentheses are for the disc lead-in area.

Notes: 1. The WRQ pin normally indicates Q subcode standby status, but provides different information during the Track Count mode or internal braking. (See the sections on track counting and internal braking.) 2. The LC78681E is active when CS is low, with output from SQOUT. SQOUT is in the high-impedance state when the CS pin is high. Reading Level Meter (LVM) and Peak Meter (PKM) Data 1. Level Meter (LVM)

• The Level Meter mode is enabled by inputting the Level Meter Set command (2CH).
• Level meter data is 16 bits, and is composed of 15 bits of absolute-value data and an MSB indicating left-right polarity. Data is for the left channel when the MSB is high and for the right channel when low.
• Level meter data is appended at the end of 80 bits of Q subcode data, and can be read from the SQOUT pin by clocking the CQCK pin 96 times. The left and right channels are swapped each time that level meter data is read. The left and right channels are independent, and the highest value read for each of the channels is held. 2. Peak Meter (PKM)
• The Peak Meter mode is enabled by inputting the Peak Meter Set command (2BH).
• Peak meter data is 16 bits, and is composed of 15 bits of absolute-value data and an MSB fixed at 0. The maximum value is detected with no regard for right or left channel.
• Peak meter data is read in a manner similar to that for level meter data. However, data is not updated by further reading.
• The absolute time for Q subcode data when in the Peak Meter mode is issued while holding the absolute time (ATIME) that is detected after generation of the maximum value. (Relative time is normal operation.)
• Issuing a Peak Meter Mask Set command causes values larger than the maximum value already in memory to be ignored, even when this command is issued in the Peak Meter mode. This is canceled by the Peak Meter Mask Reset command (used in peak searches for songs in memory). No. 4521-17/23 LC78681E MSB LSB Command RES = low

00101011 PKM set (LVM reset)

00101100 L V M set (PKM reset) /hwycircle

00101101 PKM mask set

00101110 PKM mask reset /hwycircle

Volume can be reduced by 12 dB (MUTE –12 dB) or muted fully (MUTE ∞ dB) by issuing the commands shown above. Muting switches at zero crossings to prevent switching noise on the audio output. A zero crossing is judged to be any data where the upper seven bits are all 1 or all 0. Bilingual Function

• The left and right channels are output to the left and right channels when reset or when the Stereo command (28H) is issued.
• Left channel data is output to both the left and right channels when the Left Channel Set command (29H) is issued.
• Right channel data is output to both the left and right channels when the Right Channel Set command (2AH) is issued. Deemphasis Control (pin 29: EMPH) The preemphasis on/off bit in the Q subcode data is output on EMPH. Deemphasis is required when EMPH is high. D/A Converter Interface (pin 31: WCLK, pin 33: LRCLK, pin 35: DFOUT and pin 36: DACLK) D/A converter data is output in MSB-first format from DFOUT, in synchronization with the falling edge of DACLK. Issuing the CD-ROM XA command causes data which does not undergo interpolation or muting control to be output on DFOUT (when CD-ROM XA is supported). Because the Reset command for CD-ROM XA is common with the CONT reset on pin 60, caution is required.
• LC78681 D/A Converter Interface No. 4521-18/23 LC78681E MSB LSB Command RES = low

00000001 M u t e 0 d B

00000010 M u t e –12 dB

00000011 M u t e ∞ dB /hwycircle

MSB LSB Command RES = low

00101000 STO CONT /hwycircle

00101001 Lch CONT

00101010 Rch CONT

MSB LSB Command RES = low

10001000 C D - ROM XA

10001011 CONT and CD-ROM XA Reset /hwycircle

Output for CD-ROM (pin 39: CK2, pin 37: LRSY, pin 40: ROMOUT: pin 42: C2F and pin 41: C2FCLK) Data from the ROMOUT pin which is synchronized with the LRSY signal is output in MSB-first format. Because this data has not been processed by either the interpolation, previous-value hold, or digital filtering circuits, it is suitable for CD-ROM IC input. CK2 is a 2.1168 MHz clock, and data is output on its rising edge. C2F flags 8-bit units of data, and is synchronized to C2FCLK. LC8951 and LC78681 Interface Digital Audio Out Circuit (pin 43: DOUT) This is the output pin for the digital audio interface, with output in EIAJ format. The signal is output after interpolation and muting. This output pin has a built-in driver, and can drive a transistor directly.

• The digital out pin can be fixed low by issuing the DOUT OFF command.
• The UBIT data in the DOUT data can be fixed at 0 by issuing the UBIT OFF command. Control Pin (pin 60: CONT) The CONT pin can be set high by issuing the CONT Set command. Crystal Oscillator (pin 63: X IN and pin 64: XOUT ) No. 4521-19/23 LC78681E MSB LSB Command RES = low

01000010 DOUT ON /hwycircle

01000011 DOUT OFF

01000000 U B I T O N /hwycircle

01000001 U B I T O F F

MSB LSB Command RES = low

10001110 OSC ON /hwycircle

10001101 OSC OFF

11000001 D ouble-speed mode

11000010 N o r m a l m o d e /hwycircle

01100000 VCO 8 M /hwycircle

01100001 VCO 16 M

MSB LSB Command RES = low

00001110 CONT set Low

A clock to serve as a time base can be obtained by connecting a 16.9344 MHz crystal to XIN and XOUT . The OSC OFF command stops oscillation of the crystal and the VCO. The double-speed mode can also be enabled through the use of commands. The relationship between the crystal and VCO is shown below. Recommended crystal oscillator constants 4.2M and 16M Pins (pin 59: 4.2M and pin 58: 16M) Buffered 16.9344 MHz output from an externally connected 16.9344 MHz crystal is output from 16 M. It is also divided by four to generate a 4.2336 MHz clock that is output on 4.2 M. When the OSC OFF command has been issued, these outputs are held either high or low. The same frequency is generated in both normal and double-speed modes. Reset Circuit (pin 55: RES) This pin should momentarily be held low after power-on. This is set to –∞ dB for muting or to STOP for the disc motor. No. 4521-20/23 LC78681E VCO playback speed Mode 8M Mode 16M Normal speed mode Double speed mode Normal speed mode Double speed mode After reset /hwycircle —— — AI pin external input (8M VCO) 8.6436 MHz AI pin external input (17M VCO) 17.2872 MHz 17.2872 MHz AI pin external input (LA9210) 8.6436 MHz 17.2872 MHz PCK monitor output 4.3218 MHz 8.6436 MHz 4.3218 MHz 8.6436 MHz Manufacturer Oscillator Cin/Cout CITIZEN WATCH CO., LTD. CSA-309 (16.9344 MHz) 6 pF to 10 pF (Cin = Cout) Constant linear velocity servo START BRAKE CLV Muting control 0 dB –12 db Q subcode address conditions Address free Laser control ON (low) (high) CONT High OSC OFF Track jump mode New Track count mode Standard New Standard ON Low OFF Address 1 STOP

The states shown above in boxes are set directly when RES is low. Audio Output for Calibration (pin 27: DEMO) Setting this pin high sets muting to 0 dB and the disc motor to constant linear velocity, even when the microprocessor issues no command, and activates focusing. Because this also makes the LASER pin active, EFM signals and audio output can be obtained without the microprocessor as long as the mechanism and servo are hooked up correctly. Other Pins (pin 1: TEST1, pin 9: TEST2, pin 23: TEST4, pin 61: TEST5, pin 37: TEST6 and pin 32: TEST7) These are test pins for the internal circuitry of the LC78681E. TEST1 through TEST5 have internal pull-down resistors. The test inputs can be left open during normal operation. No. 4521-21/23 LC78681E

No. 4521-22/23 LC78681E Description of Block Operation 1. RAM Address Control The LC78681E incorporates an 8-bit × 2-kbyte RAM buffer, allowing address control to be used to remove from the EFM demodulation data such timing variations, or jitter, that are caused by variations in disc motor speed. The buffer can absorb up to ±4 frames of jitter. The buffer controller constantly monitors buffer free space and adjusts the CLV servocontroller divider ratio to keep the data write address in the middle of the buffer (i.e., at zero). If the ±4-frame limit is exceeded, the write address is forced to ±0, and the output is muted for 128 frames because the resulting error cannot be handled by normal error processing algorithms. C1 and C2 Error Correction After EFM demodulation, data is written to the internal RAM, jitter is absorbed, and the processing described below is carried out under uniform timing according to the crystal clock. First, the C1 stage involves error detection and correction, determination of the C1 flags, and writing to the C1 flag register. Next, the C2 stage involves error detection and correction, determination of the C2 flags, and writing to the internal RAM. Notes: 1. If the error positions determined in the C2 stage match the C1 flags, correction is carried out and the flags are reset. However, if there are seven or more C1 flags, no correction is made (because of the danger of erroneous correction), and the C1 flags are taken as the C2 flags without change. If one error position matches but another does not, correction cannot be performed. Moreover, if there are five or fewer C1 flags, the results of the C1 stage may be incorrect, and the flag is set. If there are six or more, the situation is handled as uncorrectable, and the C1 flags are taken as the C2 flags without change. Correction is not possible if even only one error position is different, and the flags are set even if there are two or fewer C1 flags, because such data may be erroneous even if it passes the C1 stage. 2. If there are three or more errors and correction is determined to be impossible, no correction is made; if there are two or fewer C1 flags, data which passes the C1 stage may still be corrupt, and so the flags are set. Otherwise the C1 flags are taken as the C2 flags without change. C1 flag Error correction and flag processing No errors No correction required Flag reset 1 error Correction Flag reset 2 errors Correction Flag set 3 errors or more Correction not possible Flag set C2 flag Error correction and flag processing No errors No correction required Flag reset 1 error Correction Flag reset 2 errors Depends on C1 flags 3 errors or more Depends on C1 flags *2 Position Division ratio or processing –4 or less Force to ±0 –3 589 –2 589 Increase ratio –1 589 ±0 588 Standard ratio +1 587 +2 587 Decrease ratio +3 587 +4 or more Force to ±0

PS No. 4521-23/23 LC78681E This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.