LC7861KE SANYO | Alldatasheet
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CMOS LS} LC7861KE SANYO Digital Signal Processor for Compact Disc Players Preliminary vervi * The LC786IKE sets the C2 flags based on the C1 flag jew x 7 i The LC7861KE is a CMOS LSI that implements the signal and a C2 check, and then performs signal interpolation Processing and servo control required by compact disk OF previous value hold depending on the C2 flag. The players, laser disks, CD-V, CD-I and related products. interpolation circuit uses a quadruple interpolation The LC7861KE provides several types of signal scheme. The circuit holds the previous value for up to processing to reduce the cost of CD player units, including . ou vot fence 2 fags. fi trol mi demodulation of the optical pickup EFM signal, de- * DUPPOW Tor commanc Impl from a control micro- interleaving and error detection and correction. It also Processor: commands inc u © track Jump, focus start, processes a rich set of servo system commands sent from disk motor start/stop, muting on/off and track count the contro} microprocessor. It can directly interface to the Pann Serial input) a dedicated serial inputs provided by the Sanyo LC78815 unitin digital output circuits and LC78816 D/A converters, * Arbitrary track counting to support high-speed data access Functions * Zero cross muting . . + Support for double speed dubbing * Input 1 2 Th 61KE tak HF pur signal Processing: The Lev we takes an © * Complete support for CD-ROM products. The signal as input, digitizes (slices) that signal at a precise . : . level, converts that signal to an EFM signal, and LC7861KE directly interfaces with the Sanyo LC89510 , , and can also handle CD-ROM XA applications. generates a PLL clock with an average frequency of +
4.3218 MHz by comparing the phases of that signal and * Output signals for use by external D/A converters to
a VCO output improve the output data continuity by oversampling and + Precise reference clock and necessary internal timing digital filtering generation using an external 16.9344 MHz crystal Features oscillator . A * Disk motor speed control using a frame phase difference * Compact and space-saving 64-pin QIP package signal generated from the playback clock and the ° Silicon-gate CMOS design (low power dissipation) reference clock * Single 5 V power supply (suitable for portable sets) * Frame synchronization signal detection, protection and * DEMO pin for improved operability in adjustment interpolation to assure stable data readout ; | Package Dimensions (3159-QFP64E) * EFM signal demodulation and conversion to 8-bit . symbol data unit: mm * Subcode data separation from the EFM demodulated signal and output of that data to an external (L07861KE] microprocessor 7. + Subcode Q signal output to a microprocessor over the o CI - serial interface after performing a CRC error check o. Oo.8 1.9 + Demodulated EFM signal buffering in internal RAM to “Tal ARRARARA ett ie handle up to +4 frames of disk rotational jitter ts = * Demodulated EFM signal reordering in the prescribed = = order for data unscrambling and de-interleaving ¥ = ES + Error detection, correction, and flag processing (dual | = = error correction scheme: C1 plus dual C2 correction) = = o.35/| a SANYO: QFP64E SANYO Electric Co., Ltd. Semiconductor Business Headquarters NI594TH (OT) No, 4818-1/18
Equivalent Circuit Block Diagram 2 crere EE gs 2 & Bags gs gs t ib B22 8 eee’ 8 s is imi ~ ree o-—-—0000 nn i i VCO dock | — — | C4 cercux Sravaiaion Ly rseol} 5 interpolation Oasy i G ronovr cuve CLV digital C1 and C2 error detection H e.v-O servo and correction | veo Flag processing | sesy.srsy eer | t waa.soour (] Micyoprocmasor eae {pour 4A infotace TaR — | ane D Servo system interface pewo O} command Timing generation | So J — OF IN me O—-o00—o—-0 aa -—o0-0000—-~ Sae@ei gb ze eo nz ES ee eyes gBR&s 3 2 Bes 2 225 22333 So ggee * & o * cee egs e Efe 2 i sooan Pin Assignment cn lB TSSUBRTERTER AE] ng o/80 aa sure anc ets! 2° Ls orare corne 53 oer Tests rolls 27Loewo wegelss 261 yon wr else aa vee orsen ols? LC7861KE 24h von rowelse aaloresrs snobs 22h tae conreteo ail ere. vestseles 20L erorr weelee 13h ersce xaur oe) vores Lobe eye 282 sets se 19 se ose | Sa a Oa Oa ae ee . BT TEPEREESESEERS Top View No. 4818-2/18
Absolute Maximum Ratings at Ta = 25°C, Vgg = 0 V a [Nexium suppyvetege | Vppmexf SSCS gS] | a a a SEELATE CO [Outvotegs Your fo —*di gg = 0810 op 03] | [Atowabiepowersispaten Pama [S| [perio enperaire | opr | SSSSCSC*d as || [Storageterperatwe te PO CC~™COCCCSCSCSCSC RH v2 | Allowable Operating Ranges at Ta = 25°C, Vs, = 0 V [Perret | symbo [ seniors Sd ine || SL [Wu (t)_[ TESTI i6 5 Ai FOB HL, DEMO, OFOFF. Wi, RES| 07 Vp |_| Yoo |v | wputhighlovevotage -»«(_NINL@) [880K RWC. CON,COCK S| | Vo? |__| RC 0 [way [es] 09856 |e [Va (| TEST 1105, A FID, AFL, DENS, OFOFE MARES [Ves || 8p | V_| Inputlow level votage | Vite) [SBCK RWC CON, COOKS Veg [os |v | a OC a 7 [Dee seuptine [tip [oon refer woof [Deteragtine | thas RG Fguve Pa [High velclockpise with | Way | S80X, COCK Fgues.2ands——SC*CSC woo | dT [Lowivelciekpueewan [wn | S80K, COCK Fires t.2end3__—S—S* ao | [Datereadeccesstine [tao [Faweszend3 SS SSCSSCSCSC*SSSCi Pit] | |Commandoupurime [awe [AWG Fgwet Poo TT [Seeareesenabiotie [toe | Fawez.noRWCsgral SY | dr [Subeoderondeyee ewes | i | SG Os [es ovsitrteauensy | Ott [iy Houy | i PAT Electrical Characteristics at Ta = 25°C, Vgc = 0 V, Vpp = 5 V a [Spyeinen tg PS a | ee ia ee Input high level current HFL, RWC, ML: Vin = Vo | t@) [TEST 105, DEMO, TESTA OB Vy=Voo=65V_| |__| 7 [a Sr A ta HFL, RWC, ML: Vin = Vsg AO, PDO, EFMO, EFMO, CLV+, CLV-, FOCS, FSEQ, Bc FSX, V/P: lo = 1 mA TASER, SQOUT, 16M, 4.2M, CONT, SMP, SMP1, oe ee , SBSY, CK2, PW, ROMOUT, C2FCLK: ‘DD lon = -0.5 mA Continued on next page. No, 4818-3/18
[ne [Name [QT asepton {+ | tests [1 _[ Lsttestpin. Normally left open. 2 | 0 fo Inputs for the LA9210 internal VCO output. (8.6436 MHz) H+ Set up PDO so that the frequency increases when the EFM signal and the phase output are positive. a ES [7 | ermo | 0 _| Supply en HF signal witha 1 to 2 Vp-p level to EFMIN. EFMO and EFM output EFM signals with opposite phases that passed through an amplitude limiter circuit. These are used for slice fevel contro! [oe [erwin Pt | 2 | Teste | 1 | LSitestpin, Normally lett open. = [OT isk motor conte! expat Te [12 | we | © | Outputs a high level during CLV rough servo anda low level during phase control. Se FOGS outputs a high level whan the focus servo is off. The lens is lowered by FST, and when FOCS is high the lens is st reised gradually. FOCS is reset when an FZD input occurs. These are used for focus pullin, Los | roy | ae Pz Pres TT eck isthe 4.2218 monitorpin [18 [| PcK [© | Itouputs a high ieve! when the synchronization (positive FS) detected from the EFM signal matches the counter [19 | FSEQ | 0 _| syrchronization interpolation FS). (The output is itched fora single frame.) [stor [0 [21 [7 tat] © | the Lc7861Ké outputs a kick pulse from JP* and JP in response to @ track jump command. A track jump of the [22 [| THD | © _| specitied number of tracks (1, 4, 16, 32, 64, and 128) is performed. TEST3 [1 _| Lsitest pin, Normally left open. [| Yoo [=] sv [|e |e] [27 | DEMO | 1 | Sound output function for end product adjusiment manufacturing stops. [28 | tests [1 | LSltestpin, Normally let open. [29 | EMPH | © | De-emphasis is required when high, | 30 | OFOFF | 1 _ | Digital fiter on/off switch, Fitering is tured off on a high level input [3[ swe] 0] [_s3_ [7 trotk [0 | outputs for an external D/A converter. These include a latch signal, an UR ‘switching signal, and a sample and hold [2 [sue 0] a [sxx [0] [37 | OFIN | © | LSItestpin. Normally left open. creo] | 29 | cee {70 | [40 [| ROMOUT | 0 | CD-ROM application output signals [ai] carci To] | 2 | car | | | 43 [pour | 0 | Digit output [44 | sasy [| © | Subcode block synchronization signat [ 45 | EFLG | 0 | C1, C2, single and double error correction monitor pin [a7] Pet SFSY is the subcode frame synchronization signal. The P, Q, R, S, T, U, V and W subcodes can be read out by = applying 8 clock cycles to SBCK. | 49 | Fsx | o | 7.35 kHz synchronization signal output ee WRG goes high when the subcode Q data passes the CRC check. An external controller can read out data trom SQOUT by monitoring this pin and applying a COCK signal. Set M/L to low when data is required LSB first [se [scour ~o| Continued on next page. ne No, 4818-5/18
Continued from preceding page. The control microprocessor can send commands to the LC7861KE by setting RWC high and then sending command data synchronized with COCK. tt is also possible to read out the TOC memory data by sending CQGK from the SQOUT pin by command switching. [85 | RES | 1 | This pin mustbo set lowbriolly alter power is first appliod. ssf om | | [57 _| Tasen [0 | Ouiputsin conrtato by set aaa set tar ha misoprosenae [se [set [0 | tessemrzowpipn [39 | “sam [0 | azase une oupuipn [60 | Sonr—|“0-_| Ouiputinconrtabe by sel daa son fom he misoprosenoe [er | tests [1 | Lsitestpin. Normally loft open. [62 | tS [1 _| Chipsotectpin. The LC7861KE becomes active when this pin is low. (A pull-down resistor is builtin.) | [xv [| Connections for a 16,9344 MHz crystal oscillator Les | xour [2 Pin Applications 1, HF signal input circuit; Pin 8: EFMIN, pin 7: EFMO, pin 6: EFMO An EFM signal (NRZ) with an optimal slice level can be acquired by inputting the HF signal to EFMIN. HF _J ie | 2. PLL clock generation circuit; Pin 4: PDO, Pin 3: Al, Pin 2: AO I _—n | | 2 cK Yop PDO a BR EFM(NRZI) LA9210 8 A VCO can be constructed by combining the LC7861KE with the Sanyo LA9210. The PDO pin swings in the positive direction when the VCO phase lags. a No, 4818-6/18
- 1/2 VCO; Pin 18: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is the VCO frequency divided by two. 4. Synchronization detection monitor; Pin 19: FSEQ Pin 19 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is a synchronization detection monitor. (It is held high for a single frame.) 5. CLV servo circuit; Pin 10: CLV*+, pin 11: CLV-, pin 12: V/P a oo0000100 DISC MOTOR START (accelerate)
00000101 DISC MOTOR CLV (CLV)
o0000110 DISC MOTOR BRAKE (decelerate) ooo000111 DISC MOTOR STOP (stop) The CLV* pin provides the signal that accelerates the disk in the forward direction and the CLV- pin provides the signal that decelerates the disk. Commands from the control microprocessor select one of four modes; accelerate, decelerate, CLV and stop. The table below lists the CLV* and CLV- outputs in each of these modes. [feceteete [Hoh | tow _| [Deceterate [tow | High | [av [= + [See | tow | tow] Note: *In CLV mode the LC7861KE detects the disk speed from the HF signal and provides proper linear speed using several different control schemes by switching the DSP internal modes. The PWM period is 7.35 kHz, the 1/64 duty period is 1.114s, and V/P outputs a high level during rough servo and a low level during phase control. [tow High High ee a ] cly— WICLY¥+ DISK MOTOR a L Note: After a CLV servo contro! command, the TOFF pin will be at the low level only for CLV mode, and will be high for all other modes. Controlling the TOFF pin by microprocessor command is only possible in CLV mode.
ee eSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSsSSSsSsSssssssseseseFee 6. Subcode P, Q, and R to W output circuit; Pin 46: PW, pin 44: SBSY, pin 47: SFSY. pin 48: SBCK PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to the SBCK pin within 136 is after the fall of SFSY. The signal that appears on the PW pin changes on the falling edge of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output for each subcode frame cycle, and the rising edge of this signal indicates standby for the output of the subcode symbol (P to W). Subcode data P is output on the fall of this signal SFsY a a see PLS LEU LEU LL mw “or XoXo Ke Xs Xr Yu Xv Vw Yo Ye SBSY is a signal output for each subcode block. This signal goes high for the SO and $1 synchronization signals. The fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode block. (EIAJ format) So St Sz sa 8H ST, SOS 82 Pe pap ap Ral ‘SBSY ev FT LELPLPU Ly SISAL 7. Subcode Q output circuit; Pin 50: WRQ, pin 51: RWC, pin 52: SQOUT, pin 54: COCK, pin 56: M/L, pin 62: CS a oT 00001001 ‘ADDRESS FREE
10001001 ADDRESS 1 °
TOOoOTT1O ‘OSC ON o 1ooo11014 OSC OFF Subcode Q can be read from the SQOUT pin by applying a clock to the CQCK pin. Of the eight bits in the subcode, the Q signal is used for song (track) access and display. The WRQ will be high only if the data passed the CRC error check and the subcode Q format internal address is 1*. The control microprocessor can read out data from SQOUT in the order shown below by detecting this high level and applying COCK. When COCK is applied the DSP disables register update internally. The microprocessor should give update permission by setting RWC high briefly after reading has completed, WRQ will fall to low at this time. Since WRQ falls to low 11.2 ms after going high, CQCK must be applied during the high period. Data can be read out in an LSB first format if the MIL pin is set low, and in an MSB first format if that pin is set low. Note: * That state will be ignored if an address free command is sent. This is provided to handle CDV applications.
5 Wien MA is high
Grangewin | [MINT note: + toms in parontoses refer to the readin aca. fF the = Mp. a SSSSSSSSSSSSSSSSSSSSSSSeSSSsseeeeeeEe No. 4818-8/18
ee SeeeSeSSeSsSsSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSSeee wra | cack J J ofp - le CONT “ADR “AFLAME RWC Note: 1. Normally, the WRQ pin indicates the subcode Q standby state. However, it is used for a different monitoring purpose in track count mode. (See the item on track counting for details.) 2. The LC7861KE becomes active when the CS pin is low, and data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin goes to the high impedance state. 3. The “OSC OFF” command turns off the VCO and the crystal oscillator. 8. Servo command function; Pin 51: RWC, pin 53:COIN, pin 54: CQCK, pin 62: CS Instructions can be input to the LC7861KE by setting RWC high and sending commands in synchronization with the CQCK. The LC7861KE is basically upwardly compatible with the earlier LC7860K and LC7863K with respect to the control microprocessor. The commands can be classified as follows. New commands not supported by the earlier LC7860K and LC7863K are marked with a “ ©)” in the command table. Focus start Track jump Mute control 1-byte commands Disc motor control Other contro! commands Track count ‘] 2-byte command * One-byte commands RWC caK l t t LsB SB * Two-byte commands RWC cack l Commands are executed starting at the fall of the RWC signal. No. 4818-9/18
- Focus servo circuit; Pin 13: FOCS, pin 14: FST, pin 15: FZD, pin 57: LASER Commands [sang >
00001000 FOCUS START #1
10100010 FOCUS START #2
10001010 LASER OFF
00000000 NOTHING
When a focus start instruction (either FOCUS START #1 or FOCUS START #2) is input as a servo comman4, first the charge on capacitor C1 is discharged by FST and the objective lens is lowered. Next, the capacitor is charged by FOCS, and the lens is slowly raised. FZD falls when the lens reaches the focus point. When this signal is received, FOCS is reset and the focus servo turns on. After sending the command, the microprocessor should check DRF to confirm focus before proceeding to the next part of the program. If focus is not achieved by the time C1 is fully charged, the microprocessor should issue another focus command and iterate the focus servo operation. + LASER control RWC Tack com 00000000 GEE 00000000. TASER + Focus start (Values in parentheses are for the LASER START #2 command. The only difference is in the FST low period.) a rr tack con Ko XoXoX1XoX oXoXo} FST = $0ms(240ms) Focs Fz0 — AnFZD falling edge will not be accepted during the period that FST is low. — Afier issuing a focus start command, initialization will be performed if RWC is set high. Therefore, do not issue the next command during focus start until the focus coil drive S curve has completed. — When focus cannot be achieved (i.c., when FZD does not go low) the FOCS signal will remain in the high state, so the microprocessor should initialize the system by issuing a NOTHING command. — When the RESET pin is set low, the LASER pin is set high directly. — Focus start using the DEMO coil executes a mode #1 focus start. FE Tey r 7 ™ WV =v +5V 8 aie No. 4818-10/18
—SSSSSSSSSSSSSSSSSSSSSSSSSSSsSsSSSssseeeeee 10. Track jump circuit; Pin 16: HFL, pin 17: TES, pin 20: TOFF, pin 21: TGL, pin 22: THLD, pin 25: JP+, pin 26: JP- a c
10100000 TRACK JUMP (earlier version)
10100001 TRACK JUMP (new command)
10001100 TRACK JUMP BRAKE
1o0oot1114 TON fe} 00010001 1 TRACK JUMP iN #1 ooo010010 1 TRACK JUMP !N #2 00110001 1 TRACK JUMP IN #3 00010011 4 TRACK JUMP IN 00010100 46 TRACK JUMP IN 00110000 32 TRACK JUMP IN ooo010101 64 TRACK JUMP IN ooor0114 128 TRACK JUMP IN ooot1001 1 TRACK JUMP OUT #1 ooo011010 1 TRACK JUMP OUT #2 00111001 4 TRACK JUMP OUT #3 ooo011o1d 4 TRACK JUMP OUT 00011100 16 TRACK JUMP OUT 00111000 32 TRACK JUMP OUT ooo011101 64 TRACK JUMP OUT ooo11nid 128 TRACK JUMP OUT [ee orerto | Sas tac cnecK Sd iY JP-(+) sPe-) BKEA TOL THLD l a b 3 > When the LC7861KE receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the specified jump. During the braking period, the LC7861KE detects the beam slip direction from the TES and HFL. inputs. TOFF is used to cut the components in the TE signal that aggravate slip. The jump destination track is captured by increasing the servo gain with TGL. In all the disk motor control operations, the TOFF pin only goes low during CLV mode, and will be high during the start, stop, and brake operations. Note that the TOFF pin can be tumed on and off independently by microprocessor issued commands. However, this function is only valid when disk motor contro] is in CLV mode. The table lists the relationships between accelerating pulses, deceleration pulses and the braking period. sss No. 4818-11/18
—. SS command Standard track jump mode New track jump mode poe ee {TRAE JUMPIN (UT) 43 [os acum STRACK UMPIN (OUT) [2eackiump [486 58] 100s | avack jump TS TANCK JUMPIN (OUT) [eveck ump | Taaekiunp [1008 | evackiump [poe | 100s S2TRAGKIUMPIN GUT) [eaackump __[‘a-veckiune [100s | teiackiump | veteckiomp [1006 | GATRACK MPI OUT) [26-tackiomo | BB-vackiump [100s | Sewrasciump | #eiaokiume | tooms |
128 TRACK JUMP IN(OUT) | 72-trackjump | 56-trackjump | 100ms ___| 72drackjump 5é6-track jump
TOFF goes high alter 256 tracks are TOFF goes high after 256 tracks are 256 TRACK CHECK jumped. The a and b pulses are not | 100 ms jumped. The a and b pulses are not | 100 ms output. output. TRACK JUMP BRAKE There are no a or b periods. There are no @ or b periods, [iooms Note: 1. As indicated in the table, actuator signals are not output during the 256 TRACK CHECK function. This is a mode in which the TES signal is counted in the TRACKING LOOP OFF state. Therefore, feed motor forwarding is required. 2. The servo command register is automatically reset after the track jump sequence (a, b, c) completes. 3. If another track jump command is issued during a track jump operation, the content of that new command will be executed starting immediately. 4. The maximum braking time (period c) has been changed from the 17 ms of the earlier LC7861NE to 100 ms in the LC7861KE. te T.coit 1» | 2 a 20, | 2s HEL 6 iz a tes 1? | Slip detector I BKEA 11. Track counting circuit; Pin 16: HFL, pin 17: TES, pin 20: TOFF y1110000 TRACK COUNT IN .
11111000 TRACK COUNT OUT
tirtradry TWO-BYTE COMMAND RESET ie} tooo T1O00 TRACK JUMP BRAKE [ The LC7861KE will count the specified number of tracks when the microprocessor sends an arbitrary binary value in the range 16 to 254 after issuing either a track count in or a track count out command. The TOFF pin will output a high level during the track count operation and the tracking loop will be tumed off. Therefore, feed motor forwarding is required. eS No. 4818-12/18
invout command Desired wack Two byte command reset Brake command count binary input Track count i Rises at track counv2. Falls when the track count completes. Note: 1. When the desired track count is input in binary, the track count operation is started by the fall of RWC. 2. When a track count in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function to a track count monitor function. This signal goes high when the track count is half completed, and goes low when the count finishes. The control microprocessor should monitor this signal to determine when the track count completes. 3. If atwo-byte command reset command is not issued, the track count operation will be repeated. That is, to skip over 20,000 tracks, issue a track count 200 command once, and then count the WRQ signal 100 times. 4. After performing a track count operation, use the brake command to have the pickup lock onto the track. The track count operations in items 10 and 11 basically count the TES signal from the LA9210. The following two clocks are provided internally in the LC7861KE as track counting clocks. To use the earlier track count function, initialize the LC7861KE with a 23H command when power is first applied. a 2 NEW TRACK COUNT FUNCTION Oa100018 (using the TES/HFL combination) ° EARLIER TRACK COUNT FUNCTION oor 00011 (directiy counts the TES signa!) The earlier track count function uses the TES signal directly as the internal track counter clock. To reduce counting errors resulting from noise on the rising and falling edges of the TES signal, the new track count function prevents noise induced errors by using the combination of the TES and HFL signals, and implements a more reliable track count function. However, dirt and scratches on the disk can result in HFL signal dropouts that may result in missing track count pulses. Thus care is required when using this function. 12. Adjustment process sound output function; Pin 27: DEMO 30us min RWC (EMO Set directly clv Constant linear velocity mode Conditions under which FOCS goes low © When focus is pulled in and the FZD pin has gone to zero. ® When the RES pin is low or the AWC pin is high MUTE 048 4 Therefore, when setting DEMO high, RWC must Foes be low __I an @ DEMO pins tow —E “3 FST By setting this pin high, muting can be set to 0 dB, the disk motor can be set to CLV, and a focus start operation can be performed, even without issuing any commands from the contro! microprocessor. Also, since the LASER pin becomes active, if the mechanism and servo systems are complete, sound can be produced without the presence of a microprocessor. SSS : No. 4818-13/18
oo SeeeSSeSeSSSSssFFSSSSSsSFSSSSSSSSSSSsssssSSsssssssSMSSMFFMFsSeee 13, Reset circuit; Pin 55: RES. When power is first applied, this pin should be briefly set low and then set high. This will set the muting to -e- dB and stop the disk motor. +5V 5 : + | 14. De-emphasis ON/OFF; Pin 29: EMPH The preemphasis on/off bit in subcode Q control information is output from the EMPH pin. De-emphasis should be performed when this signal is high. 15. Error flag output; Pin 45: EFLG, pin 49: FSX. ct : cz Single geen 7 correction -rLIN LI Correction not CLF LST LI 1 possible No error The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal. The error correction state for each frame is output from EFLG. The playback OK/NG state can be easily determined from the extent of the high level that appears here. 16. Crystal clock oscillator; Pin 63: Xyy, pin 64: Xoyt a =e
10001110 OSC ON 3°
10001101 OSC OFF
TY000001 DOUBLE SPEED MODE
11000010 NORMAL MODE °
017100000 VCO 6M
01100001 VCO 16M
No. 4818-14/18
eeeeeSeSsSsSssSSSeseseSessSsssSsSSSseeSeSeSSSSSSSSSSSSSSSe The clock that is used as the time base is generated by connecting a 16.9344 MHz crystal @3 rr) 64 oscillator between these pins. This oscillator can Hl CI Rd be turned on and off under command control. Xtal cor ato son (The OSC OFF command turns off both the VCO ==. 16.9344MHz yout 160oMH2 and crystal oscillators.) ia iin Je Je" Also, the LC7861KE can be set up to handle double speed operation under command control. The table lists the relationships between the crystal and VCO oscillators. WOO piybackepeod | Wadee———nte J [ Narmatspeedimade [cute spsedrode | Nomalspeedmode | iia speeded | SO [Apinenemalinpa(envoo)——eawsewme [| | [Ain externa (STM VEO) frre TO] RE ee ee Crystal Clock Oscillator Recommended Values ‘CSA-309 omen WATCH CO.,LTD. Ho491U.S . oF to a2 PF ys} (16.9344 MHz) * Rd = 100 2 (220%) (Ceramic resonator) d= 47 0 (220%), FCRI6.93MCG | in = Cout = 30 pF (bull in) Note: Since the conditions on the circuit board actually used will vary, the values of the load capacitances Cin and Cout must be verified on the circuit board actually used.a 17. D/A converter interface; Pin 30: DFOFF, pin 34: SMP, pin 33: LRCLCK, pin 35: DFOUT, pin 36: DACLK, pin 32: SMPI, pin 31: SMP2 Data for the D/A converter is output MSB first from DFOUT synchronized with the falling edge of DACLK. .
12 Ly 10 1s Dn as w» s 40 4s 4812
LRCLK (LIS) TT _ LRCLK a Ce sMet | SMP2 ee LL i ee Four u sococacoouGaaaadg' ° CEGQOCDCHOGRGR000 MSB LcH tse MsB RCH tse Note: DACLK = 4.2336 MHz (when DFOFF is low) DACLK = 2.1168 MHz (when DFOFF is high) eee No, 4818-15/18
a o1100010 lS ON
01100011 US OFF is)
10001000 CDROM XA
100010114 CONT AND CD-ROM XA RESET °
When a CD-ROM XA command is issued, data that is neither interpolated nor muted will be output from the DFOUT and DOUT pins. (This command is used for CD-ROM XA application.) The CD-ROM XA reset command also functions as a pin 60 CONT reset, so caution is required. 18. CD-ROM outputs; Pin 39: CK2, pin 37: LRSY, pin 40: ROMOUT, pin 42: C2F, pin 41: C2FCLK. Data is output MSB first from the ROM OUT pin in synchronization with the LRSY signal. This data is appropriate for input to a CD-ROM LSI, since it is not interpolated, previous value held, or processed by the digital filter circuits. CK2 is a 2.1168 MHz clock, and data is output on the CK2 rising edge. C2F is the flag information for data in 8-bit : units. C2FCLK is the synchronization signal for that flag. LC8951 and LC7861 Interface HBHCVT2 7 FEIONRDKHUM WIDANRBDKASBHRVKBWHM WHOL AM KO oy wrsy ft tcH 5, a MsB \\sa use ise roveut \\_y 9° FREE OOOO ROE HOROO, - HEGRE RARER WE 19. Mute control circuit ooo0o00001 MUTE: 08 ooo000010 MUTE: -12 dB ooo0o0o0018 MUTE: © dB ° An attenuation of 12 dB (MUTE —12 dB) or full muting (MUTE ce dB) can be applied by issuing the appropriate command from the table. Since zero cross muting is used, there is no noise associated with this function. Zero cross is defined for this function as the top seven bits being all ones or all zeros. 20. 4.2M and 16M pins; Pin 59: 4.2M, pin 58: 16M The 16.9344 MHz external crystal oscillator 16.9344 MHz buffer output signal is output from the 16M pin, That frequency divided by four (a 4.2336 MHz frequency) is output from the 4.2M pin. When the oscillator is turned off both these pins will be fixed at either high or low. These frequencies do not change when a double speed command is issued. 21. Digital output circuit; Pin 43: DOUT This is an output pin for use with a digital audio interface. Data is output in the EIAJ format. This signal is a signal that has passed through the interpolation and muting circuits. This pin has a built-in driver circuit and can directly drive a transformer. SSS No. 4818-16/18
SSSSSSSSSSSSssSsSSsSSSSSSSSSSSSSSSSSSSssSssSSSSssFFFFFFFSSSe. 22. CD-ROM XA; Pin 60: CONT The LC7861KE switches to CD-ROM XA mode when an 88H command is issued and data that has not passed through the interpolation circuit is output from the DFOUT pin. The LC7861KE returns to normal mode when an 8BH command is issued, and interpolated data is output. Note that the 8BH command also functions as a CONT pin (pin 60) reset. [8 88 er ow) A 23. CONT pin; Pin 60: CONT a DS A [rere cont cenomanesr Pin 60 will goes high when this command is issued. 24. Other pins; Pin 1: TESTI, pin 9: TEST2, pin 23: TEST3, pin 28: TEST4, pin 37: TESTS, pin 61: TESTS These pins are used for testing the LS!’s internal circuits. Since the pins TEST1 to TEST 5 have built-in pull-down resistors, they can be left open in normal operation. Circuit Block Operating Descriptions 1. RAM address control The LC7861KE incorporates an 8-bit x 2k-word RAM on chip. This RAM is used as a buffer memory, and has an EFM demodulated data jitter handling capacity of +4 frames. The LC7861KE continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the PCK side of the CLV servo circuit and the frequency divisor. If the +4 frame buffer capacity is exceeded, the LC7861KE forcibly sets the write address to the +0 position. However, since the errors that occur due to this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period. a a eC ae 2. Cl and C2 error correction The EFM demodulated data is written to internal RAM to compensate for jitter, and the LC7861KE performs the following processing with a constant timing based on the crystal oscillator clock. First, the LC7861KE performs C1 error checking and correction in the C1 block, determines the C1 flags, and writes the C1 flag register. Next, the LC7861KE performs C2 error checking and correction in the C2 block, determines the C2 flags, and writes data to internal RAM. [stig | resort anttna rornere No errors No correction required - Flag reset 1 error Correction - Flag reset 2 errors Correction - Flag set Jorrors or mora Correction not possible - Flag set To SSSSSSSSSeeSSSsSSsseseseSessSesSsSsSsssseeeseeeee No. 4818-17/18
HS SSSSSSSSSSS— C2 flag Error correction and flag processing No errors No correction required - Flag reset Tertor Correction - Flag reset 2errors Depends on C1 flags" errors or more Depends on C1 flags’? Note: 1. Ifthe positions of the errors determined by the C2 check agree with the those specified by the C1 flags, the correction is performed and the flags are cieared. However, if the number of C1 flags is 7 or higher, C2 correction may fail, In this case correction is not performed and the Ct flags are taken as the C2 flags without change, Error correction is not possible if one error position agrees and the other does not. Furthermore, if the number of C1 flags is 5 or under, the C1 check result can be seen as unreliable. Accordingly, the flags will be set in this case. Cases where the number of C1 flags is 6 or more are handied in the same way, and the C1 flags are taken as the C2 flags without change. When there is not even one agreement between the arror positions, error correction is, of course, impossible, Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. The other C1 flags are taken as the C2 flags without change. 2, When data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now sean as incorrect data. The flag is set in this case. The other C1 flags are taken as the C2 flags without change. MENo products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. M Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO, LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally, Mi Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. ee No, 4818-18/18 '