LC75812PT

LC75812PT SANYO | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 54

Technical content

Features

Key input function for up to 35 keys (A key scan is performed only when a key is pressed.)
Controls and drives a 5×7 or 5×8 dot matrix LCD.
Supports accessory display segment drive (up to 65 segments)
Display technique: 1/8 duty 1/4 bias drive (5×7 dots) 1/9 duty 1/4 bias drive (5×8 dots)
Display digits: 13 digits×1 line (5×7 dots), 12 digits×1 line (5×8 dots)
Display control memory CGROM: 240 characters (5×7 or 5×8 dots) CGRAM: 16 characters (5×7 or 5×8 dots) ADRAM: 13×5 bits DCRAM: 52×8 bits
Instruction function Display on/off control Display shift function Continued on next page. CMOS IC 1/8, 1/9 Duty Dot Matrix LCD Display Controllers/Drivers with Key Input Function
CCB is a registered trademark of SANYO Semiconductor Co., Ltd.
CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO Semiconductor for this format.

No.A1417-2/54 Continued from preceding page.

Sleep mode can be used to reduce current drain.
Built-in display contrast adjustment circuit
Switching between key scan output and general-purpose output ports can be controlled with instructions.
PWM output for adjusting the LED backlight brightness
The frame frequency of the common and segment output waveforms can be controlled by instructions.
Serial data control of switching between the RC oscillator operating mode and external clock operating mode.
Independent LCD driver block power supply VLCD
A voltage detection type reset circuit is provided to initialize the IC and prevent incorrect display.
The INH pin is provided. This pin turns off the display, disables key scanning, and forces the general-purpose output ports to the low level.
RC oscillator circuit Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Symbol Conditions Ratings Unit VDD max VDD -0.3 to +4.2Maximum supply voltage VLCD max VLCD -0.3 to +11.0 V CE, CL, DI, INH -0.3 to +4.2VIN1 CE, CL, DI, INH VDD=2.7 to 3.6V -0.3 to +6.5 VIN2 OSC, KI1 to KI5, TEST -0.3 to V DD +0.3 Input voltage VIN3 VLCD1, VLCD2, VLCD3, VLCD4 -0.3 to V LCD +0.3 V VOUT1 DO -0.3 to +6.5 VOUT2 OSC, KS1 to KS7, P1 to P3 -0.3 to V DD +0.3 Output voltage VOUT3 VLCD0, S1 to S65, COM1 to COM9 -0.3 to V LCD +0.3 V IOUT1 S1 to S65 300 μA IOUT2 COM1 to COM9 3 IOUT3 KS1 to KS7 1 Output current IOUT4 P1 to P3 5 mA Allowable power dissipation Pd max Ta=85°C 200 mW Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C Allowable Operating Range at Ta = -40°C to +85°C, VSS = 0V Ratings Parameter Symbol Conditions min typ max unit VDD VDD 2.7 3.6 VLCD When the display contrast adjustment circuit is used. 7.0 10.0 Supply voltage VLCD VLCD When the display contrast adjustment circuit is not used. 4.5 10.0 V Output voltage V LCD0 V LCD0 V LCD4 +4.5 V LCD V VLCD1 V LCD1 3/4 (VLCD0- VLCD4) VLCD0 VLCD2 V LCD2 2/4 (VLCD0- VLCD4) VLCD0 VLCD3 V LCD3 1/4 (VLCD0- VLCD4) VLCD0 Input voltage VLCD4 VLCD4 0 1.5 V Continued on next page.

No.A1417-3/54 Continued from preceding page. Ratings Parameter Symbol Conditions min typ max unit CE, CL, DI, INH 0.8VDD 3.6VIH1 CE, CL, DI, INH VDD=2.7 to 3.6V 0.8VDD 5.5 VIH2 OSC external clock operating mode 0.8VDD V DD Input high level voltage VIH3 KI1 to KI5 0.6VDD V DD V VIL1 CE, CL, DI, INH, KI1 to KI5 0 0.2V DDInput low level voltage VIL2 OSC external clock operating mode 0 0.2V DD V Output pull-up voltage VOUP DO 0 5 . 5 V Recommended external resistor for RC oscillation Rosc OSC RC oscillator operating mode 10 k Ω Recommended external capacitor for RC oscillation Cosc OSC RC oscillator operating mode 470 pF Guaranteed range of RC oscillation fosc OSC RC oscillator operating mode 150 300 600 kHz External clock operating frequency fCK OSC external clock operating mode [Figure 4] 100 300 600 kHz External clock duty cycle DCK OSC external clock operating mode [Figure 4] 30 50 70 % Data setup time tds CL, DI [Figure 2],[Figure 3] 160 ns Data hold time tdh CL, DI [Figure 2],[Figure 3] 160 ns CE wait time tcp CE, CL [Figure 2],[Figure 3] 160 ns CE setup time tcs CE, CL [Figure 2],[Figure 3] 160 ns CE hold time tch CE, CL [Figure 2],[Figure 3] 160 ns High level clock pulse width tφH CL [Figure 2],[Figure 3] 160 ns Low level clock pulse width tφL CL [Figure 2],[Figure 3] 160 ns DO output delay time tdc DO RPU=4.7kΩ C L=10pF *1 [Figure 2],[Figure 3] 1.5 μs DO rise time tdr DO RPU=4.7kΩ C L=10pF *1 [Figure 2],[Figure 3] 1.5 μs Note: *1. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL. Electrical Characteristics for the Allowable Operating Ranges Ratings Parameter Symbol Pins Conditions min typ max unit Hysteresis V H CE, CL, DI, INH, KI1 to KI5 0.1VDD V Power-down detection voltage VDET 2.0 2.2 2.4 V VI=3.6V 5.0IIH1 CE, CL, DI, INH VI=5.5V VDD=2.7 to 3.6V 5.0 Input high level current IIH2 OSC VI=VDD external clock operating mode 5.0 μA IIL1 CE, CL, DI, INH V I=0V -5.0 Input low level current IIL2 OSC VI=0V external clock operating mode -5.0 μA Input floating voltage VIF KI1 to KI5 0.05V DD V Pull-down resistance R PD KI1 to KI5 V DD=3.3V 50 100 250 k Ω Output off leakage current IOFFH DO V O=5.5V 6.0 μA VOH1 S1 to S65 I O=-20μA VLCD0-0.6 VOH2 COM1 to COM9 I O=-100μA VLCD0-0.6 VOH3 KS1 to KS7 I O=-250μA V DD-0.8 V DD-0.4 V DD-0.1 Output high level voltage VOH4 P1 to P3 I O=-1mA V DD-0.9 V VOL1 S1 to S65 I O=20μA VLCD4+0.6 VOL2 COM1 to COM9 I O=100μA VLCD4+0.6 VOL3 KS1 to KS7 I O=12.5μA 0.1 0.4 1.2 VOL4 P1 to P3 I O=1mA 0.9 Output low level voltage VOL5 DO I O=1mA 0.1 0.3 V Continued on next page.

No.A1417-4/54 Continued from preceding page. Ratings Parameter Symbol Pins Conditions min typ max unit VMID1 S1 to S65 I O=±20μA 2/4 (VLCD0 -VLCD4) -0.6 (VLCD0 -VLCD4) +0.6 VMID2 COM1 to COM9 I O=±100μA 3/4 (VLCD0 -VLCD4) -0.6 (VLCD0 -VLCD4) +0.6 Output middle level voltage *2 VMID3 COM1 to COM9 I O=±100μA 1/4 (VLCD0 -VLCD4) -0.6 (VLCD0 -VLCD4) +0.6 V Oscillator frequency fosc OSC Rosc=10kΩ, Cosc=470pF 210 300 390 kHz IDD1 VDD sleep mode 100 IDD2 V DD V DD=3.6V, output open, fosc=300kHz 500 1000 ILCD1 VLCD sleep mode 15 ILCD2 V LCD V LCD=10.0V, output open, fosc=300kHz, When the display contrast adjustment circuit is used. 450 900 Current drain ILCD3 V LCD V LCD=10.0V, output open, fosc=300kHz, When the display contrast adjustment circuit is not used. 200 400 μA Note: *2. Excluding the bias voltage generation divider resistor built into the VLCD0, VLCD1, VLCD2, VLCD3, and VLCD4. (See Figure 1.) Excluding these resistors To the common and segment drivers [Figure 1] VLCD VLCD3 VLCD4 VLCD2 VLCD0 VLCD1 CONTRAST ADJUSTER

No.A1417-5/54 (1) When CL is stopped at the low level (2) When CL is stopped at the high level [Figure 3] (3) OSC pin clock timing in external clock operating mode tdh 50% VIH1 VIH1 VIL1 VIL1 VIH1 VIL1 tdrtdc tch tcs tcp tds CL tφL tφH DO DI D1 D0 CE [Figure 2] ≈ ≈ ≈ ≈ 50% VIH1 tdh VIH1 VIL1 VIH1 VIL1 tdr tdc tchtcstcp tds CL tφH tφL DO DI D1D0 CE VIL1 ≈ ≈ ≈ ≈ ≈ ≈ [Figure 4] VIH2 VIL2 OSC tCKLtCKH fCK= [kHz] DCK= tCKH tCKH + tCKL ×100[%] 50% tCKH + tCKL

No.A1417-6/54 Package Dimensions unit : mm (typ) 3274 Pin Assignments SANYO : TQFP100(14X14) 100 12 5 5175 14.0 (1.0) (1.0)0.1 0.125 16.0 0.20.5 1.2max 0.5 14.0 16.0 S55 S51 S52 S53 S54 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65/COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 KS1/P1 KS2/P2 S11 KS4 KS6 KS5 KI1 KS3 LC75812PT (TQFP100) KI2 KI3 KI4 P3/KS7 KI5 VLCD VDD VLCD0 VLCD2 VLCD1 VLCD4 VLCD3 VSS OSC TEST INH CE DO CL S35 S34 S33 S32 S31 S29 S30 S27 S28 S26 DI 5175 50 76 26 100 251 S10 S16 S22 S15 S14 S13 S12 S21 S20 S19 S18 S17 S25 S24 S23 S40 S39 S38 S37 S36 S45 S44 S43 S42 S41 S50 S49 S48 S47 S46 Top view

No.A1417-7/54 Block Diagram S65/COM9 S64 ADRAM bits CGRAM 5×8×16 bits VDET CLOCK GENERATOR CONTRAST ADJUSTER TIMING GENERATOR ADDRESS REGISTER INSTRUCTION REGISTER COMMON DRIVER INSTRUCTION DECODER ADDRESS COUNTER DCRAM 52×8 bits CGROM 5×8×240 bits SHIFT REGISTER LATCH SEGMENT DRIVER OSC INH DO DI P1/KS1 P2/KS2 KS3 KS6 CE KI1 KI2 KI3 KI4 KI5 CL S63 COM8 COM1 KEY BUFFER CCB INTERFACE KEY SCAN VDD VLCD4 VLCD3 VLCD2 VLCD1 VLCD VLCD0 VSS TEST GENERAL PURPOSE PORT P3/KS7 KS4 KS5

No.A1417-8/54 Pin Functions Pin Pin No. Function Active I/O Handling when unused S1 to S64 S65/COM9 1 to 64 Segment driver outputs. S65/COM9 can be used as common driver output pin under the "set display technique" instruction. - O OPEN COM1 to COM8 73 to 66 Common driver outputs. - O OPEN KS1/P1 KS2/P2 KS3 to KS6 KS7/P3 76 to 79 Key scan outputs. Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. KS1/P1, KS2/P2, and KS7/P3 can be used as general-purpose output ports under the "set key scan output port/general-purpose output port state" instruction. - O OPEN KI1 to KI5 80 to 84 Key scan inputs. These pins have built-in pull-down resistors. H I GND OSC 95 Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. This pin can also be used as the external clock input pin with the "set display technique" instruction. - I/O V DD CE 98 H I CL 99 I DI 100 - I GND DO 97 Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE: Chip enable CL: Synchronization clock DI: Transfer data DO: Output data - O OPEN INH 96 Input that turns the display off, disables key scanning, and forces the general-purpose output ports low.

When INH is low (VSS):
Display off S1 to S64=”L” (VLCD4) S65/COM9=”L” (VLCD4) COM1 to COM8=”L” (VLCD4)
General-purpose output ports P1 to P3=low (VSS)
Key scanning disabled: KS1 to KS7=low (VSS)
All the key data is reset to low.
When INH is high (VDD):
Display on
The state of the pins as key scan output pins or general-purpose output ports can be set with the "set key scan output port/general-purpose output port state" instruction.
Key scanning is enabled. However, serial data can be transferred when the INH pin is low. L I V DD TEST 94 This pin must be connected to ground. - I - VLCD0 88 LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, (VLCD0 - VLCD4) must be greater than or equal to 4.5V. Also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. - O OPEN VLCD1 89 LCD drive 3/4 bias voltage (middl e level) supply pin. This pin can be used to supply the 3/4 (VLCD - VLCD4) voltage level externally. - I OPEN VLCD2 90 LCD drive 2/4 bias voltage (middl e level) supply pin. This pin can be used to supply the 2/4 (VLCD0 - VLCD4) voltage level externally. - I OPEN Continued on next page.

No.A1417-9/54 Continued from preceding page. Pin Pin No. Function Active I/O Handling when unused VLCD3 91 LCD drive 1/4 bias voltage (middl e level) supply pin. This pin can be used to supply the 1/4 (VLCD0 - VLCD4) voltage level externally. - I OPEN VLCD4 92 LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the display contrast can be implemented by connecting an external variable resistor to this pin. However, (VLCD0 - VLCD4) must be greater than or equal to 4.5V, and VLCD4 must be in the range 0V to 1.5V, inclusive. - I GND VDD 86 Logic block power supply connection. Provide a voltage of between 2.7 to 3.6V. - - - VLCD 87 LCD driver block power supply connection. Provide a voltage of between 7.0 to 10.0V when the display contrast adjustment circuit is used and provide a voltage of between 4.5 to 10.0V when the circuit is not used. - - - VSS 93 Power supply connection. Connect to ground. - - - Block Functions

AC (address counter) AC is a counter that provides the addresses used for DCRAM and ADRAM. The address is automatically modified internally, and the LCD display state is retained.
DCRAM (data control RAM) DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 5×7 or 5×8 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 52×8 bits, and can hold 52 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel.
When the DCRAM address loaded into AC is 00H. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 DCRAM address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 DCRAM address (hexadecimal) 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D (shift left) Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 DCRAM address (hexadecimal) 33 00 01 02 03 04 05 06 07 08 09 0A 0B (shift right) Note: *3. The DCRAM address is expressed in hexadecimal. DCRAM address DA0 DA1 DA2 DA3 DA4 DA5 Hexadecimal Hexadecimal Example: When the DCRAM address is 2EH. DA0 DA1 DA2 DA3 DA4 DA5 0 1 1 1 0 1 Note: *4. 5×7 dots • • • • • 13th digit display 5 ×7 dots 5×8 dots • • • • • 13th digit display 4 ×8 dots Most significant bit MSB Least significant bit LSB

No.A1417-10/54

ADRAM (Additional data RAM) ADRAM is RAM that is used to store the ADATA display data. ADRAM has a capacity of 13×5 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel.
When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 13) Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 ADRAM address (hexadecimal) 0 1 2 3 4 5 6 7 8 9 A B C However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 ADRAM address (hexadecimal) 1 2 3 4 5 6 7 8 9 A B C 0 (shift left) Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 ADRAM address (hexadecimal) C 0 1 2 3 4 5 6 7 8 9 A B (shift right) Note: *5. The ADRAM address is expressed in hexadecimal. ADRAM address RA0 RA1 RA2 RA3 Hexadecimal Example: When the ADRAM address is AH. RA0 RA1 RA2 RA3 0 1 0 1 Note: *6. 5×7 dots • • • • • 13th digit display 5 dots 5×8 dots • • • • • 13th digit display 4 dots
CGROM (Character generator ROM) CGROM is ROM that is used to generate the 240 kinds of 5×7 or 5×8 dot matrix character patterns from the 8-bit character codes. CGROM has a capacity of 240×40 bits. When a character code is written to DCRAM, the character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC.
CGRAM (Character generator RAM) CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5×7 or 5×8 dot matrix character patterns can be stored. CGRAM has a capacity of 16×40 bits. Most significant bit MSB Least significant bit LSB

No.A1417-11/54 Serial Data Input (1) When CL is stopped at the low level (2) When CL is stopped at the high level

B0 to B3, A0 to A3: CCB address 42H
D0 to D119: Instruction data The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. Instruction data (Up to 120 bits) D119 D118 D4D3D200 0 0 1 0 1 0 D0 D1 CE DI DO CL A3A2A1 A0 B3 B2B1 B0 Instruction data (Up to 120 bits) D119 D118 D4D3D21 00 0 0 0 1 0 D0 D1 CE CL DI DO A3A2A1 A0 B3 B2B1 B0

No.A1417-12/54 Notes: *7. Be sure to execute the "set display technique" instruction first after power-on (VDET-based system reset). Note that the execution time of this first instruction is 108μs (fosc=300kHz, f CK=300kHz). *8.When the sleep mode (SP = 1) is set, the execution time is 27μs (when fosc = 300kHz, fCK = 300kHz). *9. The data format differs when the DCRAM data write instruction is executed in the normal increment mode (IM1=1, IM2=0) or in the super increment mode (IM1=0, IM2=1). Note that the execution time for the DCRAM data write instruction executed in the super increment mode is tiμs (fosc=300kHz, fCK=300kHz). (See the detailed descriptions.) *10. The data format differs when the ADRAM data write instruction is executed in the normal increment mode (IM1=1, IM2=0) or in the super increment mode (IM1=0, IM2=1). Note that the execution time for the ADRAM data write instruction executed in the super increment mode is tiμs (fosc=300kHz, fCK=300kHz). (See the detailed descriptions.) *11. The execution times listed here apply when fosc=300kHz, fCK=300kHz. The execution times differ when the oscillator frequency fosc or the external clock frequency fCK differs. Example: When fosc = 210kHz, fCK = 210kHz 27μs× = 39μs, 108μs× = 155μs, tiμs× = ti×1.43μs Instruction Table X: don't care 300 210 300 210 300 210 Set AC address Display shift Display on/off control Set display technique CD25 … CD32 AD1 AD2 AD3 AD4 AD5 X X X AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 DA0 DA1 DA2 DA3 DA4 DA5 X X KC4 KC5 KC6 KC7 KP1 KP2 KP3 X C T 0 C T 1 C T 2 C T 3 X X X X DG9 DG10 DG11 DG12 DG13 X X X DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 Execution time *11 D116 D117 D118 D119 0μs 0μs 27μs 27μs 27μs 0μs/27μs 0μs/ 108μs *7 IM1 IM2 X X RA0 RA1 RA2 RA3 M A R / L X M A S C S P DT FC0 FC1 OC C T C X X X X X X X X X X X D104 D105 D106 D107 D108 D109 D110 D111 D96 D97 D98 D99 D100 D101 D102 D103 Instruction DCRAM data write *9 ADRAM data write *10 CGRAM data write Set key scan output port/ general-purpose output port state Set display contrast IM1 IM2 X X DA0 DA1 DA2 DA3 DA4 DA5 X X R A 0 R A 1 R A 2 R A 3 X X X X X X X X X X X X PC32 PF0 PF1 PF2 PF3 KC1 KC2 KC3 CD33 … CD40 W34 W35 PC10…PC31 W22…W25…W33 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 D112 D113 D114 D115 D88…D93 D94 D95 D80…D85 D86 D87 D72…D77 D78 D79 CD17 … CD24 D0…D56…D71 27μs/tiμs 27μs/tiμs *10 W10…W15 W20 W21 … CD1…CD16

No.A1417-13/54 Detailed Instruction Descriptions

Set display technique ... <Sets the display technique> (Display technique) Code D112 D113 D114 D 115 D116 D117 D118 D119 DT FC0 FC1 OC 0 0 0 1 X: don’t care DT: Sets the display technique FC0, FC1: Sets the frame frequency of the common and segment output waveforms Frame frequency FC0 FC1 1/8 duty, 1/4 bias drive f8[Hz] 1/9 duty, 1/4 bias drive f9[Hz] 0 0 fosc/3072, f CK/3072 fosc/3456, f CK/3456 1 0 fosc/1536, f CK/1536 fosc/1728, f CK/1728 0 1 fosc/768, f CK/768 fosc/864, f CK/864 OC: Sets the RC oscillator operating mode and external clock operating mode. OC OSC pin function

0 RC oscillator operating mode

1 External clock operating mode

Note: *13. When selecting the RC oscillator operating mode, be sure to connect an external resistor Rosc and an external capacitor Cosc to the OSC pin.

Display on/off control ... <Turns the display on or off> (Display ON/OFF control) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D 108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG 8 DG9 DG10 DG11 DG12 DG13 X X X M A SC SP 0 0 1 0 X: don’t care M, A: Specifies the data to be turned on or off M A Display operating state 0 0 Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG1 to DG13 data.) 0 1 Only ADATA is turned on (The ADATA of display digits specified by the DG1 to DG13 data are turned on.) 1 0 Only MDATA is turned on (The MDATA of display digi ts specified by the DG1 to DG13 data are turned on.) 1 1 Both MDATA and ADATA are turned on (The MDATA and ADATA of display digits specified by the DG1 to DG13 data are turned on.) Note: *14. MDATA, ADATA 5 ×7 dot matrix display 5 ×8 dot matrix display Output pins DT Display technique S65/COM9 0 1/8 duty, 1/4 bias drive S65 1 1/9 duty, 1/4 bias drive COM9 Note: Be sure to execute the "set display technique" instruction first after power-on (VDET-based system reset). ----- ADATA --- MDATA ----- ADATA --- MDATA Note: *12. S65: Segment output COM9: Common output

No.A1417-14/54 DG1 to DG13: Specifies the display digit Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 Display digit data DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 DG13 For example, if DG1 to DG7 are 1, and DG8 to DG13 are 0, then display digits 1 to 7 will be turned on, and display digits 8 to 13 will be turned off (blanked). SC: Controls the common and segment output pins SC Common and segment output pin states

0 Output of LCD drive waveforms

1 Fixed at the V LCD4 level (all segments off)

Note: *15. When SC is 1, the S1 to S65 and COM1 to COM9 output pins are set to the VLCD4 level, regardless of the M, A, and DG1 to DG13 data. SP: Controls the normal mode and sleep mode SP Mode

0 Normal mode

The common and segment pins go to the VLCD4 level and the oscillator on the OSC pin is stopped (although it operates during key scan operations) in RC oscillator operating mode (OC="0") and reception of the external clock is stopped (external clock is received during key scan operations) in external clock operating mode (OC="1"), to reduce current drain. Although the "display on/off cont rol", "set display contrast" and "set key scan output port/general-purpose output port state" (disallowed to set pins P1 to P3 for PWM signal output and pin P3 for clock signal output) instructions can be executed in this mode, applications must return the IC to normal mode to execute any of the other instruction setting. When the IC is in external clock operating mode, be sure to stop the external clock i nput after the lapse of the instruction execution time (27 μs: fCK=300kHz).

Display shift ... <Shifts the display> (Display shift) Code D112 D113 D114 D115 D116 D117 D118 D119 M A R/L X 0 0 1 1 X: don’t care M, A: Specifies the data to be shifted M A Shift operating state 0 0 Neither MDATA nor ADATA is shifted 0 1 Only ADATA is shifted 1 0 Only MDATA is shifted 1 1 Both MDATA and ADATA are shifted R/L: Specifies the shift direction R/L Shift direction

0 Shift left

1 Shift right

No.A1417-15/54

Set AC address... <Specifies the DCRAM and ADRAM address for AC> (Set AC) Code D104 D105 D106 D107 D108 D 109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 DA0 DA1 DA2 DA3 DA4 DA5 X X RA0 RA1 RA2 RA3 0 1 0 0 X: don’t care DA0 to DA5: DCRAM address DA0 DA1 DA2 DA3 DA4 DA5 LSB MSB ↑ ↑ Least significant bit Mo st significant bit RA0 to RA3: ADRAM address RA0 RA1 RA2 RA3 LSB MSB ↑ ↑ Least significant bit Mo st significant bit This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC.
DCRAM data write ... <Specifies the DCRAM address and stores data at that address> (Write data to DCRAM) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X IM1 IM2 X X 0 1 0 1 X: don’t care DA0 to DA5: DCRAM address DA0 DA1 DA2 DA3 DA4 DA5 LSB MSB ↑ ↑ Least significant bit Mo st significant bit AC0 to AC7: DCRAM data (character code) AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 LSB MSB ↑ ↑ Least significant bit Mo st significant bit This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a 5×7 or 5×8 dot matrix display data using CGROM or CGRAM. IM1, IM2: Sets the method of writing data to DCRAM IM1 IM2 DCRAM data write method 0 0 Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.) 1 0 Normal increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.) 0 1 Super increment mode DCRAM data write (Writes 2 to 13 characters of DCRAM data in single operation.)

No.A1417-16/54 Notes: *16.

DCRAM data write method when IM1 = 0, IM2 = 0
DCRAM data write method when IM1 = 1, IM2 = 0 (Instructions other than the “DCRAM data write” instruction cannot be executed.)
DCRAM data write method when IM1 = 0, IM2 = 1 ti=13.5μs×( -1) (n=8m+16, m is an integer between 2 and 13 that is the number of characters written as DCRAM data.) For example When n= 32 bits (m=2): ti= 40.5μs (fosc=300kHz, fCK=300kHz) When n= 80 bits (m=8) : ti=121.5μs (fosc=300kHz, fCK=300kHz) When n=120 bits (m=13): ti=189.0μs (fosc=300kHz, fCK=300kHz) Note that the instruction execution time of 27μs and ti values in μs apply when fosc=300kHz and fCK=300kHz, and that these execution times will differ when the CR oscillator frequency fosc and external clock frequency fCK differ. DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes Instruction execution time (27μs) (1) (1)(1) CCB address CCB address CCB address CCB address 24 bit 24 bit 24 bit (1) CE DI DCRAM 24 bit Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) DCRAM data write finishes DCRAM CE Instructions other than the “DCRAM data write” instruction cannot be executed. CCB address CCB address CCB address CCB address CCB address CCB address 24 bit 8 bit 8 bit 8 bit 8 bit 16 bit Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes Instruction execution time (tiμs) Instruction execution time (tiμs) Instruction execution time (tiμs) (5) (5) CCB address CCB address n bit n bit (5) CE DI DCRAM n bit CCB address DCRAM data write finishes DCRAM data write finishes n

No.A1417-17/54 Data format at (1) (24 bits) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X 0 0 X X 0 1 0 1 X: don’t care Data format at (2) (24 bits) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X 1 0 X X 0 1 0 1 X: don’t care Data format at (3) (8 bits) Code D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 Data format at (4) (16 bits) Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 0 0 X X 0 1 0 1 Data format at (5) (n bit) Code AC01 AC1 1 AC2 1 AC3 1 AC4 1 AC5 1 AC6 1 AC7 1 • • • • • • • • • • • • • • • • • • • • • • • • • • • • AC0m-1 AC1m-1 AC2m-1 AC3 m-1 AC4 m-1 AC5 m-1 AC6 m-1 AC7m-1 Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0m AC1 m AC2 m AC3 m AC4 m AC5 m AC6m AC7 m DA0 1 DA11 DA21 DA31 DA41 DA51 X X 0 1 X X 0 1 0 1 X: don’t care Here, n=8m+16, z=104-8m (m is an integer between 2 and 13 that is the number of characters written as DCRAM data.) Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DA01 to DA51 AC0 1 to AC71 (DA01 to DA51)+1 AC0 2 to AC72 (DA01 to DA51)+2 AC0 3 to AC73 (DA01 to DA51)+(m-3) AC0 m-2 to AC7m-2 (DA01 to DA51)+(m-2) AC0 m-1 to AC7m-1 (DA01 to DA51)+(m-1) AC0 m to AC7m

No.A1417-18/54 Example 1: When n=32 bits (m=2: 2 characters DCRAM data write operation) Code D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 AC01 AC1 1 AC2 1 AC3 1 AC4 1 AC5 1 AC61 AC7 1 AC0 2 AC1 2 AC22 AC32 AC42 AC52 AC62 AC72 Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 DA0 1 DA11 DA2 1 DA3 1 DA4 1 DA5 1 X X 0 1 X X 0 1 0 1 X: don’t care Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DA0 1 to DA5 1 AC0 1 to AC7 1 (DA0 1 to DA5 1)+1 AC0 2 to AC72 Example 2: When n=80 bits (m=8: 8 characters DCRAM data write operation) Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 AC0 1 AC11 AC2 1 AC3 1 AC4 1 AC5 1 AC61 AC71 AC02 AC1 2 AC22 AC32 AC42 AC52 AC62 AC72 Code D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 AC03 AC1 3 AC2 3 AC3 3 AC4 3 AC5 3 AC63 AC7 3 AC0 4 AC1 4 AC24 AC34 AC44 AC54 AC64 AC74 Code D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 AC05 AC1 5 AC2 5 AC3 5 AC4 5 AC5 5 AC65 AC7 5 AC0 6 AC1 6 AC26 AC36 AC46 AC56 AC66 AC76 Code D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 AC07 AC1 7 AC2 7 AC3 7 AC4 7 AC5 7 AC67 AC7 7 AC0 8 AC1 8 AC28 AC38 AC48 AC58 AC68 AC78 Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 DA01 DA1 1 DA2 1 DA3 1 DA4 1 DA5 1 X X 0 1 X X 0 1 0 1 X: don't care Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DA01 to DA51 AC0 1 to AC71 (DA01 to DA51)+1 AC0 2 to AC72 (DA01 to DA51)+2 AC0 3 to AC73 (DA01 to DA51)+3 AC0 4 to AC74 (DA01 to DA51)+4 AC0 5 to AC75 (DA01 to DA51)+5 AC0 6 to AC76 (DA01 to DA51)+6 AC0 7 to AC77 (DA01 to DA51)+7 AC0 8 to AC78

No.A1417-19/54 Example 3: When n=120 bits (m=13: 13 characters DCRAM data write operation) Code D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 AC01 AC1 1 AC2 1 AC3 1 AC4 1 AC5 1 AC61 AC7 1 AC0 2 AC1 2 AC22 AC32 AC42 AC52 AC62 AC72 Code D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 AC03 AC1 3 AC2 3 AC3 3 AC4 3 AC5 3 AC63 AC7 3 AC0 4 AC1 4 AC24 AC34 AC44 AC54 AC64 AC74 Code D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 AC05 AC1 5 AC2 5 AC3 5 AC4 5 AC5 5 AC65 AC7 5 AC0 6 AC1 6 AC26 AC36 AC46 AC56 AC66 AC76 Code D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AC07 AC1 7 AC2 7 AC3 7 AC4 7 AC5 7 AC67 AC7 7 AC0 8 AC1 8 AC28 AC38 AC48 AC58 AC68 AC78 Code D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 AC09 AC1 9 AC2 9 AC3 9 AC4 9 AC5 9 AC69 AC7 9 AC0 10 AC1 10 AC210 AC310 AC410 AC510 AC610 AC710 Code D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 AC011 AC1 11 AC2 11 AC3 11 AC4 11 AC5 11 AC611 AC7 11 AC0 12 AC1 12 AC212 AC312 AC412 AC512 AC612 AC712 Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 AC013 AC1 13 AC2 13 AC3 13 AC4 13 AC5 13 AC613 AC7 13 DA0 1 DA1 1 DA21 DA31 DA41 DA51 X X Code D112 D113 D114 D115 D116 D117 D118 D119 0 1 X X 0 1 0 1 X: don't care Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DCRAM address DCRAM data DA01 to DA51 AC0 1 to AC71 (DA0 1 to DA51)+7 AC0 8 to AC78 (DA01 to DA51)+1 AC0 2 to AC72 (DA0 1 to DA51)+8 AC0 9 to AC79 (DA01 to DA51)+2 AC0 3 to AC73 (DA0 1 to DA51)+9 AC0 10 to AC710 (DA01 to DA51)+3 AC0 4 to AC74 (DA0 1 to DA51)+10 AC0 11 to AC711 (DA01 to DA51)+4 AC0 5 to AC75 (DA0 1 to DA51)+11 AC0 12 to AC712 (DA01 to DA51)+5 AC0 6 to AC76 (DA0 1 to DA51)+12 AC0 13 to AC713 (DA01 to DA51)+6 AC0 7 to AC77

No.A1417-20/54

ADRAM data write ... <Specifies the ADRAM address and stores data at that address> (Write data to ADRAM) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X RA0 RA1 RA2 RA3 X X X X IM1 IM2 X X 0 1 1 0 X: don’t care RA0 to RA3:ADRAM address RA0 RA1 RA2 RA3 LSB MSB ↑ ↑ Least significant bit Most significant bit AD1 to AD5: ADATA display data In addition to the 5×7 or 5×8 dot matrix display data (MDATA), this IC supports direct display of the five accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM. The figure below shows the correspondence between the data and the display. When ADn = 1(where n is an integer between 1 and 5) the segment corresponding to that data will be turned on. ADATA Corresponding output pin AD1 AD2 AD3 AD4 AD5 S5m+1 (m is an integer between 0 and 12) S5m+2 S5m+3 S5m+4 S5m+5 IM1, IM2: Sets the method of writing data to ADRAM IM1 IM2 ADRAM data write method 0 0 Normal ADRAM data write (Specifies t he ADRAM address and writes the ADRAM data.) 1 0 Nomal increment mode ADRAM data write (Increments the ADRAM address by +1 each time data is written to ADRAM.) 0 1 Super increment mode ADRAM data write (Writes 2 to 13 digits of ADRAM data in single operation.) S5m+1 S5m+5 (m is an integer between 0 and 12)

No.A1417-21/54 Notes: *17.

ADRAM data write method when IM1 = 0, IM2 = 0
ADRAM data write method when IM1 = 1, IM2 = 0 (Instructions other than the “ADRAM data write” instruction cannot be executed.)
ADRAM data write method when IM1 = 0, IM2 = 1 ti=13.5μs×( -1) (n=8m+16, m is an integer between 2 and 13 that is the number of characters written as ADRAM data.) For example When n= 32 bits (m=2): ti= 40.5μs (fosc=300kHz, fCK=300kHz) When n= 80 bits (m=8): ti=121.5μs (fosc=300kHz, fCK=300kHz) When n=120 bits (m=13): ti=189.0μs (fosc=300kHz, fCK=300kHz) Note that the instruction execution time of 27μs and ti values in μs apply when fosc=300kHz and fCK=300kHz, and that these execution times will differ when the CR oscillator frequency fosc and external clock frequency fCK differ. ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes Instruction execution time (27μs) (6) (6)(6) CCB address CCB address CCB address CCB address 24 bit 24 bit 24 bit (6) CE DI ADRAM 24 bit Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) ADRAM data write finishes ADRAM CE Instructions other than the “ADRAM data write” instruction cannot be executed. CCB address CCB address CCB address CCB address CCB address CCB address 24 bit 8 bit 8 bit 8 bit 8 bit 16 bit Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) Instruction execution time (27μs) ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes Instruction execution time (tiμs) Instruction execution time (tiμs) Instruction execution time (tiμs) (10) (10) CCB address CCB address n bit n bit (10) CE DI ADRAM n bit CCB address ADRAM data write finishes ADRAM data write finishes n

No.A1417-22/54 Data format at (6) (24 bits) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X RA0 RA1 RA2 RA3 X X X X 0 0 X X 0 1 1 0 X: don’t care Data format at (7) (24 bits) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X RA0 RA1 RA2 RA3 X X X X 1 0 X X 0 1 1 0 X: don’t care Data format at (8) (8 bits) Code D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X Data format at (9) (16 bits) Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X 0 0 X X 0 1 1 0 X: don’t care Data format at (10) (n bit) Code Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1m AD2 m AD3 m AD4 m AD5 m X X X RA0 1 RA11 RA21 RA31 X X X X 0 1 X X 0 1 1 0 X: don’t care Here, n=8m+16, z=104-8m (m is an integer between 2 and 13 that is the number of characters written as ADRAM data.) Correspondence between the ADRAM address and theADRAM data ADRAM address ADRAM data RA01 to RA31 AD1 1 to AD51 (RA01 to RA31)+1 AD1 2 to AD52 (RA01 to RA31)+2 AD1 3 to AD53 (RA01 to RA31)+(m-3) AD1 m-2 to AD5m-2 (RA01 to RA31)+(m-2) AD1 m-1 to AD5m-1 (RA01 to RA31)+(m-1) AD1 m to AD5m

No.A1417-23/54 Example 1: When n=32 bits (m=2: 2 characters ADRAM data write operation) Code D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 AD11 AD2 1 AD3 1 AD4 1 AD5 1 X X X AD12 AD2 2 AD33 AD44 AD55 XXX Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 RA0 1 RA11 RA2 1 RA3 1 X X X X 0 1 X X 0 1 1 0 X: don’t care Correspondence between the ADRAM address and the ADRAM data ADRAM address ADRAM data RA0 1 to RA3 1 AD1 1 to AD5 1 (RA0 1 to RA3 1)+1 AD1 2 to AD52 Example 2: When n=80 bits (m=8: 8 characters ADRAM data write operation) Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 AD11 AD2 1 AD3 1 AD4 1 AD5 1 X X X AD12 AD2 2 AD32 AD42 AD52 XXX Code D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 AD13 AD2 3 AD3 3 AD4 3 AD5 3 X X X AD14 AD2 4 AD34 AD44 AD54 XXX Code D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 AD15 AD2 5 AD3 5 AD4 5 AD5 5 X X X AD16 AD2 6 AD36 AD46 AD56 XX X Code D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 AD17 AD2 7 AD3 7 AD4 7 AD5 7 X X X AD18 AD2 8 AD38 AD48 AD58 XXX Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 RA0 1 RA11 RA2 1 RA3 1 X X X X 0 1 X X 0 1 1 0 X: don't care Correspondence between the ADRAM address and the ADRAM data ADRAM address ADRAM data RA01 to RA31 AD1 1 to AD51 (RA01 to RA31)+1 AD1 2 to AD52 (RA01 to RA31)+2 AD1 3 to AD53 (RA01 to RA31)+3 AD1 4 to AD54 (RA01 to RA31)+4 AD1 5 to AD55 (RA01 to RA31)+5 AD1 6 to AD56 (RA01 to RA31)+6 AD1 7 to AD57 (RA01 to RA31)+7 AD1 8 to AD58

No.A1417-24/54 Example 3: When n=120 bits (m=13: 13 characters ADRAM data write operation) Code D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 AD11 AD2 1 AD3 1 AD4 1 AD5 1 X X X AD12 AD2 2 AD32 AD42 AD52 XXX Code D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 AD13 AD2 3 AD3 3 AD4 3 AD5 3 X X X AD14 AD2 4 AD34 AD44 AD54 XXX Code D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 AD15 AD2 5 AD3 5 AD4 5 AD5 5 X X X AD16 AD2 6 AD36 AD46 AD56 XXX Code D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AD17 AD2 7 AD3 7 AD4 7 AD5 7 X X X AD18 AD2 8 AD38 AD48 AD58 XXX Code D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 AD19 AD2 9 AD3 9 AD4 9 AD5 9 X X X AD110 AD2 10 AD310 AD410 AD510 XXX Code D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 AD111 AD2 11 AD3 11 AD4 11 AD5 11 XX X AD112 AD2 12 AD312 AD412 AD512 XXX Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 AD113 AD2 13 AD3 13 AD4 13 AD5 13 XX X RA0 1 RA11 RA21 RA31 XXXX Code D112 D113 D114 D115 D116 D117 D118 D119 0 1 X X 0 1 1 0 X: don't care Correspondence between the ADRAM address and the ADRAM data ADRAM address ADRAM data ADRAM address ADRAM data RA01 to RA31 AD1 1 to AD51 (RA0 1 to RA31)+7 AD1 8 to AD58 (RA01 to RA31)+1 AD1 2 to AD52 (RA0 1 to RA31)+8 AD1 9 to AD59 (RA01 to RA31)+2 AD1 3 to AD53 (RA0 1 to RA351)+9 AD1 10 to AD510 (RA01 to RA31)+3 AD1 4 to AD54 (RA0 1 to RA31)+10 AD1 11 to AD511 (RA01 to RA31)+4 AD1 5 to AD55 (RA0 1 to RA31)+11 AD1 12 to AD512 (RA01 to RA31)+5 AD1 6 to AD56 (RA0 1 to RA31)+12 AD1 13 to AD513 (RA01 to RA31)+6 AD1 7 to AD57

No.A1417-25/54

CGRAM data write ... <Specifies the CGRAM address and stores data at that address> (Write data to CGRAM) Code D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16 Code D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 Code D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 X X X X X X X X Code D104 D105 D106 D107 D108 D 109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 X X X X 0 1 1 1 X: don’t care CA0 to CA7: CGRAM address CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 LSB MSB ↑ ↑ Least significant bit Mo st significant bit CD1 to CD40: CGRAM data (5×7 or 5×8 dot matrix display data) The bit CDn (where n is an integer between 1 and 40) corresponds to the 5×7 or 5×8 dot matrix display data. The figure below shows that correspondence. When CDn is 1 the dots which correspond to that data will be turned on. CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 Note: *18. CD1 to CD35: 5×7 dot matrix display data CD1 to CD40: 5×8 dot matrix display data

No.A1417-26/54

Set display contrast… <Sets the display contrast> (Set display contrast) Code D104 D105 D106 D107 D108 D 109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 CT0 CT1 CT2 CT3 X X X X CTC X X X 1 0 0 0 X: don’t care CT0 to CT3: Sets the display contrast (11 steps) CT0 CT1 CT2 CT3 LCD drive 4/4 bias voltage supply V LCD0 level 0 0 0 0 0.94V LCD=VLCD-(0.03VLCD×2) 1 0 0 0 0.91V LCD=VLCD-(0.03VLCD×3) 0 1 0 0 0.88V LCD=VLCD-(0.03VLCD×4) 1 1 0 0 0.85V LCD=VLCD-(0.03VLCD×5) 0 0 1 0 0.82V LCD=VLCD-(0.03VLCD×6) 1 0 1 0 0.79V LCD=VLCD-(0.03VLCD×7) 0 1 1 0 0.76V LCD=VLCD-(0.03VLCD×8) 1 1 1 0 0.73V LCD=VLCD-(0.03VLCD×9) 0 0 0 1 0.70V LCD=VLCD-(0.03VLCD×10) 1 0 0 1 0.67V LCD=VLCD-(0.03VLCD×11) 0 1 0 1 0.64V LCD=VLCD-(0.03VLCD×12) CTC: Sets the display contrast adjustment circuit state CTC Display contrast adjustment circuit state 0 The display contrast adjustment circuit is disabled, and the VLCD0 pin level is forced to the VLCD level. 1 The display contrast adjustment circuit operat es, and the display contrast is adjusted. Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the VLCD4 pin and modifying the VLCD4 pin voltage. However, the following conditions must be met: VLCD0-VLCD4≥ 4.5V, and 1.5V≥VLCD4 ≥ 0V.

No.A1417-27/54

Set key scan output port/general-purpose output port state ... <Sets the key scan output port and general-purpose output port states> (Key scan output port and General-purpose output port control) Code D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC10 PC11 PC20 PC21 PC30 PC31 Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 PC32 PF0 PF1 PF2 PF3 KC1 KC2 KC3 KC4 KC5 KC6 KC7 KP1 KP2 KP3 X X X X X 1 0 0 1 X: don’t care KP1 to KP3: Set the output pins KS1/P1, KS2/P2, and KS7/P3 as either key scan output ports or general-purpose output ports. Output pin KP1 KP2 KP3 KS1/P1 KS2/P2 KS7/P3 Max. Key Input Number General- purpose Output Port Number 0 0 0 KS1 KS2 KS7 35 0 1 0 0 P1 KS2 KS7 30 1 0 1 0 KS1 P2 KS7 30 1 0 0 1 KS1 KS2 P3 30 1 1 1 0 P1 P2 KS7 25 2 0 1 1 KS1 P2 P3 25 2 1 0 1 P1 KS2 P3 25 2 1 1 1 P1 P2 P3 20 3 *19) KSn(n=1,2,7): Key scan output port Pn(n=1 to 3): General-purpose output port KC1 to KC7: Sets the key scan output pin KS1 to KS7 state Output pin KS1 KS2 KS3 KS4 KS5 KS6 KS7 Key scan output state setting data KC1 KC2 KC3 KC4 KC5 KC6 KC7 If, for example, the output pins KS1/P1, KS2/P2, and KS7/P3 are set as key scan output ports, the output pins KS1 to KS3 will go high (VDD) and KS4 to KS7 go low (VSS) in the key scan standby state when KC1 to KC3 are set to 1 and KC4 to KC7 are set to 0. Note that key scan output signals are not output from output pins that are set to the low level. PC10, PC11: Sets the general-purpose output port P1 state PC20, PC21: Sets the general-purpose output port P2 state PC10 PC11 Output pin (P1) state PC20 PC21 Output pin (P2) state 0 0 “L”(V SS) 0 0 “L”(V SS) 1 0 “H”(V DD) 1 0 “H”(V DD) 0 1 PWM signal output 0 1 PWM signal output PC30 to PC32: Sets the general-purpose output port P3 state PC30 PC31 PC32 Output pin (P3) state 0 0 0 “L”(V SS) 1 0 0 “H”(V DD) 0 1 0 PWM signal output 1 1 0 Clock signal output (fosc/2, f CK/2) 0 0 1 Clock signal output (fosc/8, f CK/8)

No.A1417-28/54 PF0 to PF3: Set the frame frequency of the PWM output waveforms. (when general-purpose outout ports P1 to P3 are set to select the PWM signal generation function.) PF0 PF1 PF2 PF3 PWM Output Wave form Frame Frequency fp[Hz] 0 0 0 0 fosc/1536, f CK/1536 1 0 0 0 fosc/1408, f CK/1408 0 1 0 0 fosc/1280, f CK/1280 1 1 0 0 fosc/1152, f CK/1152 0 0 1 0 fosc/1024, f CK/1024 1 0 1 0 fosc/896, f CK/896 0 1 1 0 fosc/768, f CK/768 1 1 1 0 fosc/640, f CK/640 0 0 0 1 fosc/512, f CK/512 1 0 0 1 fosc/384, f CK/384 0 1 0 1 fosc/256, f CK/256 W10 to W15, W20 to W25, W30 to W35: Set the pulse width of the PWM output waveforms. (when general-purpose outout ports P1 to P3 are set to select the PWM signal generation function.) Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 PWM Signal Pn Pulse Width Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 PWM Signal Pn Pulse Width 0 0 0 0 0 0 ×Tp Note: *20. Wn0 to Wn5 (n=1 to 3): PWM data for the PWM output waveforms at general-purpose output ports Pn (n=1 to 3). T p= 1 fp

No.A1417-29/54 Serial Data Output (1) When CL is stopped at the low level (2) When CL is stopped at the high level

B0 to B3, A0 to A3: CCB address 43H
KD1 to KD35: Key data
SA: Sleep acknowledge data Note: *21. When key data read operation is executed with DO set high (no key data read request present), the key data (KD1 to KD35) and sleep acknowledge data (SA) are invalid. Output Data (1) KD1 to KD35: Key data When a key matrix of up to 35 keys is formed from the KS1 to KS7 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. KI1 KI2 KI3 KI4 KI5 KS1/P1 KD1 KD2 KD3 KD4 KD5 KS2/P1 KD6 KD7 KD8 KD9 KD10 KS3 KD11 KD12 KD13 KD14 KD15 KS4 KD16 KD17 KD18 KD19 KD20 KS5 KD21 KD22 KD23 KD24 KD25 KS6 KD26 KD27 KD28 KD29 KD30 KS7/P3 KD31 KD32 KD33 KD34 KD35 KD1 to KD10 are all set to 0 when the output pins KS1/P1 and KS2/P2 are set as general-purpose output ports with the "set key scan output port/general-purpose output port state" instruction and a key matrix of maximum 25 keys is formed from the output pins KS3 to KS6 and KS7/P3 and the input pins KI1 to KI5. (2) SA: Sleep acknowledge data This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in Sleep mode and 0 in normal mode. X: don’t care Output data CE A3A2 A1 A0 B3B2 B1 B0 KD2KD1XX KD35 01 0 0 0 0 1 1 DO DI CL SA X X KD34 CE A3A2 A1 A0 B3B2 B1 B0 KD3KD2KD1XX X X X SA 01 0 0 00 1 1 DO DI CL KD35 X: don’t care Output data

No.A1417-30/54 Key Scan Operation Functions (1) Key scan timing The key scan period is 2296T(s). To reliably determine the on/off state of the keys, the LC75812PT scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 4800T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it scans the keys again. Thus the LC75812PT cannot detect a key press shorter than 4800T(s). Note: *22. Not that the high/low states of these pins are determined by the "set key scan output port/general-purpose output port state" instruction, and that key scan output signals are not output from pins that are set to low. (2) In normal mode

The pins KS1 to KS7 are set to high or low with the "set key scan output port/general-purpose output port state" instruction.
If a key on one of the lines corresponding to a KS1 to KS7 pin which is set high is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 4800T(s) (Where T=1/fosc, T=1/fCK) the LC75812PT outputs a key data read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75812PT performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1kΩ and 10kΩ). Key scan T= T= Key data read request Key data read DO DI Serial data transferKey address (43H) Key addressSerial data transfer Serial data transfer CE Key input 2 Key input 1 4800T[s] 4800T[s] 4800T[s] fosc Key address Key data read request Key data read request Key data read Key data read fCK Key on 4592T[s] *22 *22 *22 *22 *22 *22 *22 *22 *22 *22 *22 KS4 KS5 KS6 KS3 KS2 *22 KS1 *22 *22 7 7KS7 T= 1 fosc T= fCK

No.A1417-31/54 (3) In sleep mode

The pins KS1 to KS7 are set to high or low with the "set key scan output port/general-purpose output port state" instruction.
If a key on one of the lines corresponding to a KS1 to KS7 pin which is set high is pressed in the RC oscillator operating mode, the oscillator on the OSC pin is started (the IC starts receiving the external clock in external clock operating mode) and a key scan is performed . Keys are scanned until all keys released. Multiple key presses are recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 4800T(s) (Where T=1/fosc, T=1/fCK) the LC75812PT outputs a key data read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75812PT performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1kΩ and 10kΩ).
Sleep mode key scan example Example: When a "display on/off control (SP=1)" instruction and a "set key scan output port/general-purpose output port state (KP1 to KP3=0, KC1 to KC6= 0, KC7=1)" instruction are executed. (i.e. sleep mode with only KS7 high.) Note: *23. These diodes are required to reliably recognize multiple key presses on the KS7 line when sleep mode state with only KS7 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS7 key scan output signal when keys on the KS1 to KS6 lines are pressed at the same time. Multiple Key Presses Although the LC75812PT is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS7 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. Key data read request Key data read DO DI Key address (43H) Serial data transfer CE Key scan Key input (KS7 line) 4800T[s] 4800T[s] T= 1 fosc Serial data transfer Serial data transfer Key address Key data read request Key data read T= 1 fCK When any one of these keys is pressed in RC oscillator operating mode, the oscillator on the OSC pin is started (the IC starts receiving the external clock in external clock operating mode) and the keys are scanned. KI1 KI2 KI3 KI4 KI5 *23 “L” KS4 “H” KS7 “L” KS3 “L” KS2 “L” KS5 “L” KS6 “L” KS1

No.A1417-32/54 1/8 Duty, 1/4 Bias Drive Technique When a "set display technique" instruction with FC0 = 0, FC1 = 0 are executed: f8 = , f8 = When a "set display technique" instruction with FC0 = 1, FC1 = 0 are executed: f8 = , f8 = When a "set display technique" instruction with FC0 = 0, FC1 =1 are executed: f8 = , f8 = fosc 3072 fosc 1536 fCK 3072 fCK 1536 VLCD3 VLCD4 VLCD4 VLCD2 VLCD1 VLCD0 VLCD4 VLCD3 VLCD3 VLCD2 VLCD2 VLCD1 VLCD1 VLCD0 VLCD0 COM8 COM2 COM1 LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when only LCD segments corresponding to COM1 are turned on VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 VLCD4 VLCD3 VLCD2 VLCD0 VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 f8 T8= VLCD1 LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned off LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned on fosc 768 fCK 768

No.A1417-33/54 1/9 Duty, 1/4 Bias Drive Technique VLCD3 VLCD4 VLCD4 VLCD2 VLCD1 VLCD0 VLCD4 VLCD3 VLCD3 VLCD2 VLCD2 VLCD1 VLCD1 VLCD0 VLCD0 COM9 COM2 COM1 VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 VLCD4 VLCD3 VLCD2 VLCD1 VLCD0 f9 T9= LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned off LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned on When a "set display technique" instruction with FC0 = 0, FC1 = 0 are executed: f9 = , f9 = When a "set display technique" instruction with FC0 = 1, FC1 = 0 are executed: f9 = , f9 = When a "set display technique" instruction with FC0 = 0, FC1 =1 are executed: f9 = , f9 = fosc 3456 fosc 1728 fCK 3456 fCK 1728 fosc 864 fCK 864

No.A1417-34/54 PWM Output Waveform Tp= "Set key scan output port/general-purpose output port state" Instruction Data W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PWM Output Waveform of General-purpose Output Ports P1 to 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 2 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 3 "Set key scan output port/general-purpose output port state" Instruction Data PF0 PF1 PF2 PF3 PWM Output Waveform Frame Frequency fp[Hz] 0 0 0 0 fosc/1536, fCK/1536 1 0 0 0 fosc/1408, fCK/1408 0 1 0 0 fosc/1280, fCK/1280 1 1 0 0 fosc/1152, fCK/1152 0 0 1 0 fosc/1024, fCK/1024 1 0 1 0 fosc/896, fCK/896 0 1 1 0 fosc/768, fCK/768 1 1 1 0 fosc/640, fCK/640 0 0 0 1 fosc/512, fCK/512 1 0 0 1 fosc/384, fCK/384 0 1 0 1 fosc/256, fCK/256 (32/64) × Tp (56/64) × Tp VDD VSS (48/64) × Tp VSS VDD (40/64) × Tp VSS VDD (32/64) × Tp VDD VSS (32/64) × Tp VSS VDD (32/64) × Tp VSS VDD VDD VSS (16/64) × Tp VSS VDD (24/64) × Tp VSS VDD (16/64) × Tp (24/64) × Tp (32/64) × Tp (32/64) × Tp Tp Tp (56/64) × Tp (48/64) × Tp (40/64) × Tp fp

No.A1417-35/54 Clock Signal Output Waveform "Set Key Scan Output Port/ General-purpose Port State" Instruction Data PC30 PC31 PC32 General-purpose port P3 clock signal frequency fc (=1/Tc) [Hz] 1 1 0 Clock signal output (fosc/2, f CK/2) 0 0 1 Clock signal output (fosc/8, f CK/8) Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,which is 2.2V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1ms. (See Figure 5.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 5.)

Power on: Logic block power supply(VDD) on → LCD driver block power supply (VLCD) on
Power off: LCD driver block power supply(VLCD) off → Logic block power supply (VDD) off When 5V signal is applied to the CE, CL, DI, and INH pins which are to be connected to the controller and if the logic block power supply (VDD) is off, set the input voltage at the CE, CL, DI, and INH pins to 0V and apply the 5V signal to these pins after turning on the logic block power supply (VDD). System Reset 1. Reset function The LC75812PT performs a system reset with the VDET. When a system reset is applied, the display is turned off, key scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low level (VSS). These states that are created as a result of the system reset can be cleared by executing the instruction described below. (See Figure 5.)
Clearing the display off state Display operation can be enabled by executing a “display on/off control” instruction. However, since the contents of the DCRAM, ADRAM, and CGRAM are undefined, applications must set the contents of these memories before turning on display with the “display on/off control” instruction. That is, applications must execute the following instructions.
Set display technique (The "set display technique" instruction must be executed first.)
DCRAM data write
ADRAM data write (If the ADRAM is used.)
CGRAM data write (If the CGRAM is used.)
Set AC address
Set display contrast (If the display contrast adjustment circuit is used.) After executing the above instructions, applications must turn on the display with a “display on/off control” instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off control” instruction or the INH pin. Tc Tc/2 1 fc Tc=

No.A1417-36/54

Clearing the key scan disable and key data reset states By executing the following instructions not only create a state in which key scanning can be performed, but also clear the key data reset.
Set display technique (The "set display technique" instruction must be executed first.)
Set key scan output port/general-purpose output port state
Clearing the general-purpose output ports locked at the low level (VSS) state By executing the following instructions clear the general-purpose output ports locked at the low level (VSS) state and set the states of the general-purpose output ports.
Set display technique (The "set display technique" instruction must be executed first.)
Set key scan output port/general-purpose output port state [Figure 5]
t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time)
Initial state settings Set display technique (The "set display technique" instruction must be executed first.) DCRAM data write ADRAM data write (If the ADRAM is used.) CGRAM data write (If the CGRAM is used.) Set AC address Set display contrast (If the display contrast adjustment circuit is used.) “Set display technique” and “Set key scan output port/ general-purpose output port state” instruction execution “Display on/off control” instruction execution (Turning the display on) ”Display on/off control“ instruction execution (Turning the display off) VDETVDET t3 t4 t1 t2 Key scan Display state Instruction execution VDD VLCD Initial state settings Display offDisplay on Can be set to such states as high (VDD), or low (VSS) level Fixed at the low level (VSS) Display off Execution enabled Disabled General-purpose output ports

No.A1417-37/54 2. Block states during a system reset (1) CLOCK GENERATOR,TIMING GENERATOR When a reset is applied, these circuits are forcibly initialized internally. Then, when the "set display technique" instruction is executed, oscillation of the OSC pin starts in RC oscillator operating mode (the IC starts receiving the external clock in external clock operating mode), execution of the instruction is enabled. (2) INSTRUCTION REGISTER, INSTRUCTION DECODER When a reset is applied, these circuits are forcibly initialized internally. Then, when instruction execution starts, the IC operates according to those instructions. (3) ADDRESS REGISTER, ADDRESS COUNTER When a reset is applied, these circuits are forcibly initialized internally. Then, the DCRAM and the ADRAM addresses are set when “Set AC address” instruction is executed. (4) DCRAM, ADRAM, CGRAM Since the contents of the DCRAM, ADRAM, and CGRAM become undefined during a reset, applications must execute “DCRAM data write”, “ADRAM data write (If the ADRAM is used.)”, and “CGRAM data write (If the CGRAM is used.)” instructions before executing a “display on/off control” instruction. (5) CGROM Character patterns are stored in this ROM. (6) LATCH Although the value of the data in the latch is undefined during a reset, the ADRAM, CGROM, and CGRAM data is stored by executing a “display on/off control” instruction. (7) COMMON DRIVER, SEGMENT DRIVER These circuits are forced to the display off state when a reset is applied. (8) CONTRAST ADJUSTER Display contrast adjustment circuit operation is disabled when a reset is applied. After that, the display contrast can be set by executing a “set display contrast” instruction. (9) KEY SCAN, KEY BUFFER When a reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. Also, the key data is all set to 0. After that, key scanning can be performed by executing a "set key scan output port/general-purpose output port state" instruction. (10) GENERAL PURPOSE PORT When a reset is applied, the general-purpose output port state is locked at the low level (VSS). (11) CCB INTERFACE, SHIFT REGISTER These circuits go to the serial data input wait state.

No.A1417-38/54 (3) Output pin states during the reset period Output pin State during reset S1 to S64 S65/COM9 COM1 to COM8 KS1/P1, KS2/P2 KS3 to KS6 KS7/P3 OSC DO L (VLCD4) L (VLCD4) *24 L (VLCD4) L (VSS) *25 L (VSS) L (VSS) *25 Z (high-impedance) *26 H *27 *24 This output pin is forcibly set to the segment output function and held low (VLCD4). If the "set display technique" instruction is executed, however, either segment output or common output is selected according to the instruction. *25 This output pin is forcibly set to general-purpose output port and held low (VSS). If the “set display technique” and the "set key scan output port/general-purpose output port state" instructions are executed, however, either key scan output port or general-purpose output port is selected according to the instructions. *26 This I/O pin is forcibly set to the high-impedance state. *27 Since this output pin is an open-drain output, a pull-up resistor (between 1kΩ and 10kΩ) is required. This pin is held at the high level even if a key data read operation is performed before executing the "set display technique" or "set key scan output port/general-purpose output port state" instruction. Blocks that are reset S65/COM9 S64 VLCD2 ADRAM bits CGRAM 5×8×16 bits VDET CLOCK GENERATOR CONTRAST ADJUSTER TIMING GENERATOR ADDRESS REGISTER INSTRUCTION REGISTER COMMON DRIVER INSTRUCTION DECODER ADDRESS COUNTER DCRAM 52×8 bits CGROM 5×8×240 bits SHIFT REGISTER LATCH SEGMENT DRIVER OSC INH DO DI P1/KS1 P2/KS2 KS3 KS4 KS6 CE KI1 KI2 KI3 KI4 KI5 CL S63 COM8 COM1 KEY BUFFER CCB INTERFACE KEY SCAN VDD VLCD4 VLCD3 VLCD1 VLCD VLCD0 VSS TEST GENERAL PURPOSE PORT P3/KS7 KS5

No.A1417-39/54 OSC Pin Peripheral Circuit (1) RC oscillator operating mode (when the "set display technique (OC=0)" instruction is executed) When RC oscillator operating mode is selected, an external resistor Rosc and an external capacitor Cosc must be connected between the OSC pin and GND. (2) External clock operating mode (when the "set display technique (OC=1)" instruction is executed) When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and external clock output pin (external oscillator). Determine the value of the resistance according to the maximum allowable current value at the external clock output pin. Also make sure that the waveform of the external clock is not heavily distorted. Note: *28. Allowable current value at external clock output pin > Pins P1 to P3 peripheral circuit It is recommended that the following circuit be used when adjusting the brightness of the LED backlight in PWM mode using the general-purpose output ports P1 to P3 (when PWM signal output function is selected with the general-purpose output ports P1 to P3 under the "set key scan output port/general-purpose output port state" instruction): Note when applying a 5V signal to the CE, CL, DI, and INH pins When applying a 5V signal to the CE, CL, DI, and INH pins which are to be connected to the controller, set the input voltage to the CE, CL, DI, and INH pins to 0V if the logic block power supply (VDD) is off, and apply the 5V signal to those pins after turning on the logic block power supply (VDD). OSC CoscRosc OSCExternal clock output pin Rg External oscillator VDD Rg LED VCC P1 to P3

No.A1417-40/54 Sample Application Circuit 1 1/8 duty, 1/4 bias drive technique (for use with normal panels) Note *29. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the VDET. *30. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *31. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external oscillator). (See the “OSC Pin Peripheral Circuit” section.) *32. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *33. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *34 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block power supply (VDD) is off and apply the 5V signal to those pins after turning on the logic block power supply (VDD). To the controller power supply To the controller From the controller LCD panel General-purpose output ports used with the backlight controller or other circuit Key matrix (up to 35 keys) COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 C C C C≥0.047μF +8V *29 +3.3V INH *32 CE CL *33 DO DI VLCD4 *30 VLCD3 VLCD2 VLCD1 OPEN VLCD VLCD0 VSS TEST VDD COM9/S65 S64 S63 S62 S61 S10 OSC *31 *34 P K S P K S K S K S K S K S K I K I K I K I K I P K S

No.A1417-41/54 Sample Application Circuit 2 1/8 duty, 1/4 bias drive technique (for use with large panels) Note *29. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the VDET. *30. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *31. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external oscillator). (See the “OSC Pin Peripheral Circuit” section.) *32. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *33. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *34 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block power supply (VDD) is off and apply the 5V signal to those pins after turning on the logic block power supply (VDD). COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 R R R R C C C C≥0.047 μF 10kΩ≥R≥2.2kΩ +8V *29 +3.3V CE CL *33 DO DI VLCD4 *30 VLCD3 VLCD2 VLCD1 VLCD VLCD0 VSS TEST VDD COM9/S65 S64 S63 S62 S61 S10 OSC *31 *34 P K S P K S K S K S K S K S K I K I K I K I K I P K S INH *32 To the controller power supply To the controller From the controller LCD panel General-purpose output ports used with the backlight controller or other circuit Key matrix (up to 35 keys)

No.A1417-42/54 Sample Application Circuit 3 1/9 duty, 1/4 bias drive technique (for use with normal panels) Note *29. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the VDET. *30. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *31. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external oscillator). (See the “OSC Pin Peripheral Circuit” section.) *32. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *33. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *34 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block power supply (VDD) is off and apply the 5V signal to those pins after turning on the logic block power supply (VDD). S65/COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 C C C C≥0.047 μF +8V *29 +3.3V CE CL *33 DO DI VLCD4 *30 VLCD3 VLCD2 VLCD1 VLCD VLCD0 VSS TEST VDD S64 S63 S62 S61 S10 OSC *31 *34 P K S P K S K S K S K S K S K I K I K I K I K I P K S INH *32 OPEN To the controller power supply To the controller From the controller LCD panel General-purpose output ports used with the backlight controller or other circuit Key matrix (up to 35 keys)

No.A1417-43/54 Sample Application Circuit 4 1/9 duty, 1/4 bias drive technique (for use with large panels) Note *29. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the VDET. *30. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *31. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22kΩ) between the OSC pin and the external clock output pin (external oscillator). (See the “OSC Pin Peripheral Circuit” section.) *32. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *33. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1kΩ and 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *34 When applying a 5V signal to the CE, CL, DI, and INH pins, set the input voltage to 0V if the logic block power supply (VDD) is off and apply the 5V signal to those pins after turning on the logic block power supply (VDD). S65/COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 R R R R C C C C≥0.047 μF 10kΩ≥R≥2.2kΩ +8V *29 +3.3V CE CL *33 DO DI VLCD4 *30 VLCD3 VLCD2 VLCD1 VLCD VLCD0 VSS TEST VDD S64 S63 S62 S61 S10 OSC *31 *34 P K S P K S K S K S K S K S K I K I K I K I K I P K S INH *32 To the controller power supply To the controller From the controller LCD panel General-purpose output ports used with the backlight controller or other circuit Key matrix (up to 35 keys)

No.A1417-44/54 Sample Correspondence between Instructions and the Display (When the LC75812PT-8565 is used) LSB Instruction (hexadecimal) MSB No. D96 to D99 D100 to D103 D104 to D107 D108 to D111 D112 to D115 D116 to D119 Display Operation Power application (Initialization with the VDET) Initializes the IC. The display is in the off state. Set display technique 0 8 Sets to 1/8 duty 1/4 bias display drive technique DCRAM data write (normal increment mode) 0 2 0 0 1 A Writes the display data “ ” to DCRAM address 00H DCRAM data write (normal increment mode) 3 5 Writes the display data “S” to DCRAM address 01H DCRAM data write (normal increment mode) 1 4 Writes the display data “A” to DCRAM address 02H DCRAM data write (normal increment mode) E 4 Writes the display data “N” to DCRAM address 03H DCRAM data write (normal increment mode) 9 5 Writes the display data “Y” to DCRAM address 04H DCRAM data write (normal increment mode) F 4 Writes the display data “O” to DCRAM address 05H DCRAM data write (normal increment mode) 0 2 Writes the display data “ ” to DCRAM address 06H DCRAM data write (normal increment mode) C 4 Writes the display data “L” to DCRAM address 07H DCRAM data write (normal increment mode) 3 5 Writes the display data “S” to DCRAM address 08H DCRAM data write (normal increment mode) 9 4 Writes the display data “I” to DCRAM address 09H DCRAM data write (normal increment mode) 0 2 Writes the display data “ ” to DCRAM address 0AH DCRAM data write (normal increment mode) C 4 Writes the display data “L” to DCRAM address 0BH DCRAM data write (normal increment mode) 3 4 Writes the display data “C” to DCRAM address 0CH DCRAM data write (normal increment mode) 7 3 Writes the display data “7” to DCRAM address 0DH DCRAM data write (normal increment mode) 5 3 Writes the display data “5” to DCRAM address 0EH DCRAM data write (normal increment mode) 8 3 Writes the display data “8” to DCRAM address 0FH DCRAM data write (normal increment mode) 1 3 Writes the display data “1” to DCRAM address 10H DCRAM data write (normal increment mode) 2 3 Writes the display data “2” to DCRAM address 11H DCRAM data write (normal increment mode) 0 2 0 A Writes the display data “ ” to DCRAM address 12H Continued on next page.

No.A1417-45/54 Continued from preceding page. LSB Instruction (hexadecimal) MSB No. D96 to D99 D100 to D103 D104 to D107 D108 to D111 D112 to D115 D116 to D119 Display Operation Set AC address 0 0 0 2 Loads the DCRAM address 00H and the ADRAM address 0H into AC Display on/off control F F F 1 1 4 Turns on the LCD for all digits (13 digits) in MDATA Display shift 1 C Shifts the display (MDATA only) to the left Display shift 1 C Shifts the display (MDATA only) to the left Display shift 1 C Shifts the display (MDATA only) to the left Display shift 1 C Shifts the display (MDATA only) to the left Display shift 1 C Shifts the display (MDATA only) to the left Display shift 1 C Shifts the display (MDATA only) to the left Display on/off control 0 0 0 0 8 4 Set to sleep mode, turns off the LCD for all digits Display on/off control F F F 1 1 4 Turns on the LCD for all digits (13 digits) in MDATA Set AC address 0 0 0 2 Loads the DCRAM address 00H and the ADRAM address 0H into AC *35) The sample correspondence between the instructions and the display assumes the use of 13 digits×1 row 5×7 dot matrix LCD. Neither CGRAM nor ADRAM are used. S A N YO L S I L C SANYO LSI LC7 ANYO LSI LC75 NYO LSI LC758 YO LSI LC7581 O LSI LC75812 LSI LC75812 LSI LC75812 SANYO LSI LC

No.A1417-46/54 *36) Given below are the data formats of the "DCRAM data write" instructions (No. 3 to No. 21) for the sample correspondence between the instructions and the display executed in the super increment mode. In the super increment mode processing example shown below, 19 characters of DCRAM data is divided and written into DCRAM in two operations. Instruction (HEX) LSB MSBNo. D0 to D4 to D8 to D11 D12 to D15 D16 to D19 D20 to D23 D24 to D27 D28 to D31 D32 to D35 D36 to D39 D40 to D43 D44 to D47 DCRAM data write (Super increment mode) 3 to 15 0 2 3 5 1 4 E 4 9 5 F 4 DCRAM data write (Super increment mode) 16 to 21 Instruction (HEX) LSB MSBNo. D48 to D51 D52 to D55 D56 to D59 D60 to D63 D64 to D67 D68 to D71 D72 to D75 D76 to D79 D80 to D83 D84 to D87 D88 to D91 D92 to D95 DCRAM data write (Super increment mode) 3 to 15 0 2 C 4 3 5 9 4 0 2 C 4 DCRAM data write (Super increment mode) 16 to 21 7 3 5 3 8 3 1 3 2 3 Instruction (HEX) LSB MSBNo. D96 to D99 D100 to D103 D104 to D107 D108 to D111 D112 to D115 D116 to D119 Operation DCRAM data write (Super increment mode) 3 to 15 3 4 0 0 2 A are written sequentially to DCRAM addresses 00H to 0CH. DCRAM data write (Super increment mode) 16 to 21 0 2 D 0 2 A Display data “7” “5” “8” “1” “2” “ ” are written sequentially to DCRAM addresses 0DH to 12H.

No.A1417-47/54 Notes on the controller key data read techniques 1. Timer based key data acquisition

Flowchart
Timing chart t5: Key scan execution time when the key data agreed for two key scans. (4800T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600T(s)) t7: Key address (43H) transfer time t8: Key data read time
Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 When key data read operation is executed with DO set high (no key data read request present), the key data (KD1 to KD35) and sleep acknowledge data (SA) are invalid. Key data read processing YES NO DO=”L” CE=”L” Controller determination (Key on) Controller determination (Key on) Controller determination (Key off) Controller determination (Key on) Controller Determination (Key off) Key data read request Key data read DO DI CE Key onKey on Key address Key scan Key input t9 t9t9t9 t8 t8 t7 t7 fosc T= 1 fCKT=

No.A1417-48/54 2. Interrupt based key data acquisition

Flowchart
Timing chart t5: Key scan execution time when the key data agreed for two key scans. (4800T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600T(s)) t7: Key address (43H) transfer time t8: Key data read time
Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t10 has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must satisfy the following condition. t10 > t6 When key data read operation is executed with DO set high (no key data read request present), the key data (KD1 to KD35) and sleep acknowledge data (SA) are invalid. Key data read processing YES YES NO DO=”L” CE=”L” Wait for at least t10 Key OFF CE=”L” NO DO=”H” Controller determination (Key off) Key onKey on Key scan Controller determination (Key on) Controller determination (Key off) Controller determination (Key on) Controller determination (Key on) Controller determination (Key on) Key data read request Key data read DO DI CE Key address Key input t10t10 t10 t10 t5 t6 t8 t8 t7 t7 fosc T= 1 fCK T=

No.A1417-49/54 About Data Communication Method with The Controller 1. About data communication method of 4 line type CCB format The 4 line type CCB format is the data communication method of before. The LC75812PT must connect to the controller as followings. 2. About data communication method of 3 line type CCB format The 3 line type CCB format is the data communication method that made a common use of the data input DI in the data output DO. The LC75812PT must connect to the controller as followings. In this case, Applications must transfer the data communication start command before the serial data input (CCB address “42H”, display data and control data transfer) or serial data output (CCB address “43H” transfer, key data read) to avoid the collision of the data input signal DI and the data output signal DO. Then applications must transfer the data communication stop command when the controller wants to detect the key data read request signal (a low level on DO) during a movement stop of the serial data input and the serial data output. <1> Data communication start command (1) When CL is stoped at the low level (2 ) When CL is stoped at the high level <2> Data communication stop command (1) When CL is stoped at the low level (2 ) When CL is stoped at the high level Note: *37. Connect the pull-up resistor Rup. Select a resistance (between 1 to 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *38. The (INT) pin is an input port for the key data read request signal (a low level on DO) detection. DO DI CL CE DI DO CL CE Rup LC75812PT Controller (INT)*38 *37 Note: *37. Connect the pull-up resistor Rup. Select a resistance (between 1 to 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *38. The (INT) pin is an input port for the key data read request signal (a low level on DO) detection. DO DI CL CE DIO CL CE Rup LC75812PT Controller (INT) *37 *38 0 0 0 0 1 CCB address “00H” DI/DO CL CE 00 0 0 0 0 1 1 1 1 0 Command data 0 0 001DI/DO CL CE 0 000 001 1 1 1 0 CCB address “00H” Command data 1 1 0 0 1DI/DO CL CE 00 0 0 0 0 1 1 0 0 0 CCB address “00H” Command data 1 1 001DI/DO CL CE 0 000 001 1 0 0 0 CCB address “00H” Command data

No.A1417-50/54 Data Communication Flowchart of 4 Line Type or 3 Line Type CCB Format 1. Flowchart of the initial setting when power is turned on. 2. Flowchart of the serial data input 3. Flowchart of the serial data output Data communication start command transfer Serial data output (Key data and sleep acknowledge data read) The controller acknowledges the key data read request (When the CE is low, the DO is low) YES NO Note: *40. In the case of the 4 line type CCB format, the transfer of data communication start command is unnecessary, and, in the case of the 3 line type CCB format, the transfer is necessary. *41. Because the serial data output has the role of the data communication stop command, it is not necessary to transfer the data communication stop command some other time. *40 *41 Data communication start command transfer YES Serial data input (Execute instructions) Data communication stop command transfer The controller wants to detect the key data read request signal (a low level on DO). NO *39 *39 Note: *39. In the case of the 4 line type CCB format, the transfers of data communication start command and data communication stop command are unnecessary, and, in the case of the 3 line type CCB format, these transfers are necessary. Power on (Applications must observe that the power supply VDD rise time is at least 1ms.) Serial data input (Execute instructions) Power supply stability (Applications must wait till the level of the power supply is stable) System reset clear (Display on, Key scanning is enabled, General-purpose output port state setting are enabled) Note: The flowchart for power-on time initialization is the same for the 4- and 3-wire CCB formats. See "Power Supply Sequence" and "System Reset."

No.A1417-51/54 Timing Chart of 4 Line Type and 3 Line Type CCB Format 1. Timing chart of 4 line type CCB format <Example 1> <Example 2> <Example 3> Note: *42. When the key data agrees for two key scans, the key scan execution time is 4800T[s]. And, when the key data does not agree for two key scans and the key scan is executed again, the key scan execution time is 9600T[s]. DI CE Key on Key off Key scan Key input Serial data input (Execute instructions) Serial data output (Key data read) Key data read request Key data read request Key scan execution *42 DO CCB address (42H) CCB address (42H) CCB address (42H) CCB address (43H) Key scan execution *42 DI CE Key on Key scan Key input Serial data input (Execute instructions) Serial data output (Key data read) Key data read request Key data read request Key on Key off Key off DO Serial data output (Key data read) Key scan execution *42 Key scan execution *42 CCB address (42H) CCB address (42H) CCB address (42H) CCB address (43H) CCB address (43H) DI CE Key on Key scan Key input Serial data input (Execute instructions) Serial data output (Key data read) Key data read request Key data read request Key off Serial data output (Key data read) Key off DO Key scan execution *42 Key scan execution *42 CCB address (42H) CCB address (42H) CCB address (42H) CCB address (43H) CCB address (43H) fosc T= fCKT= 1

No.A1417-52/54 2. Timing chart of 3 line type CCB format <Example 1> <Example 2> <Example 3> Note: *42. When the key data agrees for two key scans, the key scan execution time is 4800T[s]. And, when the key data does not agree for two key scans and the key scan is executed again, the key scan execution time is 9600T[s]. DI/DO CE Key on Key off Key scan Key input Data communication start command Serial data input (Execute instructions) Data communication stop command Data communication start command Serial data output (Key data read) Key data read request Key data read request CCB address (42H) Key scan execution *42 Key scan execution *42 CCB address (42H) CCB address (42H) CCB address (43H) DI/DO CE Key on Key scan Key input Data communication start command Serial data input (Execute instructions) Data communication stop command Data communication start command Serial data output (Key data read) Key data read request Key data read request Key on Key off Key off Data communication start command Serial data output (Key data read) Key scan execution *42 Key scan execution *42 CCB address (42H) CCB address (42H) CCB address (42H) CCB address (43H) CCB address (43H) DI/DO CE Key on Key scan Key input Data communication start command Serial data input (Execute instructions) Serial data output (Key data read) Key data read request Key data read request Key off Serial data output (Key data read) Key off Key scan execution *42 Key scan execution *42 CCB address (42H) CCB address (42H) CCB address (43H) CCB address (43H) CCB address (42H) Data communication start command fosc T= fCKT= 1

No.A1417-53/54 LC75812PT-8565 Character Font (Standard) ä â ê ë î ï ô ö û ü ñ ç à á é è í ì ó ò ú ù Ñ Ç s S À Á É È Í Ì Ó Ò Ú Ù Ã Õ Å a n e Ä Â Ê Ë Î Ï Ô Ö Û Ü ã õ å o n G I IJ g i i j p q r s t u v w x y z a b c d e f g h i j k l m n o P Q R S T U V W X Y Z 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 A B C D E F G H I J K L M N O CG RAM(1) (16) (15) (14) (13) (12) (11) (10) (9) (8) (7) (6) (5) (4) (3) (2) 0 0 0 1 0 0 0 0 LSB 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 MSB 0 0 0 0 Upper 4BITLower 4BIT

No.A1417-54/54 SANYO Semiconductor Co.,Ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. Information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. Any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. When designing equip ment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. This catalog provides information as of March, 2010. Specifications and information herein are subject to change without notice. PS

Summary

1/8, 1/9 Duty Dot Matrix LCD Display Controllers/Drivers with Key Input Function

Description