LC7537

LC7537N SANYO | Alldatasheet

Document overview

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Technical content

Features

• Enables controlling the below-listed functions with 3- line serial data, including CE, DI, and CLK. Also, due to 0 V to 5 V swing of the serial data input voltage, permits the use of a general purpose microcomputer. Volume : Separately controls the Lch and Rch volume levels across 81 positions over the 0 dB to –79 dB (in 1 dB steps) range and –∞ , and consequently also serves balance control purposes. Loudness : By virtue of a center tap provided at the –20 dB position of the volume controlling ladder resistors, permits loudness to be controlled with externally connected CR components. Fader : By varying only the rear or front output level across 16 positions, provides fader functions (in 2 dB steps over the 0 dB to –20 dB range, and 5 dB steps over the –20 dB to –45 dB range, and at –∞ , for a total of 16 positions). Bass/Treble :With CR components externally connected, forms an NF type tone control circuit (Baxandall type) to exercise control across 15 positions over both the bass and treble functions in 2 dB steps.
• By virtue of its CMOS structure, the LSI operates under a broad power supply voltage range from +4.5 V to +15 V, permitting the use of either a single or a dual ± power supply, whichever is preferred. Package Dimensions SANYO: DIP42S [LC7573N] unit : mm 3025B-DIP42S SANYO: QIP48E [LC7537NE] SANYO: QIP48A [LC7537AN] unit : mm 3156-QFP48E unit : mm 3052A-QFP48A

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V, VDD = ‡ V CC > VSS ‡ V EE No. 2169-2/11 LC7537N, 7537AN, 7537NE Pin Assignments Equivalent Circuit Block Diagram Specifications Note:1. A1000 pF or larger capacitor should be added on between each individual power supply terminal and VSS . 2. When the microcomputer side control signals rise faster than VDD for the LC7537, a 2 kΩ or higher resistor should be inserted midway on each of the DI, CLK, and CE lines. 3.When mounting the QIP package on the board, do not dip the entire package in solder. Only the LC7537NE may be dipped directly in solder during mounting. Item Symbol Condition Rating Unit Maximum supply voltage VDD – VEE max VDD , VEE : VEE ‡ –8 V 16 V VCC max VCC : VDD ‡ VCC VSS – 0.3 to VSS + 7 V Input supply voltage VI1 DI, CLK, CE VSS – 0.3 to VDD + 0.3 V VI2 INIT VSS – 0.3 to VDD + 0.3 V Allowable power dissipation Pd max Ta ≤ 85˚C, (LC7537N, 7537AN) 200 mW Ta ≤ 85˚C, (LC7537NE) 300 mW Operating temperature Topr –40 to +85 ˚C Storage temperature Tstg *3 –50 to +125 ˚C Allowable Operating Conditions at Ta = 25°C, VSS = 0 V, VDD = ‡ V CC > VSS ‡ V EE Item Symbol Condition Rating Unit Supply voltage *1 VDD – VEE VEE ‡ –7.5 V 4.5 to 15 V VCC 4.5 to 5.5 V Input high–level voltage VIH1 *2 DI, CLK, CE 0.8 VCC to VCC V VIH2 INIT 0.8 (VDD – VEE ) + VEE to VDD V Input low–level voltage VIL1*2 DI, CLK, CE VSS to 0.2 VCC V VIL2 INIT VEE to 0.2 (VDD – VEE ) + VEE V Input signal amplitude VIN VEE to VDD VP-P Input pulse width tøW 1 min µs setup time tset up 1 min µs Hold time thold 1 min µs Operating frequency fopg up to 330 kHz

No. 5190-3/10 LC7537N, 7537AN, 7537NE Item Symbol Condition Rating min typ max Unit Total harmonic THD(1) VIN = 1 V, f = 1kHz, all flat overall 0.005 0.01 % Distortion THD(2) VIN = 1 V, f = 20 kHZ, all flat overall 0.006 0.02 % Crosstalk CT VIN = 1 V, f = 1 kHz, all flat, Rg = 1 kΩ 60 95 dB Vomin(1) VIN = 1 V, f = 1 kHz, MAIN, VR = ∞ , FADER VR = ∞ 80 90 dB Maximum attenuation output Vomin(2) VIN = 1 V, f = 1 kHz, MAIN, VR = ∞ , VDD = 8 V, FADER VR = ∞ , 70 80 dBVEE = VSS = 0 V, C between VSS and GND of L/R = 1000 µF R VOL (1) 5 dB-step 12 20 28 kΩ R VOL (2) 1 dB-step 12 20 28 kΩ VR resistance voltage R BASS 12 20 28 kΩ R TREBLE 12 20 28 kΩ R FADER 12 20 28 kΩ Output noise VN (1) All flat overall (IHF-A) Rg = 1 kΩ 2 10 µV VN (2) Rg = 1 kΩ , VDD = 8 V, VEE = VSS = 0 V 2 10 µV Current drain IDD VDD – VEE = 15 V 1 mA ICC VCC = 5 V 1 mA Continued on next page. Electrical Characteristics at Ta = 25°C, VDD =+7.5 V, VEE =–7.5 V, VCC =+5 V Pin No. Symbol Description of Functions Remarks 12(8) L.IN 31(29) R.IN 9(4) L.C1 34(33) R.C1 10(5) L.C2 33(32) R.C2 11(6) L.OUT 32(31) R.OUT 5(47) L.FIN 38(38) R.FIN 4(46) L.FOUT 3(45) L.ROUT 39(39) R.ROUT 40(40) R.ROUT 15(11) L.B1 16(9) L.B2 14(10) L.B3 28(26) R.B1 27(28) R.B2 29(27) R.B3 17(13) L.T1 16(12) L.T2 18(14) L.T3 26(24) R.T1 27(25) R.T2 25(23) R.T3 7(1) LCT1 6(48) LCT2 36(36) RCT1 37(37) RCT2 Main volume control block 5 dB-step attenuator input terminals. These pins should be driven at a low impedance. Main volume control block 5 dB-step attenuator output terminals. Having been designed to be open, the step positions will develop errors if at low acceptor impedances, so that as high load impedances as possible should be provided. VR resistance : 20 kΩ VR resistance : 20 kΩ VR resistance : 20 kΩ Main volume control block 1 dB-step attenuator input terminals. Theses pins should be driven at alow impedance. Main volume control block 1 dB-step attenuator output terminals. Due to the step positions designed to be open, load impedances as high as possible should be provided to them, similar to those for the LC1 and RC1. Fader functions employing mode input terminals. These pins should be driven at a low impedance. Fader block output terminals. These pins permit the front and rear sides to be faded out independently of each other. Attenuations exercised on Lch will be the same as on Rch. Due to the step positions designed to be open, acceptor impedances as high as possible should be provided to them. Pin Description ( ) : LC7537AN, 7537NE Bass tone control block terminals. A total of 15 positions have been provided in 2 dB steps Treble tone control block terminals. A total of 15 positions have been provided in 2 dB steps. The VR resistance value is 20 kΩ . VR resistance : 20 kΩ VR resistance : 20 kΩLoudness dedicated terminals. A high-frequency-range correcting C should be put between CT1 and IN, and low-frequency-range correcting C between CT2 and L–VSS (R–VSS ).

No. 2169-4/11 LC7537N, 7537AN, 7537NE Pin No. Symbol Description of Functions Remarks 8(2) L-VSS 35(35) R-VSS 42(42) INIT 22(20) CE 20(16) DI 21(17) CLK 1(43) VDD 23(21) VCC 19(15) VSS 24(22) VEE 2(3, 7) 41(18, 30, NC 34, 41, 44) (19) VDD (NC) Main volume control block fader control common terminals. The impedance of pattern connected to these pins should be as low as possible. Since L–VSS (R–VSS ) and VSS have not been connected inside the LSI, they should be connected together on the outside in conformance with their individual specifications. Particular attenuation should be paid to the capacitance assigned to the capacitors put between L–V SS (R–VSS ) and VSS , which will emerge as a residual resistive component when control is turned down for maximum attenuation. Intra-IC latch resetting terminal Control-setting data at the internal latch will be indeterminate when power has just been switched on, so that by engaging the “L” level of this pin at power-on, the fader control may be set at its –∞ position and muting behaviour is engaged (Note: V DD to VEE Level). Chip enable terminal. When this pin is made “H” to “L”, data is written in the internal latch, activating the various analog switches. When the “H” level is then restored, transfer of the data will be enabled. Input terminals for serial data and clock that serve control purposes. Continued from preceding page. These pins are connected to the relevant power supplies. Exercise caution against VCC rising earlier than VDD . No connect pins. Absolutely nothing should be connected here. LC7537AN and LC7537NE onlyVDD subterminal. Connected to VDD or left open.

No. 2169-5/11 LC7537N, 7537AN, 7537NE Control Timing Data Format

No. 2169-6/11 LC7537N, 7537AN, 7537NE Main Volume Control Block Equivalent Circuit Fader Volume Control Block Equivalent Circuit Tone Control Block Equivalent Circuit

No. 2169-7/11 LC7537N, 7537AN, 7537NE Sample Application Circuits Single Power Supply Unit (resistance: Ω , capacitance: F) Note: Bipolar electrolytic capacitors should preferably be employed where no polarity has been indicated.

No. 2169-8/11 LC7537N, 7537AN, 7537NE Dual ± Power Supply Unit (resistance: Ω , capacitance: F) Note: Bipolar electrolytic capacitors should preferably be employed where no polarity has been indicated.

No. 2169-9/11 LC7537N, 7537AN, 7537NE Single Power Supply Unit (resistance: Ω , capacitance: F) Note: Bipolar electrolytic capacitors should preferably be employed where no polarity has been indicated.

No. 2169-10/11 LC7537N, 7537AN, 7537NE Caution for Pattern Designing

• Space the patterns between L.IN and L.OUT and those between R.IN and R.OUT as far apart as possible. When forced to design them close together, provide shielding patterns between as illustrated. They will be effective at the maximum attenuated level (with 10 kHz and higher frequencies). (DIP42S)
• Make the L–V SS and R–VSS as broad as possible. Unit (resistance: Ω , capacitance: F)

This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. n No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n Anyone purchasing any products described or contained herein for an above-mentioned use shall: À Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: \` Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. No. 2169-11/11 LC7537N, 7537AN, 7537NE