LC72322

LC72322 SANYO | Alldatasheet

Document overview

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Technical content

The LC72322 is a single-chip microcontroller for use in electronic tuning applications. It includes on chip both LCD drivers and a PLL circuit that can operate at up to 150 MHz. It features a large-capacity ROM, a highly efficient instruction set, and powerful hardware. Functions

• Stack: Eight levels
• Fast programmable divider
• General-purpose counters: HCTR for frequency measurement and LCTR for frequency or period measurement
• LCD driver for displays with up to 56 segments (1/2 duty, 1/2 bias)
• Program memory (ROM): 4 k words by 16 bits
• Data memory (RAM): 256 4-bit digits
• All instructions are single-word instructions
• Cycle time: 2.67 µs, 13.33 µs, or 40.00 µs (option)
• Unlock FF: 0.55 µs detection, 1.1 µs detection
• Timer FF: 1 ms, 5ms, 25ms, 125ms
• Input ports*:One dedicated key input port and one high-breakdown voltage port
• Output ports*:Two dedicated key output ports, one high-breakdown voltage open-drain port Two CMOS output ports (of which one can be switched to be used as LCD driver outputs) Seven CMOS output ports (mask option switchable to use as LCD ports)
• I/O ports*: One switchable between input and output in four-bit units and one switchable between input and output in one-bit units Note: * Each port consists of four bits.
• Program runaway can be detected and a special address set (Programmable watchdog timer).
• Voltage detection type reset circuit
• One 6-bit A/D converter
• Two 8-bit D/A converters (PWM)
• One external interrupt
• Hold mode for RAM backup
• Sense FF for hot/cold startup determination
• PLL: 4.5 to 5.5 V
• CPU: 3.5 to 5.5 V
• RAM: 1.3 to 5.5 V Package Dimensions unit: mm 3174-QFP80E CMOS LSI 32896HA (OT)/83194TH (OT) No. 4797-1/13 SANYO: QFP80E [LC72322] SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN Single-Chip Microcontroller with PLL and LCD Driver LC72322 This LSI can easily use CCB that is SANYO’s original bus format.
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

No. 4797-2/13 LC72322

No. 4797-3/13 LC72322 Block Diagram

No. 4797-4/13 LC72322 Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max –0.3 to +6.5 V Input voltage VIN1 HOLD, INT, RES, ADI, SNS, and the G port –0.3 to +13 V VIN2 Inputs other than VIN1 –0.3 to VDD + 0.3 V Output voltage VOUT 1 H port –0.3 to +15 V VOUT 2 Outputs other than VOUT 1 –0.3 to VDD + 0.3 V IOUT 1 All D and H port pins 0 to 5 mA Output current IOUT 2 All E and F port pins 0 to 3 mA IOUT 3 All B and C port pins 0 to 1 mA IOUT 4 S1 to S28 and all I port pins 0 to 1 mA Allowable power dissipation Pd max Ta = –40 to +85°C 300 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –45 to +125 °C Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Ratings Unit min typ max VDD 1 CPU and PLL operating 4.5 5.5 V Supply voltage VDD 2 CPU operating 3.5 5.5 V VDD 3 Memory retention voltage 1.3 5.5 V VIH1 G port 0.7 VDD 8.0 V VIH2 RES, INT, HOLD 0.8 VDD 8.0 V Input high level voltage VIH3 SNS 2.5 8.0 V VIH4 A port 0.6 VDD VDD V VIH5 E, F port 0.7 VDD VDD V VIH6 LCTR (period measurement), 0.8 VDD VDD VVDD 1, PE1, PE3 VIL1 G port 0 0.3 VDD V VIL2 RES, INT, PE1, PE3 0 0.2 VDD V VIL3 SNS 0 1.3 V Input low level voltage VIL4 A port 0 0.2 VDD V VIL5 PE0, PE2, F port 0 0.3 VDD V VIL6 LCTR (period measurement), VDD 1 0 0.2 VDD V VIL7 HOLD 0 0.4 VDD V fIN1 XIN 4.0 4.5 5.0 MHz fIN2 FMIN, VIN2, VDD 1 10 130 MHz fIN3 FMIN, VIN3, VDD 1 10 150 MHz Input frequency fIN4 AMIN (L), VIN4, VDD 1 0.5 10 MHz fIN5 AMIN (H), VIN5, VDD 1 2.0 40 MHz fIN6 HCTR, VIN6, VDD 1 0.4 12 MHz fIN7 LCTR (frequency), VIN7, VDD 1 100 500 kHz fIN8 LCTR (frequency), VIH6, VIL6, VDD 1 1 20 · 103 Hz VIN1 XIN 0.50 1.5 Vrms VIN2 FMIN 0.10 1.5 Vrms Input amplitude VIN3 FMIN 0.15 1.5 Vrms VIN4, 5 AMIN 0.10 1.5 Vrms VIN6, 7 LCTR, HCTR 0.10 1.5 Vrms Input voltage range VIN8 ADI 0 VDD V Allowable Operating Ranges at Ta = –40 to +85°C, VDD = 3.5 to 5.5 V

No. 4797-5/13 LC72322 Parameter Symbol Conditions Ratings Unit min typ max Hysteresis VH LCTR (period), RES, INT, PE1, PE3 0.1 VDD V Rejected pulse width PREJ SNS 50 µs Power-down detection voltage VDET 2.7 3.0 3.3 V IIH1 INT, HOLD, RES, ADI, SNS, 3.0 µAand the G port: VI= 5.5 V IIH2 A, E, and F ports: E and F ports with 3.0 µA Input high level current outputs off, A port with no RPD , VI= VDD IIH3 XIN: VI= VDD = 5.0 V 2.0 5.0 15 µA IIH4 FMIN, AMIN, HCTR, LCTR: 4.0 10 30 µAVI= VDD = 5.0 V IIH5 A port: With an RPD , VI= VDD = 5.0 V 50 µA IIL1 INT, HOLD, RES, ADI, SNS, 3.0 µAand the G port: VI= VSS Input low level current IIL2 A, E, and F ports: E and F ports with 3.0 µAoutputs off, A port with no RPD , VI= VSS IIL3 XIN: VIN = VSS 2.0 5.0 15 µA IIL4 FMIN, AMIN, HCTR, LCTR: VI= VSS 4.0 10 30 µA Input floating voltage VIF A port: With an RPD 0.05 VDD V Pull-down resistance R PD A port: With an RPD , VDD = 5.0 V 75 100 200 kΩ IOFFH 1 EO1, EO2: VO = VDD 0.01 10 nA Output high level off leakage current IOFFH 2 B, C, D, E, F, and I ports: VO = VDD 3.0 µA IOFFH 3 H port: VO = 13 V 5.0 µA Output low level off leakage current IOFFL 1 EO1, EO2: VO = VSS 0.01 10 nA IOFFL 2 B, C, D, E, F, and I ports: VO = VSS 3.0 µA VOH 1 B and C ports: IO = 1 mA VDD – 2.0 VDD – 1.0 VDD – 0.5 V VOH 2 E and F ports: IO = 1 mA VDD – 1.0 V VOH 3 EO1, EO2: IO = 500 µA VDD – 1.0 V Output high level voltage VOH 4 XOUT: IO = 200 µA VDD – 1.0 V VOH 5 S1 to S28 and the I port: IO = –0.1 mA VDD – 1.0 V VOH 6 D port: IO = 5 mA VDD – 1.0 V VOH 7 COM1, COM2: IO = 25 µA VDD – 0.75 VDD – 0.5 VDD – 0.3 V VOL 1 B and C ports: IO = 50 µA 0.5 1.0 2.0 V VOL 2 E and F ports: IO = 1 mA 1.0 V VOL 3 EO1, EO2: IO = 500 µA 1.0 V Output low level voltage VOL 4 XOUT: IO = 200 µA 1.0 V VOL 5 S1 to S28 and the I port: IO = 0.1 mA 1.0 V VOL 6 D port: IO = 5 mA 1.0 V VOL 7 COM1, COM2: IO = 25 µA 0.3 0.5 0.75 V VOL 8 H port: IO = 5 mA, VDD 1 (150 Ω ) 0.75 (400 Ω ) 2.0 V Output middle level voltage VM 1 COM1, COM2: V DD = 5.0 V, IO = 25 µA 2.0 2.5 3.0 V A/D conversion error ADI: VDD 1 –1/2 1/2 LSB IDD 1 VDD 1, fIN2 = 130 MHz 15 20 mA IDD 2 VDD 1, PLL stopped, CT = 2.67 µs 1.5 mA(HOLD mode, Figure 1) IDD 3 VDD 1, PLL stopped, CT = 13.33 µs 1.0 mA(HOLD mode, Figure 1) Current drain IDD 4 VDD 1, PLL stopped, CT = 40.00 µs 0.7 mA(HOLD mode, Figure 1) VDD = 5.5 V, oscillator stopped, Ta = 25°C 5 µA IDD 5 (BACK UP mode, Figure 2) VDD = 2.5 V, oscillator stopped, Ta = 25°C 1 µA(BACK UP mode, Figure 2) Electrical Characteristics for the Allowable Operating Ranges

No. 4797-7/13 LC72322 Pin Pin No. Functions I/O I/O circuit type PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 PD0 PD1 PD2 PD3 PE0 PE1 PE2 PE3 PF0 PF1 PF2 PF3 PG0 PG1 PG2 PG3 Low-threshold type dedicated input port These pins can be used, for example, for key data acquisition. Built-in pull-down resistors can be specified as an option. This option is in 4-pin units, and cannot be specified for individual pins. Input through these pins is disabled in BACK UP mode. Dedicated output ports Since the output transistor impedances are unbalanced CMOS, these pins can be effectively used for functions such as key scan timing. These pins go to the output high- impedance state in BACK UP mode. These pins go to the low level during a reset, i.e., when the RES pin is low. Dedicated output ports These are normal CMOS outputs. These pins go to the output high-impedance state in BACK UP mode. These pins go to the low level during a reset, i.e., when the RES pin is low. I/O port These pins are switched between input and output as follows: Once an input instruction (IN, TPT, or TPF) is executed, these pins latch in the input mode. Once an output instruction (OUT, SPB, or RPB) is executed, they latch in the output mode. These pins go to the input mode during a reset, i.e., when the RES pin is low. In BACK UP mode these pins go to the input mode with input disabled. I/O port These pins are switched between input and output by the FPC instruction. The I/O states of this port can be specified for individual pins. These pins go to the input mode during a reset, i.e., when the RES pin is low. In BACK UP mode these pins go to the input mode with input disabled. Dedicated input port Input through these pins is disabled in BACK UP mode. Input Output I/O Input Continued on next page.

No. 4797-8/13 LC72322 Pin Pin No. Functions I/O I/O circuit type PH0 PH1 PH2/DAC1 PH3/DAC2 PI0/S25 PI1/S26 PI2/S27 PI3/S28 S1 to S24 COM1 COM2 FMIN AMIN 63 to 40 Dedicated output port Since these pins are high-breakdown voltage n-channel transistor open-drain outputs, they can be effectively used for functions such as band power supply switching. Note that PH2 and PH3 also function as the DAC1 and DAC2 outputs. These ports go to the high impedance state during a reset, i.e., when the RES pin is low, and in BACK UP mode. Dedicated output port While these pins have a CMOS output circuit structure, they can be switched to function as LCD drivers. Their function is switched by the SS and RS instructions. These pins cannot be switched individually. The LCD driver function is selected and a segment-off signal is output when power is first applied or when RES is low. These pins are held at the low level in BACK UP mode. Note that when the general-purpose port use option is specified, these pins output the contents of IPORT when LPC is 1, and the contents of the general-purpose output port LATCH when LPC is 0. LCD driver segment outputs A frame frequency of 100 Hz and a 1/2 duty, 1/2 bias drive type are used. A segment-off signal is output when power is first applied or when RES is low. These pins are held at the low level in BACK UP mode. The use of these pins as general-purpose output ports can be specified as an option. LCD driver common outputs A 1/2 duty, 1/2 bias drive type is used. The output when power is first applied or when RES is low is identical to the normal operating mode output. These pins are held at the low level in BACK UP mode. FM VCO (local oscillator) input The input must be capacitor coupled. The input frequency range is from 10 to 130 MHz. AM VCO (local oscillator) input The band supported by this pin can be selected using the PLL instruction. High (2 to 40 MHz) fi SW Low (0.5 to 10 MHz) fi LW and MW Output Output Output Output Input Continued from preceding page. Continued on next page.

No. 4797-9/13 LC72322 Continued from preceding page. Pin Pin No. Functions I/O I/O circuit type HCTR LCTR ADI INT EO1 EO2 SNS HOLD RES XIN XOUT TEST1 TEST2 VDD VSS 31, 73 Universal counter input The input should be capacitor coupled. The input frequency range is from 0.4 to 12 MHz. This input can be effectively used for FM IF or AM IF counting. Universal counter input The input should be capacitor coupled for input frequencies in the range 100 to 150 kHz. Capacitor coupling is not required for input frequencies from 1 to 20 Hz. This input can be effectively used for AM IF counting. This pin can also be used as a normal input port. A/D converter input A 1.28 ms period is required for a 6-bit sequential comparison conversion. The full scale input is ((63/96) · V DD ) for a data value of 3FH. External interrupt request input An interrupt is generated when the INTEN flag is set (by an SS instruction) and a falling edge is input. This pin can also be used as a normal input port. Reference frequency and programmable divider phase comparison error outputs Charge pump circuits are built in. EO1 and EO2 are the same. Input pin used to determine if a power outage has occurred in BACK UP mode This pin can also be used as a normal input port. Input pin used to force the LC72322 to HOLD mode The LC72322 goes to HOLD mode when the HOLDEN flag is set (by an SS instruction) and the HOLD input goes low. A high-breakdown voltage circuit is used so that this input can be used in conjunction with the normal power switch. System reset input This signal should be held low for 75 ms after power is first applied to effect a power-up reset. The reset starts when a low level has been input for at least six reference clock cycles. Crystal oscillator connections (4.5 MHz) A feedback resistor is built in. LSI test pins. These pins must be connected to V SS . Power supply Input Input Input Output Input Input Input Input Output Continued on next page.

No. 4797-10/13 LC72322 Mask Options Development Environment

• The LC72P321 is used for OTP.
• The LC72EV321 is used as the evaluation chip.
• A total debugging system is available in which the TB-72EV32 evaluation chip board and the RE32 multi-function emulator are controlled by a personal computer. No. Description Selections

1 WDT (watchdog timer) inclusion selection

2 Port A pull-down resistor inclusion selection

Pull-down resistors included No pull-down resistors 2.67 µs 3 Cycle time selection 13.33 µs 40.00 µs

4 LCD port/general-purpose port selection

General-purpose output ports

Abbreviations: ADDR: Program memory address [12 bits] b: Borrow B: Bank number [2 bits] C: Carry DH: Data memory address high (row address) [2 bits] DL: Data memory address low (column address) [4 bits] I: Immediate data [4 bits] M: Data memory address N: Bit position [4 bits] Pn: Port number [4 bits] r: General register (one of the locations 00 to 0FH in bank 0) ( ): Contents of register or memory ( )N:Contents of bit N of register or memory No. 4797-11/13 LC72322 Mnemonic Operand Function Operation Machine code 1st 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 AD r M Add M to r r ‹ (r) + (M) 0 1 0 0 0 0 DH DL Rn ADS r M Add M to r, r ‹ (r) + (M) 0 1 0 0 0 1 DH DL Rnthen skip if carry skip if carry AC r M Add M to r with carry r ‹ (r) + (M) + C 0 1 0 0 1 0 DH DL Rn ACS r M Add M to r with carry, r ‹ (r) + (M) + C 0 1 0 1 0 0 DH DL Rnthen skip if carry skip if carry AI M I Add I to M M ‹ (M) + I 0 1 0 1 0 0 DH DL I AIS M I Add I to M, M ‹ (M) + I 0 1 0 1 0 1 DH DL Ithen skip if carry skip if carry AIC M I Add I to M with carry M ‹ (M) + I + C 0 1 0 1 1 0 DH DL I AICS M I Add I to M with carry, M ‹ (M) + I + C 0 1 0 1 1 1 DH DL Ithen skip if carry skip if carry SU r M Subtract M from r r ‹ (r) – (M) 0 1 1 0 0 0 DH DL Rn SUS r M Subtract M from r, r ‹ (r) – (M) 0 1 1 0 0 1 DH DL Rnthen skip if borrow skip if borrow SB r M Subtract M from r with r ‹ (r) – (M) – b 0 1 1 0 1 0 DH DL Rnborrow Subtract M from r with r ‹ (r) – (M) – bSBS r M borrow, skip if borrow 0 1 1 0 0 0 DH DL Rn then skip if borrow SI M I Subtract I from M M ‹ (M) – I 0 1 1 1 0 0 DH DL I SIS M I Subtract I from M, M ‹ (M) – I 0 1 1 1 0 1 DH DL Ithen skip if borrow skip if borrow SIB M I Subtract I from M with M ‹ (M) – I – b 0 1 1 1 1 0 DH DL Iborrow Subtract I from M with M ‹ (M) – I – bSIBS M I borrow, skip if borrow 0 1 0 1 1 1 DH DL I then skip if borrow SEQ r M Skip if r equals M r – M 0 0 0 0 0 1 DH DL Rnskip if zero Skip if r is greater r – M SGE r M than or equal to M skip if not borrow 0 0 0 0 1 1 DH DL Rn (r) ‡ (M) SEQI M I Skip if M equal to I M – I 0 0 1 1 0 1 DH DL Iskip if zero Skip if M is greater M – I SGEI M I than or equal to I skip if not borrow 0 0 1 1 1 1 DH DL I (M) ‡ I Instruction GroupAddition instructionsSubtraction instructionsComparison instructions Continued on next page.

No. 4797-12/13 LC72322 Continued from preceding page. Mnemonic Operand Function Operation Machine code 1st 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 AND M I AND I with M M ‹ (M) I 0 0 1 1 0 0 DH DL I OR M I OR I with M M ‹ (M) I 0 0 1 1 1 0 DH DL I EXL r M Exclusive OR M with r r ‹ (r) (M) 0 0 1 0 0 0 DH DL Rn LD r M Load M to r r ‹ (M) 1 0 0 0 0 0 DH DL Rn ST M r Store r to M M ‹ (r) 1 0 0 0 0 1 DH DL Rn Move M to destination MVRD r M M referring to r in [DH, Rn] ‹ (M) 1 0 0 0 1 0 DH DL Rn the same row Move source M MVRS M r referring to r to M in M ‹ [DH, Rn] 1 0 0 0 1 1 DH DL Rn the same row MVSR M1 M2 Move M to M in [DH, DL1] ‹ [DH, DL2] 1 0 0 1 0 0 DH DL1 DL2the same row MVI M I Move I to M M ‹ I 1 0 0 1 0 1 DH DL I PLL M r Load M to PLL PLL r ‹ PLL DATA 1 0 0 1 1 0 DH DL Rnregisters Test M bits, then skip if M (N) = all 1, TMT M N if all bits specified then skip 1 0 1 0 0 1 DH DL N are true Test M bits, then skip if M (N) = all 0, TMF M N if all bits specified then skip 1 0 1 0 1 1 DH DL N are false JMP ADDR Jump to the address PC ‹ ADDR 1 0 1 1 ADDR (12 bits) CAL ADDR Call subroutine Stack ‹ (PC) + 1 1 1 0 0 ADDR (12 bits) RT Return from subroutine PC ‹ Stack 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 RTI Return from interrupt PC ‹ Stack 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 Test timer F/F if timer F/F = 0,TTM N then skip if it has then skip 1 1 0 1 0 1 1 0 0 0 0 0 N not been set Test unlock F/F if UL F/F = 0,TUL N then skip if it has then skip 1 1 0 1 0 1 1 1 0 0 0 0 N not been set SS N Set status register (Status register 1) 1 1 0 1 1 1 0 0 0 0 0 0 NN ‹ 1 RS N Reset status register (Status register 1) 1 1 0 1 1 1 0 1 0 0 0 0 NN ‹ 0 TST N Test status register true if (Status register 2) N =1 1 0 1 1 1 1 0 0 0 0 0 Nall 1, then skip TSF N Test status register falseif (Status register 2) N =1 1 0 1 1 1 1 1 0 0 0 0 Nall 0, then skip BANK B Select bank BANK ‹ B 1 1 0 1 0 0 B 0 0 0 0 0 0 0 0 Instruction Group Logical operation instructionsTransfer instructionsBit test instructions Jump and subroutine call instructions F/F test instructions Status register instructionsBank switching instructions Continued on next page.

No. 4797-13/13 LC72322 This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. n No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n Anyone purchasing any products described or contained herein for an above-mentioned use shall: À Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: \` Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. Continued from preceding page. Mnemonic Operand Function Operation Machine code 1st 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 LCD M I Output segment pattern LCD (DIGIT) ‹ M 1 1 1 0 0 0 DH DL DIGITto LCD digit direct LCP M I Output segment pattern LCD (DIGIT) ‹ PLA ‹ M 1 1 1 0 0 1 DH DL DIGITto LCD digit through PLA IN M P Input port data to M M ‹ (Port (P)) 1 1 1 0 1 0 DH DL P OUT M P Output contents of M to port(Port (P)) ‹ M 1 1 1 0 1 1 DH DL P SPB P N Set port bits (Port (P)) N ‹ 1 1 1 1 1 0 0 0 0 P N RPB P N Reset port bits (Port (P)) N ‹ 0 1 1 1 1 0 1 0 1 P N Test port bits, if (Port (P)) N = all 1, TPT P N then skip if all bits then skip 1 1 1 1 1 0 1 0 P N specified are true Test port bits, if (Port (P)) N = all 0, TPF P N then skip if all bits then skip 1 1 1 1 1 1 1 1 P N specified are false UCS I Set I to UCCW1 UCCW1 ‹ I 0 0 0 0 0 0 0 1 0 0 0 0 I UCC I Set I to UCCW2 UCCW2 ‹ I 0 0 0 0 0 0 1 1 0 0 0 0 I FPC N F port I/O control FPC latch ‹ N 0 0 0 1 0 0 0 0 0 0 0 0 N CKSTP Clock stop Stop clock if HOLD = 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 DAC I Load M to D/A registers DAreg ‹ DAC DATA 0 0 0 0 0 0 1 0 0 0 0 0 I NOP No operation 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Instruction GroupI/O instructionsUniversal counter instructions Other instructions