LC7185-8750 SANYO | Alldatasheet
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Technical content
Features
1, A built-in programmable divider for the 16MHz VCO 2. Transmission is inhibited when the PLL is unlocked (digital lock monitor). 3, Direct channel 9 or 19 selection (sliding switch) 4. A T-segment, 2-character LED display 5, "PA" is displayed in public announcement mode. 6. Output beep-tone control circuitry 7. Up to & channel settings can be stored in memory. 8. 4 x 3 key matrix implementation Pin Assignment ss] fl re sof [3] we sof] (3) vss1 at fz °° Package Dimensions 3061-D30SNIC se (5 [2a FOC (unit: mm) cag fs) mt Fd 6 sof] [23] Voo i — or [8] L7185-8750 [23] pm Tl HH oe ofl [aq rest 9 «td Ea na 4, C0 «2 0] [20] xin ' 13 [2] [13] xour bili a 04s o a EET Ey 3 xo (i [17) @&er " 6 ro? B [i kos i y ° "ep ven 0.95 008 178 SANYO: DIP30S SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE.Tokyo Bldg.,1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 5220TA —_No. 3366-1/13
Ki Ki2. KI3. KM KO KOZ KO3 4X 3KEY MATRIX ie ig Os 0 sc TO at — FOLD O | CONTROL. LOGIC cH bse = DISPLAY | | NTO DRIVER ee SF ODI Vo0 MEMORY. (_) CH DISPLAY — O02 vss 1.0 | O vss2 en tne! PROGRAMMABLE i _| O De OPO DIVIDER PHASE DET. aa UNLOCK XIN © He] REFERENCE OIVIDER oer. TIMING GEN. xouT J Qne o O Beep UL Pin Descriptions TX: Transmit/receive select ‘UL: Unlock detected output HOLD: Hold mode select PO: Charge pump output INIT: Initial input NC: NC pin TEST: Test point (input) SA to SG: Segment drivers (for display) Vpp.Vssi.Vss2: Power supply 01,D2: Digit output (for display) PIN: Programmable divider input KI to 4; Key inputs XIN,XOUT: Crystal oscillator input, KO1 to 3: Key scan outputs output (e.g. 10,240MHz) BEEP: Beep-tone contro! output No. 3356-2/13
Absolute Maximum Ratings at Ta=25C, Vgg-0V | unit Vatteee” SPY no max Pin Voo =0.3~49.0 v Input Voltage Vin(1)max Pins HOLD, TX 0.3~+15 v ‘Vin(2)max Input pins other than Vin(1)max —0.3~Voo +0.3 v Output Voltage Vo(1)max Pins SA,SB,SC,SD,SE,SF,SG,01,02 0.36 +15 v Vol2)max Pins UL,BEEP —0.3~+15 v Vo(3)max PinPO —0.3~Vop +0.3 v Vo(a)max Output pins other than mentioned above ~0-3~Voo+0.3 v Output Current lot1)max. Pins SA,SB,SC,SD, SE,SF,SG 0~ +30 mA lo(2imax Pins 01,02 O~ +10 mA Jo(3)max PinOL 0~+20 mA lolaymax PinBEEP o~+10 mA Bigwabie Power ed max (Ta<e5c) 350 mw Operating Topr —40~+85 c geareecature Tstg —55~ +125 c Temperature Allowable Operating Conditions at Ta=-40 to +86C, Vss-0V min typ max = unit Supply Voltage Vop 5.0 80 Vv "H"-Level Input Voltage ViH(1) Pins HOLD, TX 0.7VoD. 12 Vv VIH(2) Pin INIT 3.2 VooD =V Vi(3) Pins KIT,KI2,KI3,Kl4 0.6V00 voo Vv "L"-Level Input Voltage VIL(1) Pins HOLD, TX 0 0.3V00 OV ViL(2) Pin INIT 0 1.30°N ViLi3) Pins KN ,Kl2,KI3, Kid 0 0.4Vo0 Output Voltage Vout(1) Pins SA,SB, SC, SO, SE,SF,SG,D1,02 0 30O«~NV Vour(2) PinsUL, BEEP 0 8 Vv Input Frequency fin() Pin XIN (sine wave, capacitor coupled) 1.0 10.24 15 Miz firn(2) Pin PIN (sine wave, capacitor coupled) 10 30 Miz Input Amplitude Vint) Pin XIN (sine wave, capacitor coupled) 0.5 1.5 Vrms ‘Vin(2) Pin PIN (sine wave, capacitor coupled) 0.15 1.5 Vrms Required Oscillating —_x’'tal Pins XIN,XOUT(CI<502 ) 5.0 10.24 15 Miz Frequency Electrical Characteristics at under allowable operating conditions min typ max — unit Internal Feedback RE) Pin XIN 1.0 Ma Resistance RE(2) PinPIN 500 ka Pull-down Resistor RpdN Pins KI1,Ki2,KI3,Ki4, TEST 30 50 mM ka "H"-Level Input Current. liK(1) Pins HOLD,TX Vi=12V 5.0 uA ta(2) Pin iNT Vi=Voo. 5.0 uA (3) PinXIN Vi= VoD 2 WA wH(4) PinPIN Vi=Vod 60 uh "L"-Level Input Current iiL(1) PinsHOLD. TX Vi=Vss 5.0 uA 42) PiniNIT Vi=Vss 6.0 uA (3) PinXIN Vi=Vss 25 WA W(4) PinPIN Vi=Vss. 50 uA “H"-Level Output Voltage VoH(1) PinsKO1,KO2,KO3 lo=tmA Voo-2.0 Voo—-1.0 Voo—0.5 v Von(2) PinPD © lo=0.5mA Voo~1.0 Vv Continued on next page. , No. 3366-3/13
Continued from preceding page. min typ mex unit "L"-Level Output VoL) PinsKO1,KO2,KO3lO=20u A 0.6 1.0 1.4 Vv Voltage VoL(2) PinPD lo=0.5mA 1.0 v Vo (3) PinBEEP lo=emA 1.0 v Vou(4) Pins SA,SB,SC,SD,SE,SF,SG 1.0 Vv fo=20mA Vow(5) Pins 01,02 lo=5mA 1.0 Vv Vou(6) PinOL fo=10mA 10 Vv Output Leakage lorF(1) Pins SA,SB,SC,SD,SE,SF,SG 5.0 uA Current Pins 01,02 Vo=13V 5.0 uA lorF(2) Pins UL.BEEP Vo=8V §.0 uA (tee Tristate |OFFH Pin PD Vo=Vvoo 0.01 10.0 nA Leakage Current "L"Level Tristate IOFFL PinPD Vo=Vss 0.01 10.0 nA (sone Current Supply Current loo(1) Normal mode § 10 mA K 1 (PLL operates) loo(2) Hold mode Voo=3.0V 5 uA >€2 (memory backup) Voo=8.0V 15 #A DK 1: fin(2)=20MH2(PIN) > 2: HOLD=Vss Vint2)=0.15Vrms TX=INIT=Voo X'tal=10.240MHz, Other inputs =Vss TX=HOLO=iNIT=Voo Other outputs =open Other inputs =Vss Other outputs =open Note: Be careful that the dielectric strength of pins SA, SB, SC, SD, SE, SF, D1, D2, UL, BEEP are weak, Key Matrix AM? AY? cH KM ME PA Dp Dp 3 13 ‘ae D As Kia koa 02 OL CH9 : Emergency CH recall UP/DN/ME/MI~§ —: Momentary SW CHI9 : Emergency CH19 recall CH9 /CHI9/PA : Slide SW PA : Public announcement display MODE 1 / 2 : Diode MODE 1 / 2 : Display Mode uP + CH up/ scan ON :CH down/ scan ME : Station Memory Enable Mi~M5 : Station Memory recall No, 3356-4/13
LED Display Configuration (Common anode/7 segment) “FS TY 2a la al 4 leo u| i {uv 2| fe | Je efedeoba 2d 1d [iso Tse Tse [so [so [se [sa | peer po fe fv fe [ie [te [w|i | o2 01 [oe | [a | [a |e [ofa | Pin Description [Pin Name [Pin No.[ Type escription 1™ 30 + Transmit/receive select HOLD 26 * Hold mode select oO > HOLD="0"...Hold mode select ="1",.,.Normal mode select iNIT ys) + Reset line fa d> INIT="0",,.Reset TEST *Test point (input) p Tie to ground or leave floating Voo *Power supply (+) — Normal mode: 5.0 to 8.0V Hold mode: 23.2V PIN 23 + Programmable divider input 150mVrms min | Hold mode: Programmable divider is disabled. XIN 20 XOUT 19 * Crystal oscillator Frequency: 10.24MHz a Hold mode: Oscillator is disabled. Continued on next page. No, 3356-5/13
Continued from preceding page. 2 «Charge pump output from the phase comparator - fV is obtained by dividing the PIN frequency input by N (programmable divider value) - fR is the reference signal (reference divider output) —S fV>fR OR leading: Positive Pulses fV<fR OR leading: Negative Pulses fV=fR and phase muched: High impedance Se Hold mode: High impedance 28 + PLL circuit and controller ground [No [ee correction i UL * Unlock detected output Low level: See Unlock Detected Output (UL) for detail. 4 _ Open: Locked BEEP 17 * Beep-tone control output Open: See Beep-tone Control Output for detail. a Low level: Hold mode. SA 1 + Segment drivers for the display to to (Common anode/7 segments) SG 7 4 + + Digit output (150Hz) for the display (Common anode/7 segments) Hold mode: Tr goes off. — —_ Ki 10 + Key inputs to to Input from the key matrix Ki4 13 o > KOI 14 * Key scan output (75Hz) to to Output to the key matrix KO3 16 Hold mode: Low (scanning stops) No, 3355-6/13
(1) Channel Selection (up/down) The unlock detected line (UL) is asserted (low) when the UP (or DN) key is pressed and deactivated 25ms after the key is released (see diagram below). The beep-tone contro! line (BEEP) is asserted (open) for 50ms after each new channel is selected (see diagram below). 1) Manual scanning (up/down) Pressing the UP key increments by one channe! and pressing the DN key decrements by channel. When scanning reaches the end of the band, it automatically wraps around to the beginning, 2) Auto scanning (up/down) Holding the UP (or DN) key down for 500ms_ or longer starts auto scanning. For both up and down scanning, each channel takes 100msec to scan. UP /ON Key BAND EDGE CH cH cH Vcr ~~ cH YH cH Channel a= A ntti Ant2A_ 40 i 2 OPEN OPEN er fC PLU LULL | > fe-25ms OPEN Po (2) Selecting an Emergency Channel (CH9/CH19) If the CH9 or CH19 switch is turned on, the LC7185 does the following: *Stores the value of the previous channel Asserts the beep-tone control line for 50ms Disables the UP/DN, M1 to M5, and ME switches Causes either "9" or "19" to blink on the display -Keep the emergency channel open until the CH9 or CH19 switch is turned off. After the CH9 or CH19 switch is turned back off the beep-tone control line is asserted for 50ms and the LC7185 reopens the previous channel. Note the CH has a higher priority over CH19. As a result, if both switches are turned on, CH9 will be opened. As shown in the diagram, the UL line is asserted for 25ms after the CH9 or CH19 switch is turned off or on, CHO/CHI9 Switch | | 50m 7h an weit es a betins | fe 25ins Lock: Open , No. 3366-7/13
(3) Public Announcement (PA) Mode When the PA switch is turned on, the LC7185 does the following: Stores the value of the previous channel -Disables ali keys «Causes "PA" to be displayed ‘Stays in PA mode until the PA switch is turned off. When the PA switch is turned back off, the LC7185 leaves PA mode and reopens the previous channel. As shown in the diagram, the UL line is asserted while the PA switch is turned on. PA Switen | | Channel cH cH (Display) a n BEEP | | | Vo ios } OPEN (4) Transmit/Receive Selection When the TX line is asserted, the LC7185 enters TX mode. The LC7185 will only leave this mode if the PA switch is pressed or the TX line is deactivated. As shown in the diagram, the UL line is asserted for 25ms after the TX line is asserted or deactivated. Pin | ! RX ™ aX MODE MODE MOE BEEP | | ey I Lock: Open (5) Channel Preset/Recall Facility 1. The LC7185 allows up to 5 channels to be preset (assigned to M1 to M5). ‘After a reset, M1 to M5 are assigned to CH33. 2, Recalling preset channels +A preset channel is recalled by pressing one of the preset memory keys (M1 to M5)* to which the channel was previously assigned. *Presetting channel (assigning keys) are covered in the next section. There are two different display modes as shown below. Mode_1 (without diode) Each time a key is pressed (e.g. M1), the new channel is displayed. Example: Display 21———~15 Key Mode 2 (with diode) Each time a key is pressed (e.g. M1), a key mnemonic (e.g. "P1") is displayed for 400msec, then the new channel is displayed. Example: Display 21—— P1—+ 15. 400ms Key . No. 3356-8/13
— SSSFSSSSSSSSSSSSSSSSSSSSSSSSS 3. Presetting channels Presetting a channel is done in the following way. First select the channel to be preset, then hold down the ME key and press the preset memory key (M1 to M5)* to which you would like to assign the current channel. in the following cases, a channel will not be preset: 9 seconds elapse after the ME key is pressed and one of M1 to MS is pressed. “Emergency channels CH9 or CH19 are currently selected, ‘The TX line is asserted, +The PA switch is turned on (PA mode). ‘The HOLD line is asserted (hold mode). There are two different display modes as shown below. Mode _1 (without diode) The current channel is displayed throughout the preset process. Example: Display 15 ———> 15 Key Mode 2 (with diode) When the ME key is held down, "PE" is flashed on the display. Once a preset memory key is pressed (e.g. M1), the key mnemonic (e.g. "P1") is displayed for 400msec before the current channel is redisplayed. Example: Display 15 —» PE —» P1——+15 400ms . Key (ME] *Note that if two or more keys are pressed at the same time, priority is assigned as follows: M1>M2>M3>M4>M5. (6) Beep-tone Control! Output After each of the following events, the BEEP line is asserted for 50msec: “A reset (e.g. battery replacement) Any key press associated with the channel memory “Any emergency channel switch activation +A new channel is selected sLeaving hold mode (7) Unlock Detected Output (UL) In the following cases, the UL line is asserted for the duration indicated. a vin AFAR Ar Phase difference When the phase difference between the programmable and reference divider outputs exceeds 3.2us .. The UL line is held low for 6ms after the last out-of-range phase sample is detected, as shown below. “After a new transmit/receive or channel selection. The UL line is asserted for 25ms . ‘While the PA switch is turned on. eee en . No. 3356-9/13
(8) Key Matrix It is normat to put diodes in series with the key scanning lines to avoid creating a short with the output lines, But KO1, KO2 and KO3 lines don't need diodes. unit : k& pow eo, ku RONN RONP, RONN : On impedance RpdN : Pull-down resistor M2 uP cH kn J KI2 cHI9 $ KB PA D © 3 os>
7 DP *
{| O Koz fi a Ko3 fi O Hold Mode The LC7185 enters hold mode when the HOLD line is asserted. In this mode, the channel preset/recall RAM is not affected. (1) System Status The LC7185 will remain in hold mode until the HOLD line is deactivated or a reset occurs (INIT line is asserted). The programmable divider, crystal oscillator, and reference divider are all inhibited, Signa! output levels are shown below, PD: High impedance UL: Vss (ground) 01, D2: High impedance . BEEP: Vss KO1 to K03: Vss When the LC7185 leaves hold mode, the previously selected channel is reopened. (2) Reset To reset the chip, assert the INIT line, Reset state: *CH9 is selected. -Preset_ memory keys are all set to CH33. Linear cireuit POWER ACC sw sw HOLD D { Rea | ° ev “ = mth BATTERY T i Ah vss . No, 3356-10/13
(3) Timing Requirements for Hold Mode HOLD pin :
1 Voo pin vot
i ! | | 3.2v — }\\ i oan te i vss _ : bt (=ov) at a t HOLD > 6.0ms ! ft 2.0ms Norma! mode Hold move Normal mode VDD must remain at S.0V or higher (crystal oscillator requirement) for 6.0msec (tHOLD) after the HOLD line is asserted (HOLD<0.3Vpp). After this Vpp may go as low as 3.2V. There are no constraints on timing when the chip is leaving hold mode. The signals can be activated in one of two orders. 1) If HOLO is already deactivated (>0.7Vpp), the LC7185 leaves hold mode within 2,0msec after Vpp rises to >5.0V. 2) If VoD is >5.0V, the LC7185 enters normal mode within 2.0ms after HOLD is deactivated. (4) Reset Timing 1) Reset timing (e.g. battery replacement) Voopin —~i 5.0V — — —— NT pin 1.3 — Vss [LI f {=0v) ~ 7 ee t INIT > 1.0us Note: tiNiT should be greater than 1.Qus . 2) Reset caused by a sudden voltage (Vpp) drop Yoo pin; 3.2v — Lor (=0y) TT A Note: If Vpp drops momentarily down to less than 3.0V and rises up to more than 5.0V (t>1.0us ), a reset may be generated. , No, 3366-11/13
Frequency Table (U.S.A.; L.C7185-8750) FREGUENGY 1 26.965 6508 16.27 §393 13.4825 2 26.975 6512 16.28 5395 13.4875 3 26.985 6516 16.29 §39? 13.4925 4 27.005 624 16.31 5401 13.5025 5 27.015 6628 16.32 5403 13.5075 6 27.025 8532 16.33 5408 13.5125 ? 27.036 6536 16.34 5407 13.5175 8 27.055 6544 16.36 $411 13.5275 9 27.065 6548 16.37 §413 13.5325 10 27.075 6552 16.38 5415 13.5375 iW 27.085 6556 16.39 6417 13.6425 12 27.105 6564 16.41 5421 13.5625 13 27.416 6568 16.42 5423 13.5575 * 14 27.125 6572 16.43 5425 13.5625 15 27.136 6576 16.44 5427 13.5675 16 27.185 6584 16.46 5431 13.6775 17 27.165 6588 16.47 $433 13,5825 18 27.175 6592 16.48 $435 13.5875 19 27.185 6596 16.49 §437 13.5925 20 27.208 6604 16.51 5441 13.6025 ei 27.215 6608 16.52 $443 13.6075 2 27.226 6612 16.53 5445 13.6125 23 27.255 6624 16.56 9451 13.6276 24 27.238 6616 16.54 $447 13.6175 25 27.245 6620 16.55 5449 13.6225 26 27.265 6628 16.57 | $453 13.6325 2 27.275 6632 16.58 $456 13.6375 28 27.285 6636 16.59 | 5457 13.6425 ra] 27.295 6640 16.60 | 5459 13.6475 30 27.305 6644 16.61 5461 13.6525 "31 27.315 6648 16.62 5463 13.6576 32 27.325 6652 16.63 5465 13.6625 33 27.336 6656 16.64 5467 13.6675 34 27.345 6660 16.65 5469 13.6726 35 27.355 6664 16.66 6471 13.6775 36 27.385 6668 16.67 5473 13.6825 37 27.328 6672 16.68 5475 13.6875 38 27.385 6676 16.69 9477 13.6925 33 27.395 6680 16.70 5479 13.6975 40 27.405 6684 16.71 $481 13.7025 Veo (TX) =RF+ 2 Veo (RX) =RF—10.695MHz (IF) CH1 !Vco (TX) =26.965+ 2 =13.4825 : No. 3366-12/13
Sample Application Circuit au — =hss ue 1 () Y MHz Lee | ace ca ee a eres T sw TK AX ca LE . STEER E EZR RES 3 = et BEPe pe Seg Pe gees K 07185-8750 SRBSS4%KBsSERSEL ZZ ES oat Tun f=] [2] mya Cam eg ae p [33 woe we Men fe a (LEO DISPLAY) (KEY MATRIX) Mi No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. @ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO, LTD, its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and Itigation and all damages, cost and expenses associated with such use: ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or itigation on SANYO ELECTRIC CO, LTD, its affilates, subsidiaries and distributors or any of their officers and employees jointly or severally. 1 Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production, SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use oF any infringements of intellectual property rights or other rights of third parties. No. 3366-13/13