LC7153

LC7153 SANYO | Alldatasheet

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Ordering number: EN 4160A CMOS LSI LC7153, LC7153M Vi . SANYO im Universal Dual-PLL Frequency Synthesizers Overview Pin Assignment The LC7153 and LC7153M are universal dual-PLL frequency synthesizers for use in cordless telephone xn Gi} 24] xouT applications in the USA, South Korea and Australia, and ce [2] [23] Pose satellite broadcast tuners in the USA and Europe. a Bl post . The LC7153 and LC7153M both have two PLLs with a o [4] [2] a6 16-bit programmable divider to generate a 1.5 to 160 Us [s] [20] Ace MHz local-oscillator frequency, and a phase detector. wK [6] Levisa [9] OU They also have a dual charge pump and fast lock-up ca [7} LO7153M_ [ia} ca circuitry for rapid PLL locking when changing frequen- vest [3] [y7] voo cy, an unlock indication output and an uncommitted roa [9| [16] ie output under external control. The PLLs share a 14-bit poat [10] [15] vss divider to generate a 320 Hz to 640 kHz reference aa [as] PA fi i 10.24 MHz crystal. cond requency using a ry’ soa [re] [3] 8% 1 view The LC7153 and LC7153M can be controlled from an external microcontroller using a C?B serial interface. Pack: Di : They also have a standby mode for single PLL opera- ‘ackage Dimensions tion. Unit: mm The LC7153 and LC7153M operate from a 4,0 to 5.5 V 3067-DIP24S supply. The LC7153 is available in 24-pin DIPs, and the 1107159) LC7153M, in 24-pin MFPs, os 3 meoeponooong + Dual charge pump and fast lock-up circuitry for rapid 7 2 PLL locking a anz. 3,9 max 0.25 * PLL unlock indication —t * 16-bit programmable local-oscillator divider + 15 to 160 MHz local-oscillator frequency (Vop = 4.0 aa to 5.5 V) * 14-bit programmable reference-frequency divider oath 05s 178 a * 320 Hz to 640 kHz reference frequency using a 10.24 MHz crystal 3112-MFP24S + LPF transistor + C’B serial interface ae ROTISSM] + 4.0 0 5.5 V supply ABARPARRARAA + 24-pin DIP (LC7153) and 24-pin MFP (LC7153M) T “T | 1 a 1 1 ad 0.15 18 max 15 L 12.6 L O41 iaarreyy Tose wot SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg.,1-10,1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 33195TH (ID)/9302JN No. 4160—1/11

LC7153, LC7153M Block Diagram OUTB | ' PLLB phase sana pose ere, ‘and fast | lock-up PoOB = i yO | sr | Ala ma D von s+ SEE, rove | cis vse | m cE a | AOA =f a mF Po ‘OUTA cA Pin Functions a a a a a a ee a ee Fast lck-upcapecor A conection a ee a ee [0 | Par PULA asec main on a ee a ee a ee No. 4160—2/11

LC7153, LC7153M a a a a a a OC a a [2 [er run earned a a Specifications Absolute Maximum Ratings T. = 25 °C ee [EDK COB, GOT and OTE ouput coro age ||| }AOK ed AOG ova cmon ge Tm Te Tm | ee i cd (Note) Pins PIA, PIB, CA and CB have a weaker electrostatic breakdown strength than the other pins. Recommended Operating Conditions Ta = 25 °C a a Ec No. 4160—3/11

LC7153, LC7153M — SSSSSSSSSSSSSMMMee

Electrical Characteristics

Yop = 4.0 to 5.5 V, Vss = 0 V, T. = —40 to 85 *C unless otherwise noted Von = 45 V, {| = 60 MHz. Sea note 1. Voo = 55 V, fi = 160 MHz. See note 1. Supply current Vo 24s DD = 4.5 ¥, Voo = 5.5 V, 110 | = 160 MHz, See note 2 rly neo Pw | fe fe fm [| voltage PDAt and PDB1 LOW-level output y v volage four PDA2 and PDB2 LOW-evel output faerermmiennwew |e fee TT fe [| TDA, IDB, OUTA and OUTE y y LOW-leval output voltaga ‘ou AOA end AOB LOW-lvel output You Van = Vag = 1.2 V voltage lo = 1 mA, Van = Vag = 1.3. V f PDA2 and PDB2 HIGH-level output _ ek a oe OT oe Pom | fle fe fw |v Voe v voltage CA and CB LOW-level thrashold CA and CB HIGHJevel threshold CE, CL and Di LOW-evel input . foowie wom [we |ieevw-sv | = | | « | a sit None om ee ee currant ~ No. 4160—4/11

C7153, LC7153M sn mf [| PDA, PDB1, PDA2 and PDB2 output _ ese ar HHL am | Yon assy Pf | "0 |» | AOA, AOB, OUTA and OUTB output . leakage current Vo =13¥ pA Fast lockup mode 0 CA and xcmpmeee [ee florsviwonsov | sim [woo | asco | ms | int cet marae |» [wesovnonsev | ain | anew | sien | | Fast lock- jode 2 CA Fast lock-up mode 3 CA and CB - . Ea Capacitively coupled PIA and PI ipa Fenverey | oe | sing wave, Vop = 6.0 V Pos f= [| om | i Capacitively coupled PIA and PIB ms np amide | oe [ere [oe | - | @ | | PIA and PIB intemal feedback Notes 1. Dual PLL, both PLLA and PLLB operating, SB = 0, fra, = 10.24 MHz, Vera = Vein = 70 mV, all other inputs =

0 V, all outputs open

1. Standby mode, PLLB stopped, SB = 1, fxrar = 10.24 MHz, Via = 70 mV, all other inputs = 0 V, all outputs open 3. CI is the crystal impedance. Contact Nihon Denpa Kogyo for further information. No. 4160—5/11

LC7153, LC7153M Serlal Data Input Timing feet les arr : ' a 1 cE i i Hi ' | ’ H 1 rot rot tort tr ' hoa \\ a '

0 LX XE

H eee ' Latch x basa ep tine ee 2k Data hold tima LOW-lavel chip enable time Chip enable soup time es Chip enable hold time LOW-evel clock pulsewidth tee HiGH-leval clock pulsewidth ‘cu ee Chip enable to data latch time ta MI No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. M Anyone purchasing any products described or contained herein for an above-mentioned use shalt: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO, LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and ligation and all damages, cost and expenses associated with such use: ® Not impose any responsibiity for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. ; No, 4160—6/11

table 1. becomes R1MIIR1S, decreasing the LPF time constant Table 1. Phase-detector output states and the time required to lock the PLL. Figure 1. Dual charge-pump circuit when the PLL is locked. In this case, R1 becomes R1M, sideband and modulation response.

the mode number, the greater the expansion width of the operates normally, as shown in figure 4. detected phase error signal. Table 2. Fast lock-up mode Poasserorg@) LP LIL..IL__L Table 3. Frequency ranges stopped, PIB is pulled LOW, and PDBI and PDB2 are = 0, operating mode 0 is selected and the fast lock-up changed. LDB, can change state. The extension for different no Output extension occurs. Table 5. LDA, [DB output extension

phase-insensitive bandwidth, or dead zone, of the phase for normal operation. circuit is shown in figure 5. The telephone is tuned to MHz.

46.610 MHz H I

Figure 5. American 10-channel, 46/49 MHz, cordless telephone base station For frre = 5 kHz, the divider ratios are as follows.