LC7074M SANYO | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
LC7074, 7074M SAKYO Synchronous Error Correction LSI for RDS Applications Overview Package Dimensions The LC7074 and the LC7074M are ICs for the RDS (radio unit: mm data system) implemented by the EBU (European 3907A-DIP18 Broadcasting Union) and the RDBS (radio broadcast data system) implemented by the NRSC (National Radio DIP Package Product System Committee) in the USA. ” 0 RDS and RBDS are standards that allow data to be PCa ano ou broadcast multiplexed with other FM broadcasts. When Ds 338 combined with an IC in the LA2230 series, the LC7074/M ee ay ‘ ° DO OU synchronizes with data multiplexed in an FM broadcast | —— 24.2 Fo 5 i en and detects and corrects errors in that data. The Koo ai synchronized data is output as a serial signal which can f H / vv y / ff then be decoded and processed on the system control H Yl — microprocessor. OS 12 2.54 SANYO: DIP18 Functions + Group synchronization RDS group synchronization 3095-MFP18 MMBS/RDS group synchronization MFP Package Product 215 + Error detection and correction Fi AARAAAR y » Error detection function enable/disable selection ee + Serial data output ~ wl * Serial data clock polarity selection -- “) ae + Data block start signal output “TTEET AEE Features " 12.6 s + Systems that decode, synchronize and detect and correct F] ae . errors can easily be constructed by combining the 2 2 SIAR SANyo : MFP1e 1LC7074/M with an LA2230 series product. 8129 || 035 + Reduces overhead in the microprocessor that decodes 127 and processes the RDS or MMBS/RDS data. Product-Package Relationship Sr SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg,, 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 12094JN B8-0839 - 0840 No. 4789-1/18
LC7074, 7074M SSS Pin Assignment 4 MHz ceramic oscillator iT It oscs 14] [se} osce Vest re Ves3 a The DIP and MFP product pin assignments are identical. The LC7070 Series This section describes the differences between the different products in the LC7070 series. Usage Notes The basic functions, including the pin functions and J/O timing, are identical in all products in the series, However, some pin circuits and function operation details differ. * LC7070NM ...While the LC7074M is pin compatible with this product, the circuit type of the three output pins differs as shown in table, Package and Output Driver Type Comparison. These products can be interchanged to match the output interface. However, since the data output method following synchronization detection differs as shown in table, Comparison of Functional Differences, care is required in writing programs that receive, decode and process the output data for the control microprocessor. shown in table, Package and Output Driver Type Comparison. These products can be interchanged to match the output interface. However, since the data output method following synchronization detection differs as shown in table, Comparison of Functional Differences, care is required in writing programs that receive, decode and process the output data for the control microprocessor. + LC7071NM....The LC7074M is pin compatible with this product, and the Pin circuit types, pin functions, and signal timings are identical. In principle, these products are interchangeable. However, since the data output method following synchronization detection differs as shown in table, Comparison of Functional Differences, care is required in writing programs that receive, decode and process the output data for the control microprocessor. timings are identical. Furthermore, the synchronization detection method and the post-synchronization data output method are also identical. In principle, these products are interchangeable. However, since these products handle the block offset words E and F differently, and also handle MMBS/RDS data differently as shown in table, Comparison of Functional Differences, care is required in writing Programs that receive, decode and process the output data for the control microprocessor. timings are identical. Furthermore, the synchronization detection method and the post-synchronization data output method are also identical. In principle, these products are interchangeable. However, since these products handle the block offset words E and F differently, and also handle MMBS/RDS data differently as shown in table, Comparison of Functional Differences, care is required in writing Programs that receive, decode and process the output data for the control microprocessor. ee SSSSSeeSSSSSSSSSSSsSSSSsSSSSSSSSSSSeee No. 4789-2/18
C7074, 7074M sO SSSsSSSSSSSSSSSSSSSSSSSSSSSSS—SS— Package and Output Driver Type Comparison LETO7ON Open d ain type LC7070NM [were SSSS~*diSC en rain we Identica! functions LG7071NM MFPi6 Pull-up MOS transistor (CMOS type) Lo7073 DiPté See table, Comparison of Toro7aM wEPTS Pull-up MOS transistor (CMOS type) Functional Dotloronces, Lo7o74 DIP18 See table, Comparison of C7074 [wera] Pulbup MOS transistor (CMOS type) Functional Detferences, Note: * Only applies to the three pins DATA START, DATA OUT and CLOCK OUT. Comparison of Functional Differences LCvOvONM Lo7073 Le7074 Lo7071NM Le7073M tc7o7em Offset word E These are taken to be offset words | Thesa are not seen as offsat words. | Olfsel words A, B,C, C, DandE and a group synchronization Only offset words A,B, C,C’ and D | are detected. Offset word F detection operation is performed. _| are detected. Offset word F is not detected. All zaro data is not seen as being an offset word E block. Rather, all zero data is taken to All zero data is taken to be an offset eohennetee foto one All zero data is seen as an offset All zero data word E block. Accordingly, an ottset | Pera ront word E block, Accordingly, an offset (corresponding to offset E) word E block synchronization ; word E block synchronization ‘ Hea Wall zero data is input, these sporation oe tema operation is performed. products decide that data input has | °P Performa ‘stopped, and they stop outputting data and enter the pullout sequence. For the transition from an ROS group (ABCD) fo an MMBS group | Since these products do not (EEEE) or the reverse transition, | synchronize on an offset word E these are taken to be the pull-out | block, each time an RDS group is | MMBS/RDS data is correctly output MMBS/RDS compound deta and resynchronization sequences. | inserted in an MMBS group, they _| with no pull-out and no errors. During transitions, date errors can | repeat the pull-out and occur and data output can be resynchronization sequences, interrupted. ‘Synchronization is achieved when the offset words in five out of 12 | Synchronization is achieved when the offset words in two out of three Synchronization detection method | biccks are dotocted in the correct | blacks are detected in the correct order, order. P When synchronization detection completes with an offset word A block, Data naa tre cata | output starts with the data in the second block (the offset word B block) Post-synchronizaton detection data | 47 ine ore {ine otsot wers | fromm the same group, output *oUp for whi ets meh sin i "© | When synchronization detection completes with an offset word B, C or D Sotention whiel owe ‘ ° ‘ zation block, output starts with the data in the first block (the offset word A block) fection was completed. from the same group. Pullout determination method When the offset words from five or more consaculive blocks were not detected. In modes where error correction is enabled, up to five error bits are corrected for distances of 5 bits or less. mS No. 4789-318
LC7074, 7074M ee Block Diagram e & re 5 Ea 5 a = ow 3 5 ¢ x FA < Fa <« @ 5 8 - 8 Ba § . 8 a a a H i H H H H i io i ig H 5 Ao i 8 = ia i 8 5 5 H i 3 5. { i 3 ao 5 | t 2 ria) Fd 1 H 3 5° 2 H H 3 3 3 i } é gay ie H <5 al H a} > H gi 3 i - 3 i aO 3g H ai § 3 di 8 Fa & i ¢ s H i 3 i 6 | = 7° a} { @ | H 80~- ! j 55 i H 55 H «i ee H FA } 20 ge | : 35 i ay 38 i i 55 i 4 H a} H gi i Bi H i i i i H Lo i 5 d% i 8 ia, i 3 —O8 2 i. 1 5 oD H —0 8 i ys i i i 8 H +> i j Leeaeee ne ewenenenee. C) eeeene. C)} Oe ee f z z < x < FA < 8 a 5 Fe Ee No. 4789-4/18
C7074, 7074M Pin Functions Vp. Vgst ; Vgg2, Veg Power supply osct Clock oscillator osc2 Connect the external ceramic oscillator and capacitor at these pins. 02078 clock IN ADS demodulation clock input Connect to the clock output from the LA2230 series demodulation IC. A0z080 DATA IN oO ROS demodulation data input Connect to the data output from the LA2230 series demodulation IC Aozoso Error correction selection input This pin selects whether the IC corrects errors in the RDS demodulated data. Input =0: No correction pertormed* CORR.SEL Input = 1: Error correction performed aozo8o In modes where error correction is enabied, up to five error bits are corrected for gistances of § bits or less. Seriat data clock output polarity selection input Input = 0: Serial data output is vatid on the rising edge of the output CLED SEL lock. (Data output changes on the falling edge of the clock.) Input = 1: Serial data output is valid on the falling edge of the output Aoz080 lock, (Data output changes on the rising edge of the clock.) Block data siart signal control input D.S.CONTROL Input =0: Output the DATA START signal for all blocks. Input = 1; Output the DATA START signal for only the second block. Aoeono RDS data reception in progress output Outputs a low level while serial data is being output following High lovet RECEIVE > completion of synchronization detection. Outputs a high level at ali | (high other times. impedance) Open drain output aogoat Note: * 0: Low level input 4: High level input Continued on next page a No. 4789-5/18
C7074, 7074M Continued from preceding page. [Fino Error correction operation output +> Outputs a low level when the serial data output data has been error High levet CORRECTION corrected, or could not be corrected. Outputs a high level (high (high impedance) when correction is disabled. impedance) Open drain output nooo Error output {> Outputs a low level when there were errors in the input data and High level ERROR those errors could not be corrected. Outputs a high level (high {high impedance) when there were no errors or the errors were corrected. impedance) Open drain output nozoas Yoo ‘Serial data output block data start signal DATA START The output type is controlled by the D.S.CONTROL input. High level Pull-up MOS transistor (CMOS) output aozoee Yoo Serial data output data output - DATA OUT ok Oo Pull-up MOS transistor (CMOS) output High level novoae Yoo Serial data output clock output CLOCK OUT 5 Pull-up MOS transistor (CMOS) output High level aozose Yoo Reset input input a low level pulse with a length of at least 4 clock cycles to reset RES and restart IC operation. Note that when a 4 MHz oscillator is used, since a single clock cycle is 0.25 ys, four clock cycles is 1 ps. Schmitt type input. Aeeees | Built-in pulbup resistor No, 4789-6/18
C7074, 7074M Specifications Electrical Characteristics at Ta = 25°C Vggl, Vsg2, Vgg3 = 0 V [frame] Syter|—fonteati pi [on ing a) Supply voltage [Voomax [Voo | 080 7.0 TT OSC2, DATA START, up voliage RECEIVE, CORRECTION [vi [Res.oscx fe 2 toon +08 ‘CLOCK IN, DATA IN, Input voit _ * input voltage v2 | CORA.SEL, CLEDSEL, 3015s} Vv D.S.CONTROL RECEIVE, CORRECTION, ERROR The output current per pin Output current DATA START, DATA OUT, CLOCK OUT [E10 [aout pine [Toman to | va | Allowable power dissipation —— Ta =-40 to +85°C | ew | MFP package product Up to 150 [oramgurmeawe [Ter] oes 0 [Sioragetemperawre [tg Pesto va Teo | Note: * When driving the oscillator with the recommended constants shown in figure 1, values up to the oscillation amplitude that occurs are allowed. Allowable Operating Ranges at Ta = ~40 to +85°C, Vss1, Vss2, Vsg3 = 0 V, Vpp = 4.5 to 6.0 V Peteape nn [contin Ee | [parang way votags | Von [Veg] CLOCK IN, DATA IN, Vint CORR.SEL, CL.ED.SEL, 7 Vi Input high level voltage WH | DS.CONTROL ©7o0 v [vane [ees 28 [Yoo TT CLOCK IN, DATA IN, Vt | CORR.SEL, CL.ED.SEL, Vsg 03Vp] Vv Input low level voltage DS.CONTROL [M2 [Res es TO 025 Vo ‘See the ceramic oscillator guaranteed Electrical Characteristics at Ta = -40 to +85°C, Vgg1, Vgs2, Vsg3 = 0 V, Vpp = 4.5 to 6.0 V . Symbol Anplcab| Condi seme me prea pr ereven [min Tye Tmax | CLOCK IN, DATA IN, Input high level current iW CORR.SEL, CL.ED.SEL, | VIN=+13.5V pA D.S.CONTROL CLOCK IN, DATA IN, It | CORR.SEL, CLED.SEL, | VIN= Veg pA {Input low level current D.S.CONTROL ye [RES VIN Vs [ sf TT Output high level voltage Vou, _ | DATA START, DATA OUT| IOH = -50 HA [Voo-12] Ty _ ° OH | cLock our JOH = ~10 pA [Moo-osf RECEIVE, CORRECTION | Ouputow el age vou | Eason OAK Sram poof ts Ty DATAOUT, CLock OUT | 1OL = 1.8 ma" re ee ERROR Vo=Vss [of Hysteresis voltage Vas [RESP top PO [Supny eure | tp [Yop [7 Ceramic oscitlator stabilization time OSC, Osc2 See figure 2 rr ee Note: 1 When the IOL values for the remaining output pins (when an arbitrary 4 output pins are excluded) are all under 1 mA. 2 Using the oscillator circuit in figure 1, when there is no power dissipation in the output pins, and when the input pins are at the Vp level. No. 4789-7/18
C7074, 7074M Se Ceramic Oscillator Guaranteed Constants
4 MHz ceramic oscillator c1,C2
CSA4, 0OMG (Murata Mfg. Co., Ltd.) KBA4. OM (Kyocera, Ltd.) 93 pF + 10% Yop rerre tne flennnerenennneneennees ABV, osca osce Snopoceeccsnrnceccasesnn ee OV osc Cc. ce L Ceramic a Stable oscillator tCFS oscillation ‘Oscillator unstable period Figure 1 Oscillator Circuit Figure 2 Oscillator Stabilization Period v Operation starts Yoo] Yoo oo i —_— 4.5V y RES 0.8VD0 Brceo.taF 4,425V (0,25Vopmin) This example shows a simplified Set this period to 10 ms or longer to allow for the reset circu, oscillator stabilization period. In actual applications, we recommend 400 100 ms when C -0.1 uF. Pa sca cee cetigned 90 ta However, adjust the value of C in application circuits in the control microprocessor 10 handle which the power supply has a slow rise time. cases where IC operation becomes. unstable due to power supply noise or other causes. Figure 3 Reset Circuit RDS Data Processing System Organization Example Synchronization and RDS demodulator ertor correction ‘System control Laz230 CLOCK IN [——h5o5q DATA START > Display [nara our | Lageaa BATA IN Le7074m aa eecoaing PLL control Aozova System Organization Example No, 4789-8/18
1.07074, 7074M ee System Operation 1, Relationship between RDS Demodulated Data (LA2230 series IC output) and LC7074/M Output Data , Correctable, Uncorrectable : 1 error error i : ADS demodulated y Y y ‘ ‘ DATAIN A } f A f Quip aa LT Te fed Led Lee] i 1 tetbiock | and block} ard block | "ath block ERROR i H : CORRECTION H } i DATA START i rt in rT i RECEIVE | A02089 + The DATA START signal indicated with broken tines is the signal when the O.S.CONTROL input is iow level. + The serial data output (DATA OUT) Irom the LC7074/M is data that is delayed by one block with respect to the data received rom the LA2230 series IC. + The ERROR and CORRECTION signa's are output continuously when consecutive errors are detected. + The RECEIVE output signal is output only in periods when output data is being output from the DATA OUT pin Relationship between the Demodulated Data and the Output Data cS No. 4789-9/18
C7074, 7074M 2. Input Data Timing Lc7074/74 RDS CLOCK ROS CLOCK IN demodulation ic ROS DATA pATA IN clock EN 472+¥pp ara sooongeennc == otennce ts te aozogo 1 Min, 1.0 ps 12 Max. 10.0 ys * Input data is acquired on the falling edge of the input clock, * Input data must be stable just before and just after the falling edge of the input clock. This means that itis desirable that the input data change state on the rising edge of the input clock. Input Data Timing No. 4789-10/18
C7074, 7074M eee 3. Serial Data Output Format and Timing s : Start bit (always “0") E : Error flag } See table F : Correction flag OE : Offset E OF : Offset F (always “0”: reserved for future expansion) AB : Group type version 0: Version A 1: Version B E and F Flags B1, BO : Block number 00: First block tT ETL To reaand lock cr a 10: Third block [ere eorases [9 [| 11: Fourth block [Uncoreciabi nore [1] 1] DO to D15 : RDS data Note: When the CORR.SEL input pin is high level. MSB__ Datais transmitted MSB first. The LSB is outputlast. LSB A o Data format 7] 7 B sone block ad pyre 10 msec H 11.8 msec H eee TEE sore oT 1 ULI, oe ULL rt The clock is not output for it When CL.ED.SEL is 0 section with no data. CLOCK OUT fl fl mW mn mr id When CLEDSEL is 1 DATA START a a (1) Detailed Timing for Data with a DATA START Signal H eareour a a i {— 420240usec =a CLOCK OUT t i 240220seec 210220s8ec 21~28 DATA START : i a iiv~isusec H (2) Detailed Timing for Data without a DATA START Signal H earaour a CLOCK OUT oe oe a ee oon ee | 19~23esec Serial Data Output Format and Timing No, 4789-11/18
C7074, 7074M 4, Informative Bits in the Serial Data Output * Error Flag (E) and Correction Flag (F) The error flag (E) and the correction flag (F) in the serial data output are identical to the ERROR and CORRECTION output pins, except that the logical levels are inverted. The meaning of the error and correction flags differ slightly depending on the setting that determines whether input data error correction is to be performed (the CORR.SEL pin). The tables below show the relations between the output value combinations of the error and correction flags. — When the CORR.SEL pin is high: Error correction enabled = ererag te [ —carosion tg [ERROR pn —[ Go RRECTION a —] [Newnes [etarecorected fo [Uncorrectablieerrors ft PP The value combination where E is 1 and F is 0 (or equivalently, where the ERROR pin is 0 and the CORRECTION pin is 1) cannot occur. — When the CORR.SEL pin is high: Error correction disabled retest [Coreston tn EROR pn __[__coRRECTION SR —_] [Noerore [Uncorrectable errors | The value combinations where E is 1 and F is 0 (or equivalently, where the ERROR pin is 0 and the CORRECTION pin is 1) and where E is 0 and F is 1 (or equivalently, where the ERROR pin is 1 and the CORRECTION pin is 0) cannot occur. In this case, the combination indicating no errors is output if there were no errors in the data, and the combination indicating uncorrectable errors is output when there are errors in the data whether or not those errors are correctable. * Offset E (OE) and Offset F (OF) . When the IC has synchronized with the offset word E block data, the OE bit in the output data goes to “1”. At this point the bits B1 and BO, which express the RDS block number, will be “00”, i.e., both will be zero. The LC7074/M does not recognize an offset word F block as a correct offset word. Therefore, the OF bit in the output data will always be “0”. Block pe “A” indicates offset word A, thatis, the first block. ro [>[4]@[e[>lelelelelele elelaqe Our [eJo[a|sfefolefsle[el= efelelale OE bit Bits B1 and B2 10 11 00 01 10 11 00 00 GO 00 00 00 00 00 00 o1 OE Bit Output No, 4789-12/18
C7074, 7074M * Block Number (BO and B1) The block number bits indicate the data block of the output data. [er Bock a [0 [1 second cok the osetwod bo) —SC—C—id [1 [0 Tre ok the ost word Cor book [1 [1 [Fourth btock the otiset word block) — The OE bit becomes one when the offset word E block data is output. At this point the bits B] and BO will be “00”, i.e., both will be zero. — Consider the situation where there is a block in the RDS group data output for which the input data offset word cannot be detected. Here, the IC assumes that the blocks were input in the correct offset word order, and outputs BO and B] accordingly. roa DRBOQORBBEEE ou [eJ>]a]atefola}> [2 [ofata Bits BO and B1 10 11 00 01 10 11 00 01 10 11 00 01 ww Output interred from the block order Block Number Output * Group Type Version (A/B) The A/B bit is set based on the third block offset word of input data. If the offset word is “C’”, the A/B bit is set to “0”, and if the offset word is “C’", the A/B bit is set to “1”. Note that the version bit BO in the second block (the offset word B block) data of input data is not used for group type version determination. As a result, the version bit A/B in the output data changes in the third block. rou [>[+Tefe[e[afefefo[alale] la] ouput [e[>[ajefelofafale |p] alalclo[al AB bit A/B Bit Output No. 4789-13/18
C7074, 7074M 5. Group Synchronization * Recognized Offset Words The LC7074/M recognizes the five offset words A, B, C, C’ and D. The offset word F, which is stipulated by the EBU, is not recognized. * Group Data Ordering and Synchronization The LC7074/M recognizes the following three types of group data. However, there is no limitation on the number of blocks in groups consisting of offset E blocks (type 3). (i) A-B-C-D (2) A-B-C'-D G3) E-E-E-E E-E-E E-E E As a result, there are nine block data orders (listed as (1) to (9) below) that the LC7074/M recognizes, and any other order is determined to be an error. Correct data orders Data orders handled as errors aaAnx> B ASC Q BO C BOE 3) Boa C E> B 4 C > D . 6) C > D . ©D >A . MD3> E (8) E> E O EO A The data input wait state is called a synchronization sequence. When a clock signal is first input to the LC7074/M. from the demodulation IC, the LC7074/M starts the operation of detecting offset words from data synchronized with the clock. The LC7074/M synchronizes with the input data when it detects two blocks with correct offset words in correct positions. * Synchronization with RDS Group Data — RDS block data format [> [a[[e]o[a]fc]o fas Ww Ue Block data ROS group data RDS Group Format No. 4789-14/18
C7074, 7074M — Synchronization with RDS data me PEP LTTE Pals output Delayed by 1 block \\BEPERECPEE 3 + Here the LC7074/M detects blocks D and A consecutively. Since it synchronizes at A, output starts with 6 from the same group. ual ZOO ROR + Here, the LC7074/M detects the D and B blocks. Since it synchronizes at B, output starts with A from the next group. RDS Synchronization Sequence * Synchronization with RDS/MMBS Group Data — RDS/MMBS compound group data format Type 1 (data with a single RDS group inserted) elelelelefefelaslclojelelelelele Jelelelalaic ‘Type 2 (data with two RDS groups inserted) eJeleletele[e]s[ete[o]afelclolele jelelelalaic RDS/MMBS Group Data Format — Synchronization with MMBS Data bon *Teye[elele[elelelelele ou fele[ejel=]el2[e[e + Detected for two consecutive blocks ios Te]? [ele Jelele[=[ele + Detected for nwo of three blocks Note: The LC7074/M does not recognize that MMBS group data consists of four MMBS blocks (offset word E blocks). MMBS Synchronization Sequence . we No. 4789-15/18
C7074, 7074M oo + Pull-Out When a state occurs in which the LC7074/M is in the synchronized state and cannot detect the block data offset word, it enters a pull-out sequence. When the LC7074/M is unable to detect the offset word in five consecutive blocks while in a pull-out sequence, it goes to the pull-out state. When the LC7074/M pulls out, it stops clock and data output and switches to the synchronization sequence. Note that if the LC7074/M was unable to detect the offset word in fewer than five consecutive blocks, the synchronization state continues without change. — Pull-out in RDS group data Offset word not detected for 5 consecutive blocks. Input ——_. e[ojatefeypyafefeoy eT TT Tet tle] TT TT | Output Four blocks of data and format ‘our blocks of data and error information are EO ENA NES 0 To the synchronization Note: “Error output" refers to the E and F flags in the output data ang to the ERROR and CORRECTION pins. RDS Pull-Out Sequence — Pull-out in MMBS group data Otiset word not detected for 5 consecutive blocks Input ——_— BlelelelelefefeP PPT yy Pry PTT TTT | Output Four blocks of data and error information are output. PEPEPEP ERE TTT] meester Error output ——_-» To the synchronization sequence MMBS Pull-Out Sequence a No. 4789-16/18
LC7074, 7074M ooo + CL.ED.SEL The LC7074/M reads in the state of the CL.ED.SEL pin about 1 ms after a reset clear. It uses this signal for the internal settings that determine the clock output polarity. Yoo —— RES Lt Pin readin timing ime} CL.ED.SEL x H nozose CL.ED.SEL Pin Read-In Timing + CORR.SEL and D.S.CONTROL The LC7074/M continuously checks the state of these pins. As a result, error correction can be tumed on or off and the DATA START signal output form can be changed at any time. — During synchronization detection (synchronization sequence) The pin states are read-in on each bit of demodulated data from the RDS demodulation IC (at the points shown by arrows in the figure), The state is read into the IC if the input values agree four times in a row. Demodulated data DATA IN 7 | — Clock input CLOCK IN | i Lr LSt internal state setting i A02083 Pin Read-In Timing during Synchronization Detection a No. 4789-17/18
C7074, 7074M — Following synchronization detection (while. synchronized) The LC7074/M reads in the pin state at the start of each block in the demodulated data from the RDS demodulation IC (at the points shown by arrows in the figure). The state is read into the IC if the input values agree four times in a row. Block data Demodulated data blocks DATA IN LSlinternat state setting _ aoz0a4 Pin Read-In Timing following Synchronization Detection WM No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property toss. HM Anyone purchasing any products described or contained herein for an above-mentioned use shall: @® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO,, LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO. LTD,, its affiliates, subsidiaries’ and distributors or any of their officers and employees jointly or severally. @ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production, SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties, No. 4789-18/18