LC680100A SANYO | Alldatasheet
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Technical content
Features
(1) CPU core :32 bit RISC (Speed: 15MHz, Instruction cycle time: 67ns) (2) High Speed Multiplier :16bit x 16bit (in 1 instruction cycle) (3) Instruction cache RAM :2kB (512x32bit) (4) Data RAM :2kB (512x32bit) (5) DRAM Control Unit (6) External memory bus control unit (7) I/O port :One 16 bit I/O port, one 8 bit I/O port (8) UART :Two full duplex asynchronous channels (one channel has 16bit FIFO) (9) Serial I/O :One three-wire synchronous clock, 8 bit (10) Timer :4 channels (TM0 = 16bit + 16bit) (TM1, TM2, TM3 = 8bit + 8bit) (11) PWM Output :Three 8 bit resolution outputs (Common with TM1, TM2, TM3) (12) Interrupt controller :13 source events (5 internal, 8 external), 5 vectored (13) OSC circuit :Two types: main and RC. VCO/PLL is built-in, frequency multiplication possible. (14) Standby :Standby (HOLD) and sleep (HALT) modes available (15) VDD :3.3V typ. Package and Pins SQFP100, 100 pins Development tools A C compiler, assembler and emulator are available to be run on a PC. 32-Bit RISC Microcontroller LC680100A Ordering number : ENN*6830 CMOS IC
No.6830-2/16 System Block Diagram 32bit RISC CORE Special Function Register SFR Bus Control DRAM Control Data RAM (2k bytes) Instruction Cache (2k bytes) Interrupt enable control Coprocessor (Multiplier) Mode Control Reset Control RC OSC Multiplier Circuit Main OSC System Clock, Standby Control Interrupt Control Timer 0 Timer 1 Timer 2 Timer 3 SIO0 UART0 UART1 Port 0 Port 1 Instruction Cache Control Bus Control SIO0 UART0 UART1 TM0H TM0L TM1H TM2H TM3H Figure 1 LC680100A System Block Diagram
No.6830-3/16 Terminal Assignment Diagram (SQFP100, 0.5mm pitch) 1 2 3 4 5 6 7 8 91 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 5 26 57 56 55 54 53 52 5160 59 5867 66 65 64 63 6270 69 68 6175 74 73 72 71 100 VDD CK1 CK2 VSS CMP VDD CKOT CKIN VSS PHIOT HOLDI RESET MODE TEST VDD P00/TXD0 P01/RXD0 P02/SDO P03/SDI P04/SCK P05/PWM0 P06/PWM1 P07/T0IN/INT0 VSS P08/INT1 P09/INT2 P0A/INT3 P0B/PWM2 P0C/TXD1 P0D/RXD1 P0E P0F NMI P10/BGNT P11/RAS P12/CASU P13/CASL P14/DMXS P15/RFREQ P16/IRQOT P17/MCLK/HOLDO VDD VSS A0/LBS A10 VDD A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25/CS5 A26/CS4 A27/CS3 VSS VDD D10 D11 D12 D13 D14 D15 VSS CS0 CS1 CS2 CS6 RD WRU/UBS WRL/WR WAIT BREQ LC680100A Package Dimension (unit : mm) 3181B SANYO : SQFP-100
No.6830-4/16 Terminal Functions Note: PU = pull-up Pin Number Pin Name I/O Function Description Pin Format 1,6,15,34,55 ,82 VDD - Power supply +ve - 4,9,24,43,73 ,91 VSS - Power supply -ve -
2 CK1 I Input to main oscillator Schmitt Input
3 CK2 O Output from main oscillator CMOS output
5 CMP I/O Phase comparator filter pin (multiplier circuit). Schmitt InputTristate output
7 CKOT O CK1 or half frequency clock output from multiplier CMOS output
8 CKIN I External clock input Schmitt Input
10 PHIOT O System clock output CMOS output
11 HOLDI I HOLD request input Schmitt Input
12 RESET I Reset terminal Schmitt Input
13 MODE I Bus mode setting at reset Schmitt Input
14 TEST I Test input (Normally connected to VSS) Schmitt Input
16 P00/TXD0 I/O PORT0 bit0 I/O. Also UART0 send 17 P01/RXD0 I/O PORT0 bit1 I/O. Also UART0 receive 18 P02/SDO I/O PORT0 bit2 I/O. Also SIO0 data out 19 P03/SDI I/O PORT0 bit3 I/O. Also SIO0 data in 20 P04/SCK I/O PORT0 bit4 I/O. Also SIO0 clock 21 P05/PWM0 I/O PORT0 bit5 I/O. Also PWM0 output 22 P06/PWM1 I/O PORT0 bit6 I/O. Also PWM1 output 23 P07/T0IN/INT0 I/O PORT0 bit7 I/O. Timer0 event input INT0 input 25 P08/INT1 I/O PORT0 bit8 I/O. INT1 input 26 P09/INT2 I/O PORT0 bit9 I/O. INT2 input 27 P0A/INT3 I/O PORT0 bit10 I/O. INT3 input 28 P0B/PWM2 I/O PORT0 bit11 I/O. PWM2 output 29 P0C/TXD1 I/O PORT0 bit12 I/O. UART1 send 30 P0D/RXD1 I/O PORT0 bit13 I/O. UART1 receive 31 P0E I/O PORT0 bit14 I/O. P0F I/O PORT0 bit15 I/O. Used as input: Schmitt Input; presence of PU resistor software selectable. Used as Output: CMOS/N-ch OD mode software selectable.
No.6830-5/16 Pin Number Pin Name I/O Function Description Pin Format
33 NMI I NMI interrupt Schmitt Input
35 P10/BGNT I/O PORT1 bit0 input. Also bus grant output. 36 P11/RAS I/O PORT1 bit1 input. Also DRAM control RAS signal out. 37 P12/CASU I/O PORT1 bit2 input. Also DRAM control CASU signal out. 38 P13/CASL I/O PORT1 bit3 input. Also DRAM control CASL signal out. 39 P14/DMXS I/O PORT1 bit4 input. Also DRAM control DMXS signal out. Schmitt InputTristate output 40 P15/RFREQ I/O PORT1 bit5 input. Also DRAM control RFREQ I/O. Schmitt InputPU Output P16/IRQOT I/O PORT1 bit6 input. Also IRQOT output. 42 P17/MCLK/HOLD0 I/O PORT1 bit7 input. MCLK output, HOLD state output Schmitt InputTristate output
44 A0/LBS I/O Bus Address bit0 or
Lower byte strobe signal. 45 to 54, 56 to 69 A1to A24 I/O Bus Address bit1 to 24. 70 A25/CS5 I/O Bus Address bit25 or CS5.
71 A26/CS4 I/O Bus Address bit26 or CS4
72 A27/CS3 I/O Bus Address bit27 or CS3. Schmitt InputTristate output 74 to 81, 83 to 90 D0 to D15 I/O Bus data bit0 to 15 Schmitt InputTristate output
92 CS0 I/O CS0
93 CS1 I/O CS1
94 CS2 I/O CS2
95 CS6 I/O CS6
Schmitt InputTristate output 96 RD I/O Bus read signal. 97 WRU/UBS I/O Upper byte write signal or Upper byte strobe. 98 WRL/WR I/O Upper byte write signal or Write. Schmitt InputTristate output
99 WAIT I/O Bus cycle wait Schmitt InputPU
100 BREQ I Bus request. Schmitt Input
No.6830-6/16 1. Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Symbol Pins Conditions Ratings Unit Supply voltage VDDmax VDD Note1 -0.3 to +4.6 V Input voltage VI(1) Pins for each input only -0.3 to VDD+0.3 V Output voltage VO(1) Pins for each output only -0.3 to VDD+0.3 V Input/Output voltage VIO(1) Pins for both input and output -0.3 to VDD+0.3 V High level peak output current IOPH(1) Each output pin Current at each pin -5 mA ∑ IOAH(1) P00 to P08 Total of 9 pins -80 mA High level total output current ∑ IOAH(2) P09 to P0F Total of 7 pins -80 mA Low level peak output current IOPL(1) Each output pin Current at each pin 20 mA ∑ IOAL(1) P00 to P07 Total of 8 pins 80 mA Low level total output current ∑ IOAL(2) P08 to P0F Total of 8 pins 80 mA Maximum power consumption Pdmax SQFP100 Note2 Ta = -20 to 70°C 440 mW Operating temperature range Topg -20 to +70 °C Storage temperature range Tstg -55 to +125 °C Note1:All VDD terminals (pin1, 6, 15, 34, 55, 82) should be connected externally. All VSS terminals (pin4, 9, 24, 43, 73, 91) should be connected externally. Note2:Reflow method is recommended when soldering the SQFP package.
No.6830-7/16 2. Recommended Operating Range at Ta = -20 to 70°C, VSS = 0V Ratings Parameter Symbol Pins Conditions Min. Typ. Max. Unit Operating supply voltage range VDD (1) VDD 3.0 3.3 3.6 V Supply voltage (Memory hold) VHD VDD Keep RAM and Register data in Standby mode. 2.5 3.6 V VIH(1) Input pins except CK1 0.7VDD VDD High level input voltage VIH(2) CK1 0.7VDD VDD V VIL(1) Input pins except CK1 VSS 0.3VDD Low level input voltage VIL(2) CK1 VSS 0.3VDD V tCYC(1) CKIN 300K to 15MHz 66 3333 Operation cycle time tCYC(2) CK1 400K to 15MHz (VCO is not used.) 132 5000 ns fEXCKIN CKIN Figure 1 300k 15M External system clock frequency fEXCK1 CK1 Figure 1 400k 15M Hz tCKINL tCKINH CKIN Figure 1 28 External clock pulse width tCK1L tCK1H CK1 Figure 1 28 ns External clock rising and falling time tEXR tEXF CKIN, CK1 Figure 1 5 ns Operation frequency range fCK1 CK1, CK2 Figure 2, Table 1 400k 8M Hz
No.6830-8/16 3. Electrical Characteristics at Ta = -20 to 70°C, VSS = 0V, VDD = 3.0 to 3.6V Ratings Parameter Symbol Pins Conditions Min. Typ. Max. Unit IIH(1) Pins for each input only VIN = VDD 5 High level input current IIH(2) Pins for both input and output VIN = VDD Output disabled 5 µA IIL(1) Pins for each input only VIN = VSS -5 IIL(2) P15/ RFREQ,WAIT VIN = VSS Output disabled -5 Low level input current IIL(3) Input/output commonly terminals except written above VIN = VSS Output disabled -5 µA VOH(1) Port0 with PU option, P15/RFREQ IOH = -0.05mA VDD-0.5 High level output voltage VOH(2) Input/output commonly terminals except written above, CKOT, PHIOT IOH = -1mA VDD-0.5 V VOL(1) Pins for each output only IOL = 4mA 0.4 Low level output voltage VOL(2) Pins for both input and output IOL = 4mA 0.4 V PU resistor rPU Port0 with PU option, P15/RFREQ 1K 20K Ω Hysterisis voltage vHIS Each input only, I/O terminal 0.1 VDD NMI 2 External interrupt pulse width tINTL tINTH INT0 to INT3 Figure 4 4 Tcyc Reset input pulse width tRESL RESET Figure 4 2 ms VCO frequency fVCO CKOT Figure 5 4M 16M Hz VCO lock-up time tLOCK CMP,CKOT Figure 5, cCMP = 0.1µF 10 ms RC oscillation frequency fRC Built-in RC oscillation circuit 300k 1M Hz Ceramic oscillation stabilizing time tCF CK1,CK2 Figure 3 10 ms Current consumption in run mode IDDRUN VDD CKIN=15MHz 60 120 mA Current consumption in sleep mode IDDSLP VDD 50 100 mA Current consumption in standby mode IDDSTY VDD 10 200 µA Pin capacitance cP All pins 10 PF
No.6830-9/16 4. Serial Input/Output Characteristics at Ta = -20 to 70°C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure 14 Ratings Parameter Symbol Pins Conditions Min. Typ. Max. Unit Input clock cycle time tSCK SCK input Figure 6 16 Tcyc Input clock L pulse width tSCKL SCK input Figure 6 533 ns Input clock H pulse width tSCKH SCK input Figure 6 533 ns Output clock cycle time tSCKO SCK output Figure 6 16 Tcyc Output clock L pulse width tSCKOL SCK output Figure 6 8 Tcyc Output clock H pulse width tSCKOH SCK output Figure 6 8 Tcyc Input data set up time tsDI SCK, SDI Figure 6 200 ns Input data hold time thDI SCK, SDI Figure 6 50 ns Output delay time tdDO SCK, SDO Figure 6 100 130 ns
- DRAM Timing at Ta = -20 to 70°C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure 14
Table 1. Guaranteed Value for the Ceramic Oscillators
No.6830-12/16 VCO 1/2 VCOSW 0.5VDD 0.8VDD 0.2VDD CMP CKOT CK1 CK2 C1 VDD CK2 CK2 CKIN CK1 cCMP tINTL tRESL tINTH tCF 1/fEXCKIN or 1/fEXCK1 tCKINL or tCK1L tCKINH or tCK1H External Input External Input Figure2 Ceramic Oscillation Figure3 Oscillation Stabilizing Time Stabilized oscillation Figure5 VCO VDD lowest limit Oscillator Figure4 External Pulse Input Phase Compare Figure1 External Clock Input 0.5VDD tSCKL OR tSCKOL tSCKH OR tSCKOH tSCK or tSCKO thDI tsDI tdDO SDI SDO SCK 0.5VDD 0.5VDD Figure6 Serial Input/Output Timing
No.6830-13/16 Figure7 External Bus Read Timing Figure8 External Bus Write Timing
No.6830-14/16 Figure9 DRAM Read Timing Figure10 DRAM Write Timing
No.6830-15/16 Figure11 REREQ Input/Output Timing Figure12 Bus Request/Release Timing Figure13 Wait Input/Output Timing Figure14 The Load Used in Measuring the Timing
No.6830-16/16 PS