LC66354B

LC66506B SANYO | Alldatasheet

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Features

(1) On-chip 6K-byte/8K-byte ROM, 512x4-bit RAM {2) instruction set with 127 instructions extended from that of the LC6500 series (3) 1/0 ports ----- 58 pins (4) 8-bit serial interface ----- 2 lines (16-bit cascade connection available) (5) Minimum instruction cycle time ----- 0.92, (4.3MHz external clock input mode) {6) Powerful timer function and prescaler 12-bit timer-used interval timer, event counter, pulse width measurement, burst pulse output B-bit timer-used interval timer, event counter, PWM output, burst pulse output 12-bit prescaler-used time base function (7) Powerful 11-source 8-vector interrupt function External interrupt: 6 sources, 3 vector addresses Internal interrupt: 5 sources, 5 vector addresses (timer: 2 sources, serial !/O: 2 sources, prescaler) (8) Flexible 1/0 function Comparator input, 3-level input, 20mA drive output, 15V breakdown voltage, pull-up/open drain selectable by option (9) Runaway detection function (option) (10) 8-bit input/output function (11) HALT/HOLD mode-used power-down function (12) Package: DIP64S, QFP64A (QIP64A) . . (13) Evaluation LSI: LC66599 (evaluation chip) + EVA850/800-TB665XX, LCB6PG5XX (piggyback) LC66E516 microcontroller with built-in EPROM, LC66P516 microcontroller with built-in one-time programmable ROM. Note: The LC66506B, 66508B are different from the LAG6506A, 66508A in the external constants for RC Series Lineup Type No. Pins | ROM capacity Package Remark | capacity L.C66304A/306A/308A 4K/6K/BKB S12W | Lceessas/as6s/sses | 44 | 4K/6K/6KB 512 LC66E308 42,48 | EPROM BKB | s12W | DIC42s, QFCas Available | with window [ucéersog_— 42.4 ToTPROMBKB | S12W | DiP42s OFPasE | Available 4K/6K/BKB [S12W Available with window jcesraog_ a2. ag [oTPROMBKB "| “SiaW [DiPa2S, OFPABE | Available | | LC66506B/508B/5128/6168 |" 64_| GK/BK/12K/16KB_| 512W__| DIPG4S, QFPE4A | Available 64 [6kaK/i2KneKe | 612W | DIP64S, QFPE4E | Available 42,48 | akieKiske | 612W | DIP42S,QFPABE [Available | Lesessépyssea | 64 | Kak | 5 12W | D1P64S, OF PG4E [Leees62B/6668 4 12K eKB |S 12W_| DiP64S, OF PE4E LO66E516 EPROM 16KB DICé4S, QFCE4 Availabl il ca [iceerst6 | ba orpRomieks | si2w [oireas arr6ae [Available SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 92293JN A8-9226 KAWA/2222JN/6099YT/4288TA,TS No. 2796-1/25

LC665068,66508B _—S SSS Package Dimensions 3071 Pin Assignment DIP64S. (unit: mm) 6% EY j sio/p20 LO [64) Vo wi soo/P21 2] [3] P13 es $OKO/P22 eal ar wro/p23 Fa] fer Pt | -® inti/e30 Fe] | fray P10 DUTTTUUTDTODOT TOUT TUDOMOOT TOOT: Pouto/P3t Ce] [53] Po3 ry PoUTI/P32 [58) Po2 7 $7.2 Q OLD /P33 CB] [57] Poi ce | P40 [3] [56) Poo

3 AT PP pai Fit] HS) peatra

! ‘ao u it Pa2 [i] [54) Peo/TRa mi P43 [12] [53] PD3/CMP3

095 O48 178 SANYO: DIP64S P50 [32] Po2/ome2

psi (ia) [51] Po1/emPy 82 05 LC66506B ‘[50) Poo/cmpo P53 [43] PC3/VREFI si1/p6o 7] 66508B fam Pcz-vrero so1es? [16] Pet ScKT/P6z [3} [46] Pco PINT/P63 [45] Pas 70 (21) [44] Paz Pr [a3] pat P72 [23] [42] pao P73 (28) [4J pag P80 [25] [40] PA2 per (26) Par p82 [27] [38] PAO ___ P83 [28] {32} P93/iINTS. . inT2/P90 [23] P92/ NTA test 0] {35} P91/iNTS Vs [34) RES ose! (32) [33] osc2 Package Dimensions 3057 Pin Assignment {unit: mm) Qipes " C_o- 8g . 0.8 035 ZEES SE. pee ee ee 2: FD AAON NADIA | PEGE RES S255 aR EE POAT TA TAAL ( Pet ok ick cht Eee 64 63 &2 61 60 59 58 57 85 5 54 53 $2 51 $0 69 —— —— = el 4800 == == =] pace a7C]PeV TAS = ==> = part] 3 se] PEO/TRA == =— = pastja «s[]P03/omP3 —— == = esol eap02/omee = == = eats «aC]P01 omer 2g == = = peel]? «2]P00/emPo —— = = pate aiQ)pcavaert == eS = si/p60 29 LC66506B, 66508B pPjeca/vacro —— = = sot/P61 E10 setect =| == FY +scxr/ese Qin 38G}°co — ee 7 Pint /P63 C12 a0)Pa3 AMT ET. Q pms siieee enge 8 TUTTLE ULE eae mE }>80 : pte a0)Pa3 SANYO: QFP64A, 245 ‘U7 18 19 20 21 22 23 24 25 26 27 28 29: 3 32 (alp6sa) OOOO CHHIOOOO HO SESPEEEROL EP SEY SERRE RS REBEL ER az £ L238 H gee Note) Reflow soldering is recommended for QFP {QIP) packages. gf Please consult your local representative for information on solder-bath immersion of the device. No.2796-2/25

LC66506B,66508B System Block Diagram rad RAM STACK nom Ww) (6K/8K) vest 1 FLAG SYSTEM u ose1 CONTROL fi iii wee le] +] RIHLI|XY - fr 6 TL i ifi jf¢-—_- PouTO TRA D RIAL 1/0 0 $50 PO cue = re eee ee cue? on im ome “et INTE, (NTS inn INTERRUPT si SCKI ip ig—— it PIN, POUT! re it y Gia eS No.2796-3/25

LC66506B,66508B Pin Description . Panne [ve [fonts | coro [ont [ouan in POO 1/0 | input/output common port POO | *Pch: Pu MOS type +With Pu MOS | H or L Pow to PO3 *Nch: Small sink or Nch OD {option} P02 + 4-bit and single-bit input/out- current type output | PO3 put -Output level * P00 to P03: Provided with during reset HALT mode control function P10 1/0 | Input/output common port P10 | *Pch: Pu MOS type «With Pu MOS | HorL Pit to P13 *Nch: Small sink or Nch OD {option) P12 +4-bit and signle-bit input/out- current type output P13 put + Output level during reset P20/SI0 0 Input/output common port P20 | *Pch: CMOS type +CMOS or P21/SO0 to P23 *Nch: Small sink Nch OD out- P22/SCKO +4-bit and single-bit input/out- current type put P23/INTO put *+15V breakdown +P20: Common with serial input | voltage at Nch OD SIO configuration +P21: Common with serial out- put SOO +P22: Common with serial clock SCKO +P23: Common with INTO interrupt and timer O-used event count, pulse width Measurement input P30/INTT 1/0 | Input/output common port P30 | +Pch: CMOS type +CMOS or P31/POUTO to P32 *Nch: Small sink Nch OD out- P32/POUT1 +3-bit and single-bit input/out- current type put put ++15 breakdown +P30: Common with INT1 voltage at Nch OD interrupt request configuration + P31: Common with burst pulse output from timer 0 + P32: Common with burst pulse output, PWM output from. timer 1 P33/HOLD HOLD mode control input +The HOLD mode is entered by executing the HOLD instruc- tion at HOLD=L. +The CPU is restarted by setting the HOLD to H level at the HOLD mode. « Usable as input port P33 with P30 to P32 + Even if the RES is brought to L level when the P33/HOLD is at L level, the CPU is not reset. So this pin must be H level when Vpp has risen to a point where the CPU can operate properly. Continued on next page. No.2796-4/25

LC66506B,66508B Continued from preceding page. ed P40 1/0 | input/output port P40 to P43 *Pch: Pu MOS type «With Pu MOS P41 + 4-bit and single-bit input/out- | *Nch: Small sink or Nch OD P42 put current type output P43 +8-bit input/output with P50 to P53 +8-bit output of ROM data with P5O to P53 P50 1/0 | Input/output port P50 to P53 +Pch: Pu MOS type -With Pu MOS | H P51 +4-bit and single-bit input/out- | »Nch: Small sink or Nch OD P52 put current type output P53 +8-bit input/output with P40 to P43 +8-bit output of ROM data with P40 to P43 P6O/SI1 1/0 | Input/output common port P60 | +Pch: CMOS type +CMOS or H P61/SO1 to P63 +Neh: Small sink Nch OD out- P62/SCKI + 4-bit and single-bit input/out- current type put P63/PIN1 put ++15V breakdown +P60: Common with serial input| voltage at Nch OD sit configuration +P61: Common with serial out- put SO1 +P62: Common with serial clock SCK1 +P63: Common with event counter input of timer 1 P70 Output-only port P70 to P73 +Pch: Pu MOS type -With Pu MOS P71 +4-bit and single-bit output +Nch: Medium sink or Nch OD P72 + When an input Instruction is current type output P73 executed, the contents of the | -+15V breakdown output latch are input. voltage at Nch OD configuration P8e Output-only port P80 to P83 +Pch: CMOS type »CMOS or Pech | Hor L P81 +4-bit and single-bit output +Nch: Small sink OD output (option) P82 «When an input instruction is current type -Output level P83 executed, the contents of the during reset output latch are input. +Pch OD output option avail- able POO/INT2 (/O | Input/output common port P90 | - Pch: CMOS type *CMOS or H P91/INTS to P93 *Neh: Small sink Neh OD out- Pgz/INTS + 4-bit and single-bit input/out- current type put P93/INTS put P90: Common with INT2 interrupt request +P91: Common with INTS interrupt request +P92: Common with INT4 interrupt request +P93: Common with INTS interrupt request Continued on next page. No.2796-5/25

LC66506B,66508B Continued from preceding page. Prine [10 | femew | woe ton [ovat PAO Output-only port PAO to PA3 *Pch: Pu MOS type “With Pu MOS PAI *4-bit and single-bit output *Nch: Medium sink or Nch OD PA2 *When an input instruction is current type output PAZ executed, the contents of the | *+15V breakdown output latch are input. voltage at Nch OD configuration PBO Le) Output-only port PBO to PB3 *Pch: Pu MOS type *With Pu MOS PBI *4-bit and single-bit output *Nch: Medium sink or Nch OD PB2 +When an input instruction is current type output PB3 executed, the contents of the output latch are input. PCO 1/0 Input/output common port PCO | -Pch: CMOS type *CMOS or Pct to PC3 *Nch: Small sink Nch OD out- PC2/VREFO + 4-bit and single-bit input/out- current type put PC3/VREF1 put *PC2: Common with VREFO comparator comparison voltage pin *PC3: Common with VREF1 comparator comparison voltage pin PDO/CMPO Input-only port PDO to PD3 Normal input PD1/CMP1 +The comparator input is soft- PD2/CMP2 ware-selectable. PD3/CMP3 The comparison voltage of PDO is VREFO. The comparison voltage of PD1 to PD3 is VREF1. The comparator is specified in units of PDO,PD1, (PD2, PD3). PEO/TRA Input-only port PE1/TRB *The 3-level input port is soft- ware-selectable. Osc1 Pins for externally connecting *Ceramic osc2 R, C or a ceramic resonator for resonator system clock generation. OSC, RC For the external clock mode, the OSC, or ex- OSC2 pin is left open and the ternal clock OSC1 pin is used for input. System reset input pin + When the RES is brought to L level at P33/HOLD=H, the CPU is initialized. , TEST CPU test pin Connected to Vgg at the operat- ing mode VDD Power supply pins vss No.2796-6/25

LC66506B,66508B User Options (1) Options of ports 0, 1, 8 output level during reset For input/output ports 0, 1, 8, either of the following two output levels may be selected in a group of 4 bits during reset by option. 1, Output during reset: “"H” level All of 4 bits of ports 0, 1,8 2. Output during reset: “L” level All of 4 bits of ports 0,1, 8 (2) Oscillator Circuit Options 1. External * Input: Schmitt type clock sel an 2. 2-pin RC » Input: Schmitt type osc ose! C “od Fie 4 Ren > 3. Ceramic resonator closet osc H Ceramic 5 resonator | osc2 (3) Watchdog timer option The presence or absence of the runaway detection function (watchdog timer) may be selected by option. No.2796-7/25

LC66506B,66508B (4) Options of port output configuration i) For each port of PO, P1, P2, P3 (except P33/HOLD), P4, P5, P6, P7, P9, PA, PB, PC, either of the following two output configurations may be selected by option {in bit units). 1. Open drain P7, PA, PB: Output only type output P2, P3, P6, P9: Schmitt input Output data Input data ose 2. Output with P7, PA, PB: Output only pull-up Output data | P2, P3, P6, P9: Schmitt input resistance CMOS output (P2, P3, P6, P9, PC) or Pu MOS output (PO, P1, P4, P5, P7, PA, PB) | is selected according to Pch Tr drive Input data) capacity. ose ii) For P8, either of the two options may be selected (in bit units). Option Name Circuit Conditions, etc. 1. Open drain | output | J Outpt data L DSB 2. Output with pull-down o. a resistance ae] jutput deta | ake DsB iii) The comparator input of PD and the 3-level input of PE are software-selectable. No.2796-8/25

LC66506B,66508B —).7 SSS (1) Absolute Maximum Ratings at Ta=25°C, Vgs=0V [Perr [Syst [ avai Rema | __Contans [Unie on [Wo | WWekse™S" [yoo mae [Yoo Tao | VY eae eens a via) fomerinpute | 0 ttov00+0.3 Output Voltage |Vout(1) | P2,P3(except P33/HOLD), —0.3t0+15.0 | Vv P6P7,PA | Your) Output Current {!on(1) PO,P1,P2,P3(except P33/ per Pin HOLD),P4,P5,P6,P8,P9, PC jrowte)_ereare ma | —lor(1) PO,P1,P4,P5,P7,PA, 2 | mA PB —lor(2) P2,P3(except P33/HOLD), mA 4 P6,P8,P8,PC Total Pin Current | S1on(1) | P2,P3(except P33/HOLD), % | mA | 3 P4,P5,P6,P7,P8 ime [rem TT ‘ —Zlop(!) | P2,P3texcept P33/HOLD), 25 | mA 4 P4,P5,P6,P7,P8 aie prerrr : mice [ mw [S| i [Wertpiawre [tste Por (Note 1) Applicable only when the open drain output type is selected. If other type than the open drain output is selected, the specification indicated in the column for other pins applies. (Note 2) For OSC input/output, up to self OSC level is allowable. (Note 3) Sink current (applicable to P8 only when the CMOS output type is selected) (Note 4) Source current {applicable to pins other than P8 only when the pull-up output type or CMOS output type is selected) (Note 5) Reflow soldering is recommended for QFP packages. Please consult your local representative for information on solder-bath immersion of the device. {2) Allowable Operating Conditions at Ta=—30 to +70°C, Vgs=0V unless otherwise specified cable Pins _ oot) [Serato vows von [veo] ST Cid no 0 feo pL | Data Retention | VOO(H) | Vop. HOLD mode 1.8 Vv Voltage “H"-Level ViH(1) | P2,P3(except P33/ | Output Nch Tr OFF | 4.06.0} 0.75V00 vid Input Voltage HOLD), Pe Vin(2) | P33/HOLD,P9, Output Neh Tr OFF | 4.0t06.0} 0.75V00 v {2 RES osci ViH(3) | PO,P1,P4,P5,PC, Output Neh Tr OFF | 4.0to6.0} 0.2V0o oo Vv PD,PE [Wie fre inertness [Coe bose Le Continued on next page. SSS No.2796-9/25

LC665068,66508B Continued from preceding page. Symbol Applicable Pins Unit “M-Level Input | VIM S-level input mode | 4.0to6.0| 0.4Voo 0.6Vo0 | Vv Voltage Range mode “L"-Level input j Vit (1) P2,P3(except P33/ | Output Nch Tr OFF | 4 Qto6.0} VSS 0.25Voo | V Voltage HOLD), P6,P9, RES osc1 vit) P33/HOLD 1.8 Vss 0.25Vvoo | Vv 106.0 vi(3) PO,P1,P4,P5,PC, |OutputNch TrOFF /4.0to§.0| Vss 0.3Vvo0 | Vv |3 PD, PE, TEST Vale _[ve [Zinctineatmon [coe6 | ves |_| 0ave0 |v |_| Operating for 4.0106 .0 0.4 4.35 MHz Uinstruction | (TCYC) a) (0.92) | (us) Cycle Time) is used for input and ithe OSC2 is left * open, {OSC option: g External clock input) é Pulse Width | text See Fig. 1. The OSC1] ¢.0t06.0) 70 ns . text is used for input and z the OSC2 is left x ‘open. {OSC option:

3 External clock input

E|Rise/Fal | tex See Fig, 1. The OSC1/4 0106.0 30 ns | Time text is used for input and ut the OSC2 is left open. {OSC option: External clock input)| «| gsc for OSCI, OSC2 MHz | 4.0t06.0 Mrz ‘| QjFrequency 8 ee losc ters, Fig. 3 4Mbz | 4.0t06.0 10 ms @ | Eg} Stabitizing 3 |82 perioa 3 “ee =e see | [el fel Constants 7 for Ac osc_|Rext 2. kQ (Note 1) Applicable to pins of open drain type. For P33/HOLD, VIH(2) applies. P2, P3, P6 of CMOS output type cannot be used as input pin. (Note 2) Applicable to pins of open drain type. P9 of CMOS output type cannot be used as input pin. (Note 3) When PE is used for 3-level input, VIH(4), VIM, VIL(4) apply. PC of CMOS output type cannot be used as input pin. No.2796-10/25

LC66506B,66508B (3) Electrical Characteristics at Ta=—30 to +70°C, Vgg=0V unless otherwise specified Symbol | Applicable Pins J remae _| ar | ern au ee a |F "H"-Level Input | 1H (1) P2,P3 (except P33/- | ViIN=13.5V 4.0106.0 5.0 uA Current HOLD), P6 Output Neh Tr OFF M(2) Po, P1, P4,P5,P9, | VIN=VOD 4.0t06.0 uA | Pc, OSC1, RES, Output Neh Tr OFF P33/HOLD {except PD, PE, PC2, PC3) (3) PD, PE, PC2, PC3 Vin=Vod 4.0t06.0 1.0 HA Output Neh Tr OFF "UteLevel Input | liu (1) Inputs other than — | VIN=V/SS 4.0t06.0] —1.0 up |2 Current PD, PE, PC2, PC3 Output Neh Tr OFF We(2) PC2, PC3, PD, PE Vin=Vss 4.0t06.0 ub \\2 Output Noh Tr OFF “H"-Level Output | VOH(1) | P2, P3 (except P33/ |!OH=—1MA | 4.0t06.0 [vorrof v Voltage HOLD), P6, P8, P9, vont) [ro.et,pa.es.e7, liow=—200ua [| 46 | 24 [| |v |, PA, PB ToH=—130uA _[4.5t05.5[Voo—1.35] | | CV Output Pull-up PO,P1,P4,P5,P7, | ViN=VSS mA Current PA, PB “U-Level Output] VOL(!) | po, P1,P2,P3,P4, |IOL=1.6mA 4.0t06.0 0.4 Vv Voltage P5, PG, PB, PO, PC {except P33/HOLD) Output OFF-State [lore(1) | P2,P3,P6,P7,PA | ViN=13.5V 4.0106.0 ee ee Leakage Current lioce(2) [(Except P2,P3,P6, | VIN=VOD 4.0%06.0 uA P7, P8, PA) er ~ al ‘Comparator Offset | VOFF Vin=1.0V 4.0106.0 +50 +300 | mv Voltage toVOO—1.5V Hysteresis IViyyg "| P2, P3, RES,P6, Po, 4.0108.0 0.1Vo00 Vv | Vote OSC1 (RC, EXT) 5 “HLevel [Vt H 0.5V00 0.75Vvoo | V g Threshold B | Voltage g wUttevel = [VIL 0.25Voo 0.5voo | V § | Threshold Voltage Frequency C=100F + 5% R=2.7kKQE 19 Continued on next page. No.2796-11/25

LC66506B,66508B Continued from preceding page. Symbol | Applicable Pins Unit Cycle Timing of Fig. 5 and] 4.0:06.0| 0.9 us oa) gyre tCKL 4.0106.0 us 8 | Level 3 | Pulse 3 t : Rise/ tCKR 4.0t06.0 0.1 us Fall g Time | 8 licker Data Setup | tick sl0, SI1 Timing of Fig. 5, 4.0t06.0 0.3 us Time | specified for H ‘SCKO, SCKT rise Data Hold TCKI (ty 4.0106.0} 0.3 us Time Output Delay | tCKO | $00, $01 Timing of Fig. 5 and|4.0t06.0| T 03 | #8 Time test load of Fig. 6 specified for SCKO, ‘SCRT fall ($) | | i srrreerere Fig.7,| ° condition under : ee ke tod INTO 19.7) ° Which the INTO. | 4:0t06-0 2 Teye | ee toe interrupt is & | Width at accepted 2 | Into * Condition under 2 which the event 8 ‘counter/pulse 8 width measure 5 input by timer < O is accepted B | interrupt Yi INT?, INTZ + Condition under Teye ee lta INTS, INTA which each ivel False INT interrupt is Other than accepted INTO mH (tPIN | PINT * Condition under 2 Tove Level Pulse | tine which the event Width at counter input PINT by timer 1 is accepted ia TRSH * Condition under 3 Tove Level Pulse | pace which a reset Width at is coused RES ‘Comparator TRS 4,006.0 30 “Ss Response Time Current Ipp op =| Vpp 4MHz ceramic 4.0t06.0 4.5 mA Dissipation at resonator OSC Operating Mode MHz external 1 mA clock ee Continued on next page. No.2796-12/25

LC66506B,66508B Continued from preceding page. Symbol | Applicable Pins Unit Current IDDHALT | VOD 4MHz ceramic 4.0106.0 1.0 2.5 mA Dissipation at resonator OSC ee ee ‘Current IDDHOLO HOLD Mode {Note 1) The input/output common ports are of open drain output type with output transistor OFF. When the CMOS output type is selected, the input/output common ports cannot be used as the input pins. (Note 2) The input/output common ports are of open drain output type with output transistor OFF. The specifi- cation for pull-up output type is specified by output pull-up current IPO. When CMOS output type is selected, the input/output common ports cannot be used as the input pins. {Note 3) CMOS output type and output Nch transistor OFF (The open drain type can be also selected for P8.) (Note 4) Pull-up output type and output Nch transistor OFF. (Note 5) P8 is of CMOS output type. (Note 6) Open drain output type and output Nch transistor OFF. (Note 7) Open drain output type and output Pch transistor OFF. (Note 8) Reset mode. ee 7) oe oo + e+ 222+ 0,75V00 osc1 (osc2) External clock — OPEN onasyen L_ teat tex enh 1ext Fig. 1 External Clock Input Waveform Voo wine eof eee ee eee ns 22 ---+ Lower limit of operating VOD oso1 ose2 | cee ee eee eee eee OV qo osc coremi EXO C1 rotor 7 C2 resonator | unaabitzes Stebilized OSC OSC period tors Fig. 2 Ceramic Resonator OSC Circuit Fig. 3 OSC Stabilizing Period as | 4MHe(Murata) 330F + 10% ee CSA4,00MG 33pF + 10% osci__osc2 eee 4 Miz (Kyocera) 33pF + 10% *| KBR4.OMS 330F + 10% n - Cort ext (28 | 4Miz(Murata)CST4.00MG i Sy BE 4 Mrz(kyocera) KBR-4.0MES Fig.4 RCOSC Table 1 Ceramic Resonator OSC-Guaranteed Constants No.2796-13/25

LC66506B,66508B to«er town tone tow toxe a 0.75Voo (input) ae 0.25Vo0 (input) | | Voo~ 1 V foutput) 0.4Vp0 (output) R=1kQ font TEST pont si J X= 0.7500 nS0pF si} A— 0.25V00 1 texo Fig.6 Test Load soo Voo— 1 So 0.4Vo0 Fig.5 Serial Input/Output Timing tion tin 0.75V00 0.25V00 to. the enc tes Fig.7 INTO, INT1, INT2, INT3, INT4, INT5, PIN1, RES Input Timing vw VREF Wore Vin Vorr ‘Comparator output data Ts Fig. 8 Timing of Comparator Response Time Trs No.2796-14/25

LC66506B,66508B eee RC OSC Characteristic of the LC66506B ,, 665088 Fig. 9 shows the RC OSC characteristic of the LC66506B, 665088. For the variation range of RC OSC frequency of the LC66506B, 665088, the following are guaranteed at the external constants only shown below. External constants Cext=100pF, Rext=2.7kohms 2.0MH2SfRCS4.0MHz (Ta=—30°C to +70°C, Vpp=4.0 to 6.0V) If any other constants than specified above are used, the range of Rext=2 to 20kQ, Cext = 68 to 150pF must be observed, (See Fig. 9.) (Note 10) The OSC frequency at Vpp=4.0 to 6.0V, Ta=—30 to +70°C must be within the operation clock frequency range {0.4 to 4.3MH2). fpc—Rext Characteristic | a 4 _— This characteristic curve is given for KN] reference only without guarantee z a z= yy g _N x q iif 1009 <a IN N XI N Voo= 5V Tan 25 \\ 3 N

2 A 2 3004«5

10 R (KM) 100

Fig.9 RC OSC Frequency Data (Typ.) (No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD,, its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO. LTD, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally, I Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. No,.2796-15/25

. LC66506B,66508B Application Development Tools , The programs for the LC66506A, 665088 microcomputers can be developed on the MS-DOS Personal computer system {IBM-PC model system). Cross assembler for this system is provided. To help the user develop programs for the LC66506B , 665088. microcomputers, the following development tools are prepared: Host control program Cross assembly Piggyback type simulation chip 64 pin Evaluation chip (LC66599) (ucespasxx) S4 ~ plug ifr . WYRE Sy lan Slit r Evaluation \\\\ Q SS » tt arp board EON sh — (EVA800- \\F ———__ 1 Ny eet TBEE5XX) \\ : VEE WY renanl epurayom Debugging unit (EVA850/800) (gg: MS-DOS) User application product circuit board Appearance of Application Development Tools (1) Program debugging unit (EVA850/800) The program debugging unit (EVA800) is an emulator that inctudes the EPROM WRITE function and the paratlel/ serial data communications interface function between the unit itself and external systems (host computer, etc.). Application programs can be developed, corrected, and debugged at the machine language level, The debugging function can be carried out through break, step and trace operations. (Use the MPM665XX as the monitor ROM ‘on the EVA800 debugging unit.) (2) Evaluation chip board (EVA850/800-TB665XX) The evaluation chip board sends control signals to the user application board through the 64-pin connector. Data is transferred between the 1/O ports on the evaluation chip board and the user application board through the 64-pin connector. If the LC66599 evaluation chip is connected to the 64-pin plug by the output cable, the data from the LC66599 microcomputer is converted into the LC66506B, 66508B -bound data by the plug. There are jumber connectors on the evaluation chip board. They are used to select options and status levels. Therefore, using these jumper connectors, the same input/output formats and functions as those of the LC66506B, 665088 microcomputers can be selected on the evaluation chip board. Jumpers Type Reset type selection Power supply to the user application board through the evaluation chip bosrd [Gimpercame | sumpor Ti) _[Jomper ua) uper 33) [EXT | Externst clock | INT Reset by the RUN instruction VDD supply to the user eppli- Jumper setting from the host computer. cation board through the evalu- andmode [RC [RCOsc | etion chip board output. Ceramic resona- | EXT | Reset by the reset circuit on Power supply to the user appii- tor OSC the user application board cation board from an independ- ent power source {from the evaluation chip board) Switch 1 (SW1) selection [Switch nome [pos [pis | pas | Roo [Act [Ceecity {| wor =i Port 0 Pore | OPEN | OPEN [RESERVE Watchdog timer| Switch setting oH" oH" RESERVE function and mode selected Port Port O Ports | OPEN | ON | 612W | Watchdog timer| “un “Lu “un function not selected Switches SW2 to SW14;: Pull-up resistor option select © Set to ON when on-chip pull-up resistor is used, Set to OPEN when open drain output type is selected. @ Selectable for each pin. No.2796-16/25

LC665068,66508B (3) Cross assembler . Cross-assembler } Mme | Functional differences LC66S.EXE Lce6698 invalid LC66508B, SB command LC66599 invalid (4) Simulation chip The simulation chip (LC66PG5XX) is a piggyback type microcomputer. An EPROM containing programs is mounted on this chip. Then, the simulation chip is incorporated into an application product board and actual operation can be monitored. @® External view and EPROM The pin assignment and dimensions of the LC66PG5XX are the same as those of the LC66506B, 665088. The pin assignment is shown below. The EPROMs to be mountable are 2764 and 27128. @® Reset output level of ports 0, 1, 8, watchdog timer function, and memory capacity selection Select the reset output level of ports 0, 1, 8, watchdog timer function, and memoty capacity according to a microcomputer to be evaluated. Set as shown below pins 1 to 6 of the 14-pin socket on the package surface. [Function tyes] Fino. [Pntome | Pineting [Function moss] output level at reset PTHL pu] ore | oreune” | Watchdog timer [ * wool | ON Operation | [ore ale On-chip RAM cepacity RAMCO | __—Pinsetting | RAM capacity RaMct [ore [on | or ON: +5V voltage input OFF: Open LC6G6PGSXX Pin Assignment 5,29 GAJO Lan veo _soo/Pat C2] [Ba] P13 SoKo/e22 Fa] pono1 wo+sy fe Pi? wro/ezs Fa] pincoa 130-+5y [B® intie30 C3} pen.o3 120 +5y foo) PY pouro/P3! [élaawcoo4 1045 (oe) P03 pout P32 [7] ramc1o5 100 +5y [oB) P02 FOL0/P33 LB} wocos 90 +5y [SD PO! P03} e107 go [6} Poo Pat [ip [58] PEN/TRS ea 01 [Sa] Peo/TRA p43 [$3] PD3/0MP3 ps0 [13] [2] Po2/ome2 est OZ] POI/OMP! P52 [50] POO/CMPO P53 [16] [43] PC3/VREFI BOKI/Pa2 [IS)PMI29 2 270 TaE) eco pini/es Cz] PM7Q 3 26OPM UTE) pas pr [at] PMEQ 4 2OPME Eon p71 (aa) pms 5 24 PMS fa3] pat bro Ga] PMA § BQPMIERS © prs (2a) PM3Q 7 zou Han OS an fs] PM2Q £21 OPMIOEE ae per CBPPMIO ® 2QCE Ts) pal a2 [Ez] PMOQ'S 19QIM7 FF pag P83 (23) mogr 1BOIME 5) P93/INTS. wi = M19l2 1705 “a caies M2013 16 IMA ES is vss O14 1501M3 Fe vss GY) C----4 {34} RES osc: G2] [33] osc2 No.2796-17/25

LC66506B,66508B ee SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSssssssessesse @ Power source for EPROM Normal current dissipation per EPROM is in the range of 50mA to 100mA. When power capacity of an application product is not sufficient, power can be supplied to the EPROM from external independent power source. That is, the power source which is different from that on the application system can be selected. {See the figure given below.) At the factory shipment, the +5V pin and Vpo pin are connected on the LC66PG5XX. Therefore, power is supplied to the EPROM from the LC66PG5XX power source terminal. Of the power source pads on the . package surface, +5V pad is used to supply power to the EPROM. git wat er 0' e gee gee sootst ° e a0 38 28) <O ao a ee ie x) eee sd? Oe ald e008” e ease? rine t ses gee i nt 200%” of q sy ‘\\er*ig. i po \\a ore Se Pint ‘64-pin shrink pitch terminals = int ay in shrink pitch terminal TSS EPROM power source Pini (different power source n . from that for the LC6GPG5XX) —_At the factory shipment, the +5V pin and VoD pin are connected. The LC66E516 microcontroller with built-in EPROM and LC66P516 microcontroller with built-in one-time programmable ROM are used as emulation chips for the LC66506B and LC66508B. Data sheets for the emulation chips are in preparation. Please contact your local representative for further information. No.2796-18/25

LC66506B,66508B SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSEO LC665XX SERIES INSTRUCTION SET (BY FUNCTION) . Symbol Description AC : Accumulator E : E register CF > Carry flag ZF : Zero flag HL : Data pointer DPH, DPL XY : Data pointer DPX, DPY M : Data memory M (HL) : Data memory contents specified by data pointer DPH, DPL. M (XY) : Data memory contents specified by supplementary data pointer DPX, DPY M2{HL) : 2-word data memory contents specified by data pointer DPH, DPL. In this case, the accessed data memory area address must be multiples of 2 (even address). SP : Stack pointer M2 (SP) _: 2-word data memory contents specified by stack pointer M4 (SP): 4-word data memory contents specified by stack pointer in + mbit immediate data t2 : Bit specification | 2 [J to [or [00 | Pee fee [ef PCh : Bits 8 to 11 of PC PCm : Bits 4 to 7 of PC Pcl : Bits O to 3 of PC Fn : User's flag n=O to 15 TIMERO : TimerO TIMER1 ~~: Timer 1 slo : Serial register P : Port P (4) : Port contents specified by 4-bit immediate data INT : Interrupt enable flag (JC) 1: Contents - : Transfer direction and operation result ¥ : Exclusive logical sum A : Logical product Vv : Logical sum + : Addition - : Subtraction _ : 1's complement No.2796-19/25

LC66506B,66508B ——_.s SS Ee DrDeDs01 | Ds020,0s | & CLA Clear AC 0000 1} AC—o0 Clears AC, Samson {Equivalent to LAI 0) fee, Decimal adjust AC in Lido; i1id AC—(AC) +6 Adds 6 to AC. addition 0010; 0110 (Equiveient to AD! 6) DAS | Decimal agyust AC in | 2100/1131 ‘AC—(AC) +10 ‘Adds 10 t0 AC. aF g subtraction 0010] 1010 (Equlvotent to AD! OAH) Boe lower [evo friveli[ifeco [omen re Elsie Jew [eeer peat [efor fewer, or J] [am oneeene tooo Pees Tr ete remeron ne fe E(x Trceren as [odor [oreo filemon fawewat pre E [ox [essere Ae fe er0[ 0100] 1 |r [xem9c)—1 [nena en AG H er | Rotate AC right [oor] 0000 a ‘ACi—(CF), ACN—(A | Rotates AG right through CF, CF 3 through CF Cn+1) , CF (AC) | z i RAL Rotate AC left through | 0000 ACor=(CF), ACN +l | Rotates AC left through CF, oF (Gn), CF-(ACs) | [ie —[reniesewe foree[erer [i ifecao REF Reamer [tex [tome ew se [oroo[orre|e[s[ao-m@ [enn oe Emerson we | | [rss [extoree ewe evoo lovee] i | [aon [Pass rere ple [rwerenm [ooo Poor e| ef wow ecnet [asa toa et |

2 M(HL)—(MCHU))— 1 | Subteaces 1 trom MHL), 2, CF

H [Se a ee ee Pe § [SMa 12 [Set M date or 0000 ree tap| (M(HL), (2)—1 ‘Sets a bit pecified by 1110 of MIHLI. | || } [ee | Reset Mdatabt | 0010 peer py (MHL), 2-0 | Rests 6 bit specified by tH of F |] T Adds together the contents of AC "Ad M te AC 0000{ 0110 ACe-(AC) +(M(HL)) | AEBS roRerhor the contents of AC ZF. CF || rewuit ia AC. = ia) | Adst together the contents of AC ‘ADDR i8| Add M direct to AC a a el ACH(AG)+(M(i8)) | Bdge together, the ‘contents of AC Pe} | rotutt in AC F ‘Adds together the contents of AG, ADC [Add M to AC with CF | 0000 Ac (AC)+(MCHU) | Hi Ena rn binary end toes | 2 OF | | +(CF) the rest in AG. 3 ‘Aad immediate data to[ 1100 2 [2 [ACH(AG) ta tatile | Add, tonathor the ‘contents of AC | i ac (oo10 stores the result in AC. Hf — — ‘Subtracts the contents of AC from | zr, CF [CFROi EY Suac | subtract AC tom [0001 AREIMOHD)~(A0) | See ce nay ond oe fewive § with CF the result in AC. een

3 Winer ie

i ins, 8 AND Mwith AGthen |0000)/ 0111 ACH (AC)A(M(HL)) | Performs Tonics! AND “operation em | = store AC the revult In AC, fe i a }) | Performs @ logical OR operetion ORMwith ACthen | 0000 AC=(ACIVIM(HL)) [Performs 6 logies! OF operation FP | store AC the result in AC. i rt Performs @ logical exclusive OR EXL | Exciusive OR M with 1] ACH(AC)¥(MCHL)) | Performs 8, logical axclusvedng |Z || AC then store AC and stores the result in AC, (AC) Performs @ fogicel AND operation AND Mwith ACthen |0000| 0011 MCHL)—(AC)A(M | Performs fe Touleal AND operation | 7p | | store M (Ht) ‘the result in MHL). ORMwithActhen [0000/0100 MCHL)—(AC)V(M | Performs 8 Togies! OF operation F [| store M (Hu) the results in MHL). No.2796-20/25

LC66506B,66508B 12 flogs: Dr010s0. | 0101010 | & | 6 affected , Tac) 1 | Compares the contents of AC end Compare AC with M 0110 MCHTY} + (AC) +1 MHL) and. then sets/resats ne 2F, CF ‘carry fleg (CFI and zero fleg (ZF). (M(HL)}> (AC) oO {M(HL))=(AC) 1 : {M(HL))< (AC) o H cr ia Compare AC with 1100} 1111 Ta Te Ti To +(AC) +1 rene soe on ae, secumuletor (AC) H immediate date 1010] bitte ard rade Gt 12110 rd mea i [Sompartn intone [OFF] H fateh le >AC

8 In leh tesAC

Flore Compare OP, with 1100/1111 Wet ‘Compares the contents of OPL and é immediate data 1011] bhhbe if(DPL)= Ia fa Ls Lo | Immediate date and sats the zero fleg eo (ZF: if they are equal, or resate the IMOPL) Ala Ly ty le | MART Sot ena: Compare AC bit with | 1100} 1111 Fed Compares the contents of AC and M data bit 1101) OOtt (AC, 2) =(M(HL), | MUHL) bit specified by the 2 bits 2} (t1 and 12) of the instruction aod sets 2-0 ‘the zero fag, 26) Hf they are equel, — or resets the flag i . it(AC, 12) mcMcHey, | OF ™#eN He Tag nox aa t2) UAE [Load AC and E trom | 0101/1100] 1] 1/AC—M(HL) ‘Loads the contents of M2(HL) into M2 (HL) | EoM(HL+1) the AC and the E register. LAL i4 {Load AC with immed- [ 2000[hbht | 1] 1) ACH ih le | Loads immediate data into AC. aF fiueney ate data { Pace Pie Totten LADR ig | Load AC trom M direct] 2.100 ane ‘AC (M(i8)) | kpads the contants of MBH into =e || Tale ls be Stores the contents of AC imi Store AC and EtoM2} 0101] 1110/1 M(HL)—(AC) ‘Stores the contents of AC and the E (HO M(HL + 1}—(E) ragister into M2(HL), LA reg | Load AC trom M(reg) AC—(M(reg)) Loads the contents of Mireg) into AC. reg is either on HL or XY. HL xy LA reg,l | Load AC from M(reg) | 0100] 10t1 ACH(M(reg)) (Loads the contents of Miregl into the ZF stotus then increment reg DP OPS EL sccumulator (ACI. r0g is either an HL depends on : or XY. After loading, increments the DrLorDPY 5 or contents of DPL or DPy, Refer to ‘increment & DPy—(OPy) +1 the LA reg instruction for the result. z relationship between reg and to, $ LA reg. | Load AC from M(reg) | 0101 ACH (M(reg)) Loeds the contents of Mireg) into ZF status (DPE) AC. rag is either an HL or XY. After pends on 2/° then decrement reg DPEm{DPL) = loading, decrements tha contents of OPLorDPY 3 PL oF DPY. Refer to the LA reg oeroment

3 OPy—(DPy)—1 instruction for the relationship rasult

5} barween reg and 10, Exchange AC with M (AC) —(M(reg)) Exchanges the contents of AC and (reg) ‘Micog). cog i eithor an HL or XY. HL 9 xy 1 XA reg.| | Exchange AC with M (AC )—(M(reg)) Exchanges the contents of AC and | ZF ZF status (reg) then increment OPL-(OPL) +1 ‘M(ceg). ro is either an HL or XY. epends on ree or After ‘exchanging, increments the OPLorDPy Oo -(oPy) 41 contents of DPL or OPY. Rafer to increment v—(OPy the XA reg instruction for the result. relationship between reg and 10, Exchange AC with M (AC)—(M(reg)) Exchanges the contents of AC and | ZF ZF stetus (reg) then decrement DPL-(DPi)~1 M(reg). reg is sither an HL or XY, depends on ree or After ‘exchanging, decrements the DPLorDPY, OP (0Py) =1 contents of DPL or DPY. Refer to dacroment ve (DP ry) — the XA reg instruction for the result, relationship between reg and to. XAOR i8 | Exchange AC with M 1000 2 | (AC)=(Mi8) ) Exchanges the contents of AC end direct Ish be MiB}. No.2796-21/25

LC66506B,66508B SS & flags 0:040:0, | 0,030.0» affected | LEAI i8 | Load E & AC with 1100/0110 E ty te ls le Loads immediate date i8 into the E & immediate data ty le Us te] ta be th be AGIs Ie li te register and the eccumwulstor (AC) t | RTBL | Read table data trom £, AC+-(ROM(PCh, E, | fin'unr mga end ec some Then eee . H program ROM 4C)) BenOW sateen brow acid by th nor £ fora of the Toner 8 iro! PC ime E A menered Ae & RTBLP | Read table data from Port 4, 5 fire. impizens the contents af lower @ bits of AC 3 program ROM then (ROM(PCh, E, AC)) | Senou date n anne ov Byte one s output to P45. ‘contents of the owas B bits of PC to por d end 6. LODZ i4 | Load OPx with zero and OPH Loads the deta of O (zero) and OPA with immediate Pi b hai le irumediate dat i into the OPH ond data respectively Lrespacitively UHI 14 [Load OPx with 1100 Loads immediate deta i@ into the immediate data 0000 OPH. LU id | Load OP, with 1100 Loads immediste dats i4 into the immediate data oool Pt. LHL 18 [Load DPw, DPA with 0000 DPwm tr es Loods immediate deta into the DPH immediate data Ith lo PLM Is tet be and DPL, LXYI 18 [Load DPx, DPy with 0010 OPk—Ir lols ly | Loads immediote data into the DPX immediate data lala le DPy—ts I2 hh bo land DPY. by 1. | i aac a aa cc yt. | A byt £ [Tan | transter AC to DP Tilt OPi=(AC) Transfers the contents of the § 0000 ‘accumulator {AC) to the DPH. S\\THA | Tronster DPx to AC 1111] 2| 2; acecoPw) Transfers the contents of the OPH to | ZF = 0000 the AC. é Exchange AC with DPw 0000 (AC)= (OPH) Exchanges the contents of the : sccumutator (AC} and the DPH, B[TAL Transter AC toOP, [1100/1111 DPi-(AC) Transfers the contents of the g 1111/0001 secumulator (AC) to the DPL, lta [Transfer OP. to aC [1200/1111 Transfers the contents of the DPL to 1110] 0001 the eccumuletor (AC), Senge Reino ae voor [Esme meme stm ney [| and DPL, TAX Transfer AC to OPx 1roo; aiid DPx--(AC) Transfers the contents of the 1111} 0010 wccumulator (AC) to the OPx. TXA Transfer DPx to AC 1100/1111 ‘Transfers the contents of DPX to the 1110] 0010 AC Exchange AC with OPx 1] 1 | (AC)—(0Px) Exchanges the contents of the AC ond OPX. TAY Transfer AC to DPy 1100}; 1111 DPy—(AC) ‘Transfers the contents of the . liirjoo1l ‘eccumulator (AC) to the DPY, TYA Transfer DPy to AC 1100 AC—(DPy) ‘Transfers the contents of the DPY to 1110 ‘the AC, XAY | Exchange AC with OPy | 0100] 0011 (AC)=(DPr) Exchanges the contents of the eccumulator (AC) and the DP. i aK al a a Jump in the current [1110 | PuPuPsPy| PCL2—PC12 Jumps to an sddress specified by when le bank PCL1~O—Pu~Po | immediste deta Pi: ~ Po in the ee coly PyPePsP. | PaP2PiPo ‘current bank, after the Be BANK EE instruction, H Pera tPCra Jump to the address [0010] 0111/1 PC12~PCB—PCI2~ | Jumps to an specified by the Hy Stored at E and AC in PCB PC7—4--(E) | Semulora LARY whisk Gere nies the current page PC3~0-(AC) Breoremeouncer (PEP of me meee No.2796-22/25

LC66506B,66508B Els Function tiogs | Remarks E { CAL Call subroutine 0101/0 PwPoP,} 2 | 2 | PCI2,11--0 addr PC10~O— Pig~Po PrP6PsPo | PsP2PiPo M4(SP)—(CF, 2F PC12~0) SPH(SP)-8 Call sudroutine in the PSP:P:Po| 1 | 2 Bole>6, PCL-0--0 Calls a subroutine in page 0 of bank 0. zero page ~ 2s Pa~ Po [| macsP)—(CF, ZF. PCi2~0) sp—sP.4 eee eee 2 ben ‘B| PUSH | Push reg on M2(SP) | 12100) 1111 2 | M2(SP}—(reg) ‘Stores the contents of rag into the M2ISP). and then subtacte 2 from g| ve 111d] lie SPr-(SP)-2 the stack pointer (SPI. = HL oo g xy Oo}

2 AE 1 0

2 tonibited | 11 POP reg | Pop veg off M2(SP) Tiid SP—(SP) +2 So te conan oF ie MRP) rd pas Livio 0 i rege~(M2(SP)) | Soma fnl'by'2 ond ome Be conn oT a {Srl eon eg Reto fo te PUSH rgimeton {Grose eescnani utwaen 10 on RT Return from subroutine | 0001] 1100] 1/| 2 )SP-(SP)+4 Berane srseaton fom |s nabroutine or interrupt PC-(Ma(SP)) Pistaehman ated | ent atuna rm he Hack oe RTI Return trom interrupt oo001;1101 2 | sP(SP) 44 beled execution from # subroutine or interrupt | ZF, CF routine Bom tedc$P)) Prong cia ek oh tend CF, ZF—(Ma{SP)) | (Gereermvied tom wnuct ee. BAt2 — | Branch on AC bit 1101] 00t% PC7~O—P1 Po Ps Py Traraferysxacution toon accom 1 PP sP. | PsP? * ps | specified by the contents of P7 to ada PrPsPaPe | PaPsPiPo Tire ia | the current Boge it a bit specified i hers by immediste cate 1110 of AC in 1 rogram branch), BNAI2 | Branch on no AC Bt | 1001| 00 PC7=O= PrPsPsP, | Transfer exgcution to an address © PAPsP ‘Pe oe | specified by tho contents of P7 to. ace PrPePsPe | PoPaPiP Tena aye | in te current page if» bit epectied 12)= | py immediate date t1t0 of AC lr 0 i J (program branch). @Mt2 | Brench on M bit 1101 |0ttt& PO7=O—PsPaPsPc | Transfery sxacution oan cdrom specified by the contents of P7 ta dr PaPePsPo | PaPsPiPo Fob Pe | in the currant page it a bit specified | HCM(HL), | py immediate data t1to of M(HL) is t2)=1 1 (program branch}. BNM(2 | Branch onno Mbit | 1001] 01tw POT~O—PsPePsPs | Teaafere execution to, wy addrom } 18 of P7 to ader PaPePsPe | PaPaPiPo Fein), | im the current page if» bit specified CAMEO: | by immediate date tito of MIHL is (program branch). BPI2 [Branch on Poko | 1101] 10Nw PC7~0-P;PsPsP, | Tronetors execution to an eddress Ted 1 addr PyPePsP | PsP2PiPa PsP2PiPo | specified by the contents of P7 to PO eterna : irePcDP,), | ia the current page if bit spectieg contra & t2)=1 | by immediate data tito of the port registers if & d= sccessed by DPL ln 1 (program recut aiy| : branch). disc = Peete, : tha intornat eontrot . ase BNPt2 Branch on no Port bit | 1001) 10t& PC7~O—P1 PoPs Py ‘Temnates exrcutin, to on address specified by the. Some as addr PiPsPsPe | PaPaP Po PaPiPiPo | Seitiod ty ininaum Gate 1 the ort above. if(P(DP.), | Screed by DPL 90 Ipropram branch 12)=0 Bc Branch on CF 1101) 1100 PC7~O—P, Pe Ps Py | Tranafars execution to wn address woecitied boy the ‘addr PrPsPsP, | PiPiPiPe PoPaPiPs Seer ot ary HF oem iCF)= 1 | box Branch on no CF 1001/1100 PC7~O- Py Pe Ps Py ‘Texas aneson 62 00 bdr epee ty vue PiPaP SPs | PaPsPiPy PabsPuPe | Grantor fag WH 8 Toons az Branch on ZF 1101/1102 PC7~O-—Pr PePs Py_| Trams oxen vow ese wat by te addr PrBsPsPa | PoPiPiPo P2P2PiPo | Sot ot tw mw tag 126th t Nooo iKZF)=1 | Swen, BNZ Branch on no ZF 1001} 1101 PC7~O—P; Pe Psy Py | Trenctorn execution to wh eddies sotcified by the: eddr PaPePsPo | PaP2PiPo pepapige = Te tat ee Browee No.2796-23/25

LC66506B,66508B eS 3 flags BFn4_— | Branch on flag bit armani ne PC7-0-—-PiPsPsP, | Transfers execution 10 en address B| ado PiPaP Pe P,P:P,P, | sotciled by the contents of P7 to PO s itten)c1__ | if the current page if the content of g * ‘the flag specified by n3n2n ind it 1. E The ftag is one of the 16 flags. =} enend | Branch on no flag bit | 1.01 1 | nsnenine PC7~O—PiPePsP, | Transfers execution to an address addr PoP 6PsPa | PaP2PiPo P3P2P\\P, | sPecified by the contents of P7 to PO Fieeay2o._| 18 the cureant page If tho content of & the flog specified by n3n2n1n0 is 0, The flag it one of the 16 flags. Iaput port 0 to AC 0000 AC—(PO) Inputs the contents of port 0 to the | ZF accumulator (AC). Input port to AC AC—(P(OPL)) Inputs the contents of port accessed | ZF by DPL to the accumulator (AC). Input port to M M(HL)—(PCOPL)) | Inputs the contents of port accessed by DPL to the M(HL}. Input port to AC direct] 1100| 1112 AC (PCs) Inputs the contents of port accessed | ZF 0110] hhh be by i4 to the accumulator (ACI. iPa5 | input port 4510 EAC = m1P4)) Tapia the contents of Baru 4 and respectively ACH(P(5)) Tach tapectvenr’ °72 Becumuletor £ oP Output AC to port 1 | P(OPL)—(AC) Outputs the contents of the accumu 5 lator (AC) to a port accessed by DPL. BT opm | ouput to pont T[P(OPL)—(M(HL)}, | Outputs the contents of the MIL z Yo 8 port accessed by DPL. Z OPOR i] Output AC to port 1100|1111 2 | P(i4)—(AC) ‘Outputs the contents of the accumu- H direct O11 itt bo tator (AC) to a port accessed by i4, Zlorss [ouput €. ac to pot | 1100/1111 /2|2|Pa—e ‘Output the contents of the E ister and lator {AC) = 45 respectively 1101/0101} P(S)==(AC) ported and 6 respectively. ° SPB t2 0000) 10tt/1 (PCOPL), t2)—1 ‘Sets @ bit specified by immediate | dota t1t0 of e port accessed by DPL. RPB t2 | Reset port bit 1Oti to} 1 | 1 | (PCOPL), t2)-0 Resets 9 bit specified by immediate | dete t1t0 of # port accessed by DPL. ANOPOR| AND port with 1100/0101 P(P2~ Po) —(P(P3~ Pero 8 logics! AND operstion between the | ZF i404 |immesiate data then | tr a] PHPLPLPa Po))VIa~le Ter a BN we te md ORPOR [OR port with immediate | 1100] 0100] 2 P(Ps~Pe)—(P(Pa~ | Perfor lened OR oowrlon tate te i, p@ | data then output Ih yh bo] PaPaP Po Po))V I~ lo ‘msclne date TDD en ovtovee the reads tone apo at Writes the contents of the MHL) end WTTMO) 1100] 1010]1 TIMERO (M2(HL)). | Tho sccumutoter TAG) te the tien o it reload register. i 1 I frites the contents of the E rogiiter . timer 1 reload register. | RTIM i — Reads the contents of the timer O g]RTINO. [Resa tirer 0 eee ee Counter into ihe MSIHL) andthe 2 ¢ ecoumulstor (AC). i 7 Feods the contents of the timer 7 a ESTES cam ecco = accumulator (AC). B| STARTO 1100); 111d ‘Start timer O counter | Starts the timer 0 counter operation. 5 1110) 0110 g | STARTL 2100; 1111 ‘Start timerl counter | Starts the timer 1 counter operation, é J P1L1LO;O1I1 STOPO 1100] 1111] 2| 2] Stop timer Ocounter | Stops the timer 0 counter operation, D111; 0110 STOPI 1100| 2111] 2| 2] Stop timert counter | Stops the timer 1 counter operation, Lat} orld eee No.2796-24/25

LC66506B,66508B H By D1D.03D. | :0:D.0 | 8] O MET | Set interrupt Master [1100/1101 tee | ‘Sats the Interrupt moster enable flag, ft | Enable Flag 0101/0000 MRESET | Reset Interrupt Master | 1100] 1101 MSE—0 Rents the interrupt master enable Enable Flag 1001| 0000 fieg. g [EIi¢ | Enable interrupt high | 1100 eee EDIH=(EOIH)Vid | Sets the interrupt enable flag, r [| : o101 : ee | seven [oi8e ee ores [womens fT s 0100 3 — : Pe | — [agen]? | oven [rrerenneenne eT : 1OOlLjhh hl i 1008 nae surgouns [terereenremente Te | 4 1000 Tranafors the contents of the © _ | et otal]? “ee [srreseamn Rover] [| : stack araa, ‘Transfors the contente of the stock Intor (ACI. ; iio "I" _ oomerne TT rit EB 1101 ° B8/ Hou [Hou rroo;1iiti | 2 | HoLo Solects the HOLD mode, | || q| troar}iiiy | g 1110/1110 Sz) el 1 Writes the contents of the E register S8| wrsio [wee seria! v0 1100] 1111] 2/2] sto ce), cacy | Writes the contents of the E register SH riio} iii cogistr Ba Reeds the contents of the S10 se Read serial 1/0 rroo]r1ii[2/ ale acs) aoe oro tee B veciior eed the paaayraid ! sccumulator (AC). a vere refi wome [eyoacaam | Just one machine cycle signal reeches the oPU. UsbTe Select bank ri00;1111 PC13, POLZ— Is lo priy 22 BOPOEXM No.2796-25/25

Summary

6K-Byte/8K-Byte ROM-Contained Single-Chip 4-bit Microcomputer for Control-Oriented Applications

Description