LC66354A SANYO | Alldatasheet
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LC66354A, LC66356A, LCG6358A SANYO i 4-bit Microcontrollers with Built-in ROM OVERVIEW The LC66354A, LC66356A and LC66358A are 4-bit ¢ 12-bit timer for timeout function, event counter, pulse microcontrollers with built-in 4, 6 and 8 Kbyte ROMs, measurement and rectangular waveform generation respectively. They incorporate RAM, input/output ports, © 8-bit timer for timeout function, event counter, pul- a serial interface, a comparator and timers in a single sewidth modulated output and rectangular waveform chip. generation The LC66354A, LC66356A and LC66358A feature a [PI Pre-scaler for timebase function 7 . . . ee external interrupt inputs large instruction set compatible with that of the ° Five i . . . . . ive internal interrupt sources (two for the timers, two LC66000 series devices. They are functionally identical for the serial /O and one for the pre-scaler) to the LC66306A, LC66308A, LC66E308 and ©20 mA dri . P . . . river outputs with 15 V withstand voltage LC66P308, but have a different supply voltage range . . * Ternary-level and comparator inputs and hold-mode release time, . . V/O pull-up resistor and open-drain options The LC66354A, LC66356A and LC66358A operate * Runaway detection option from a 5 V supply and are available in 42-pin DIPs and ¢ Halt and hold modes for program-controlled power- 48-pin QIPs. down * LC66599 evaluation chip, EVA850/800-TB6630X FEATURES debugger, LC66E308 EPROM and LC66P308 PROM development tools available ¢ 4, 6 or 8 Kbyte ROM and 512-word, 4-bit RAM * 5 V supply * Instruction set compatible with the LC665XX series ¢ 42-pin DIP and 48-pin QIP ¢ 8-bit serial interface which supports 16-bit cascade connection * 1.96 Us minimum cycle time at 3.0 to 5.5 V, and 3.92 us, at 2.2 to 5.5 V SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg..1-10,1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 11894 JN A8-8427/10823N No.3928-1/24
LC66354A, LC66356A, LC66358A PIN ASSIGNMENT PACKAGE DIMENSIONS Unit: mm poo [| [42] TAePEs or [a] men 3025B-DIP42S poe [a] [zo] voo pos [| [39] cupsipos 2 is pro [5] [38] cupapo2 | pn [e| eMPH POI 198 18:24 2s pre [z=] cuPooo | | prs [| [35] vREFuPcs ' bi sior20 [| [34] vreropce 379 Stina Sooper [9] ucesssaa [33] Pimves TT To SeKorrze [11] LC66356A {22] SoKtPEe | woes [a] 1569584 fa] sovmes vb bic lheoos a intvrso [3] [20] sivpso pourars: [1a] fea] iNizeso poutwps2 [15| [2a] ps2 3156-QIP48E wowwress [ro] Pst 172—_$<+ mo fs) po ff Tg oy pas [ral [as] as eee test [19] [2a] Pse Z E vss [20 [2a] AES 172 140 =| E oscr [22] osce =| = a= Fe 13 TEE TEy! veal ee t2 270k) ok Le =288, so max efesee eee =| fear BaSSESSR TELE cof APARA RAAB Res Note 37, 24 Mpapps cot Ee bs Reflow soldering is recommended for QIP packages. VOD cx —- Please consult your local representative for further infor- ‘TRAPEO oo Fo Fes : TABFEY S LC66354A ‘aad osca mation. | LceesseA ES te Poo oS Lce6358a Fe osc Por = Fo vss Poz oH Fao Test =O) ES pe @ rr WOTOUS EEOC ON =sogrONRgs EERE? SEER RE
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No. 3928—2/24
LC66354A, LC66356A, LC66358A BLOCK DIAGRAM = | Test & re (elz] oset soe [ [ Osce
1 Doo
wo Tae) [1 [x\\ fi pati i if {$a pouro teaper gl os | [Presenter ] f| Minener of Timer 0 $00 [> 1 raarco gl pes cuPor00 m—p> [Mutiplexer] ee eee curio: won| CMP2PD2 aan om Wi, NB curaros wf Un Soval : vreruece Co T 7 7} n Pc fF ____sm pins. pours VREFLPCa a P00 Pot Poe Po3 PIO P11 P12 PIa.P20P21 P22 P23 P30P91 Pa2 PIS P40 Pai P42 PAS PSO PS! P52 PS9 PEO PE P62 PES PIN DESCRIPTION [ne vane oesrn ares - + “semen eee a ee ee ee Poe 4-bit inguvoutput port P1 (P10 to P13) ee ee ee ee Multiplexed 4-bit inputoutput por P2 (P20 to P23), serial input 0 (S10), cc | serial output 0 (S00), serial clock 0 (SCKO) and interrupt request 0 (INTO) [i [rena et a a (INT), timer outputs (POUTO and POUT!) and hold-mode control input eae No. 3928—3/24
LC66354A, LC66356A, LC66358A ee a poe Pe ee 4-bit inputioutput port P4 {P40 to P43) a Poe foe |e a a a - External oscillator connections ee po [| «= [| | [Tf raters tour pt 25 (P50 oP) aed erg equ 2 Ee ee a ee [| [S08 | sateres at npwougt pat P6 P60 0 PS), sre mpl 1 (SI, [es {| # | ern sett output 1 (SO%), seal clock + (SORT) and event counter input (PIN) Multiplexed 2-it ipwoutput port PC (PC2 and PC3), comparator 0 reference voltage input (VREFO) and comparators 1, 2 and 3 reference [sos arr J [7 | | wir | Multiplexed 4-bit input pot PD (POO to PD3) and comparator inputs (CMPO ee P # [ «| TRAIPEO Multiplexed 2-bit input port PE (PEO to PEt) and temary inputs (TRA and 6, 18, 19, 20, a ae coe SPECIFICATIONS Absolute Maximum Ratings a a ig Input voltage range for all inputs, See note 2. 0.3 10 Vop + 03 No. 3928—4/28
LC66354A, LC66356A, LC66358A. ec SN pyrmmerrnnereases [ST | current grvaeeares [S| | current qrnrenmmrewniem | aw fe pormrma nem mom [me fe | Fn fre coon ores fmm Se Notes 1. Open-drain output configuration option 2. All output configuration options Recommended Operating Conditions T. = 25 °C, Vss = 0 V a a [ee
Electrical Characteristics
Von = 2.2 to 5.5 V, Vss = 0 V, T, = -30 to 70 °C unless otherwise noted a ee eam [| Voo = 30 to 55 V Voo = 30 to 55 V [recone woo | | | em [> [| Vop = 3.0 to 55 V Halt-mode supply current looer ame vmeraees | | om [os | mA Voo = 3.0 to 6.5 V fiwireene nae | [w= | s_| ocr oor ore | woo |m=vewssy | - | om | wo | m_| No. 3928—5/24
LC66354A, LC66356A, LC66358A moranater a Ports P2, PS (excluding P3), PS and P6, RES and OSC1 LOW-level Vus Guta nana! Hansson Vss 0.2Vo0 v Ports PO, Pt, P4, PC, PD and PE, Output n-channel transistor ang TEST LOW-level input voltage OFF. See note 1 Powe | = | eae fv | Temary input levels, Por PE Lovie! neu vologe Yoo = 27 to $8 V Powe | = [om | ov | Temary input levels, Pon PE Mip‘evel not xokege Yoo = 27 10 85 V [ows | - [oom | ov | Ports P2 to PS (excluding P33) Output n-channel transistor HIGH-level input voltage Vins OFF. See notes 1 and 2. 0.8V00 135 v FOLOIP33, AES and OSCt Ovtput n-channel transistor HIGH-vel input voltage Vine OFF. See note 2. 0.8¥o0 Voo v Ports PO, Pt, PC, PO and PE Output n-channel transistor HIGH-evel input voltage OFF. Soe role 1. [owe | - fw | ov | Temary input levels, Fort PE Lovie! oat vole Voo = 27 0 55 V [wm | - fw |v | ssw | - | - | | PC LOW-level output voltage OL lon = 8 mA, Voo = 3.0 to $5 V tos = 1 mA, Voo = 30 to 55 V. Voo = 1.0 See note 3. Ports P2, P3 (excluding P33), P6 7 and PC HIGH-evel output voltage Vor Cae om Voo - 1.0 v low = -01 mA. fens [vemos] = | | low = -80 A, Voo = 30 to 55 V. Voo - 1.0 See note 4. lon = 20 uA, Vpo = 30 10 55 V. Voo = 05 Ports PO, Pt, P4 and PS HiGHJevel output voltage Voue See note 4. v low = -30 HA. . leew [we] = | | low = -20 HA - ae Kod ee Ports PC2 and PDO in-phase, . comparator input vottage range Von = 27 10 58 'V Pe | a ‘ Ports PC3 and PD1 to POS in-phase, . _ comparator input vollage range Vowwe Voo = 27 to 55. V Vss Voo - 1.8 v Poris PD1 to PD3 comparator ofset Vi = Vss 10 Voo - 15 V, voltage Vos: Voo = 27 to 55 V +50 #300 mv Wi = 15 V to Vo, Pot FDO compara ose voage Voo = 27 10 85 V | - | 2 | | om | Ports P2, P3, PS and P6, and AES and OSC! Schmit-rigger LOW-evel Me 0.2Vo0 0.5V00 v threshold voltage No. 3928—6/24
LC66354A, LC66356A, LC66358A Ports P2, P3, PS, and P6, and RES and OSC1 Schmitt-trigger HIGH-level Va 0.5Vo0 0.8Vo0 v threshold voltage Ports P2, P3, PS and P6, RES and OSC! Schmitttrigger hysteresis Vavs 0.1V00 v voltage Ports PC, PD and PE LOW-level \\ Vi = Vss, output n-channel 10 A input current mt transistor OFF, See note 2. ° " LOW-level input current for all other | Vi = Vss, output n-channel “10 A inputs ne transistor OFF. See note 2. , " ‘i Mi = 13.5 V, output fons val heat tevcng P33) hay n-channel transistor OFF. 5.0 pA See notes 1 and 2. Ports PO, P1 and P33, and FES and \\ Mee pat rerannel OSC1 HIGH-level input current ie Sea notes 1 and 2 , Vi = Voo, output n-channel Ports PC, PD and PE HIGH-level triton OFF 10 Input curent See notes 1 and 2. Mi = 13.5 V. Output Ports P2 to P6 oulput leakage channel transistor OFF. uA current See nole 2. Ports PO, P1 and PC output leakage I Vi = Vpp. Output n-channel A current orFe transistor OFF. See note 2. 0 Vi = Vos, Voo = 5.5 V. Ports PO, P1, P4 and PS output current with pull-up option pow | Sean neanne Mansi Von = 30 t0 55 V, za Ceramic resonator input frequency for 2 MHz resonator MHz Ce Voo = 3.0 to 5.5 V, Ceramic resonator input stabilization ' 2 MHz resonator time crs [mene | - | - |» Notes 1. Ports with CMOS output configuration option cannot be used as input ports. 2. Open-drain output configuration option 3. CMOS output configuration option 4. Pull-up output configuration option No. 3928—7/24
LC66354A, LC66356A, LC66358A Timing Characteristics Serial input/output timing toxoy pw toxe = Po) Pav cinpuy Sa, HL avyS fsa Yoo = TV outa Nick ton a | Ver — OEY sensor = Mie Von = 2.2 to 5.5 V, Vss = 0 V, Ts = -30 to 70 °C eran es a tove = 04 to 2.03 MHz, |» | 10 1.98 Instruction cycle time teve Voo = 30 to 55 V | us SCRO and SCRT serial clock input vo-sowssy [19 [| - [ - | lexcy us SEKG and SCKT serial clock output 2 cycle time love SER ard SCR stl cock we ssoossv | oe [= | = | SCKO and SCKT serial clock output ' pulsewidth ve SCKG and SCKT serial clock output tise time us SCKO and SCKT serial clock output fall time $00 and SO1 serial data output texo Voo = 30 10 55 V [= fe fs | us Note Each test input and output has an RC load as shown in the following figure. Yoo Test point | 1ka pr No. 3928—8/24
LC66354A, LC66356A, LC66358A External clock timing wenn nn nnn nnn gy -- oe -\\ --02Vp9 Vpp = 2.2 to 5.5 V, Vss = 0 V, T, = -30 to 70 °C OSG1 external clock LOW-level input Voo = 30 to 55 V [ wo | - [ - | ns sew ee ee ee OSCt extemal clock HIGHevel input fom | Yoo = 30 fo 85 ¥ [om | - [ - | 1s Interrupt and reset timing ios ts tei tase 0.8Vo0 | ©2V09 tok. HL, tiny: CASE Von = 2.2 to 5.5 V, Vss = 0 V, Ta = -30 to 70 °C me | = ee No. 3928—9/24
ware. The function of each pin is described in table I. Table 1. Pin functions a halt-mode control functions. Level atter reset is set by user option.
active pull-up as shown in figures 3and 4, respectively. to P6 have a maximum withstand voltage of 15 V. Figure 3. N-channel open-drain option The output level of ports PO and P1 after a CPU reset is The p-channel pull-up option for all ports is identical. . . sistor. Ports PO, Pl, P4 and PS are classified as pull-up, runaway. and ports P2, P3, P6 and PC, as CMOS. grams, and addresses 2000H to 2007H, for option mation.
Table 2. User options—continued
Figure 6. Ceramic resonator stabilization time Table 3. Recommended ceramic resonators remaining oscillator connection, OSC2, should be left
1 MHz Kyocera KBR1000H 0a
under MS-DOS. A number of other development tools or LC66P308 PROM, shown in figure 8. Figure 8. Development tools
monitor software control. It also_includes-an EPROM as shown in tables 4and 5. Table 4. Jumper settings Table 5. Switches 9 to 11 option. When a switch is ON, the corresponding output corresponding pin is an open-drain output. used for the devices shown in table 6. Refer to the operating information. Table 6. Cross assembler compatibility an 8-Kbyte EPROM which is used to set the user LC66358A. adapter boards. The LC66E308 is pin- and functionally- . time and electrical specifications of the LC66E308 differ .
ovror [2 [a1] tanreoice with those of the LC6635X series is shown in table 7. areas [1] [25] arorpas oscillator. Figure 9. LC66E308 pinout A breakdown of the LC66 series devices, which includes the LC6630X series, is shown in table 8. Table 8. LC66 series devices
LC66354A, LC66356A, LC66358A INSTRUCTION SET The following abbreviations are used in the instruction set table. AC Accumulator PCh Bits 8 to 11 of the program counter E E register PCm Bits 4 to 7 of the program counter CF Carry flag PCI Bits 0 to 3 of the program counter ZF Zero flag Fr User flags, n = 0 to 15 HL Data pointer DP, and DP. TIMERO Timer 0 XY Data pointer DPx and DPy TIMER] Timer 1 M Data memory SIO Serial port register M (HL) Data memory pointed to by DPi. P Port M (XY) Data memory pointed to by DPxy P (i4) Port specified by 4-bit immediate data M2 (HL) =‘ Two-word location of data memory at INT Interrupt enable flag even address pointed to by DPi O01 Contents SP Stack pointer eq Direction of transfer, result M2 (SP) Two-word location of data memory @ Logical exclusive-OR pointed to by SP : Logical AND Mé4 (SP) Four-word location of data memory + Logical OR pointed to by SP + Arithmetic addition in n-bit immediate data - Arithmetic subtraction (2 Bit specifier
2 Bit
ee P| ES ceed Fm" HB 8 fe fee Ppp h Pel en eee Cc OO fa eres EEE DD [eves ar OOO ee oe Cer 0 Ce ld ACs & (CR, ‘ og & (CA. Camere 0000 Ce eee PEELED face eeeeren fe | peewee EEE EEL bee a=] No, 3928—17/24
LC66354A, LC66356A, LC66358A Jw rc dof fefef fe] | wey © Me +t for fame fof fe fefole fife] | wee [more [reeoewone [ales fete/e [a fel = | ‘wel = Ml +t [owen [owmeewem [alls falelels fal = | wa) © Mh 1 me oe [eva fe fefefefeffate[ «| we ae | {0 ard It [mee [emwome —— foleffelefefnfof | wey ain ‘Adds the contents of memory location HL to AC + (AC) + (MIHL)] ‘the contents of the accumulator and stores the | ZF, CF ‘Md Mi diet to AC AC = (AC) + (MiB ontants of the accumulator and stores the mF, CF ‘Add M lo AC with CE AC + (AC) + IMIHL]] + (CF) | the contants of the accumulator with cary and | 2F, CF ‘Add immediate data to AC P 1 AC & (AC) + I 2 Ih Ip the accumuialor and stores the result in the ay ‘accumulator ‘SuBC ‘Subtract AC hom M with CF ‘AC © (MIHL}] - (AC) - [GF | the conients of mamory location HE with cary Takes the logical AND of the contents of the AND M with AC than store in e y accumulator wilh the contenls of memory aC ac (AC) - (MHL) location HL and stores the result in the ofA AC AG (AC) + (MHL) focation HL and stores the result in the aF Takes the logical exclusive-OR of the contents et ‘store in AC AC = (AC) @ (MHL) localion HL and stores the resuil in the u MEHL) (AC) «(MILI location HL and stores the resul in be Takes the logical OR of the conlenis of the OR M wilt AC thon tore In ba MAHL) (AC) + MHL] location HL and stores the result In memory a ‘Compares the contents of the accumulator with Compare AC with M ‘[M(HU] - (AC) - + 2F, CF wni-09 | [| wares fa |e | No, 3928—18/24
LC66354A, LC66356A, LC66358A blo} oe Compares the contents of the accumulator wih immadata dala Io lo Ig and sets ta condion fags 8 shown below data eenw>a | o | o | Leave | [| Compares the contents of the lower nibble of \\ Compare DP. wih immedi 2&1 (ORL) «Ip ig It Ip, | dala por HL with immadate dala Ip to Ia | ap Cut | ate ZF © 01 (OPLI = Ia It b | Sele te zor0 fag whan equal snd clears he zero fag when unequal Compares the bit of the accumulator specified . ZF 1H (AC, = BML, | by 19 ard 14 with to Bi o! memory lesion owe @ | Compare AC bt wit M data 2) 2F OW AC, 2 a | HL speciied by lo and Uy, Sels he 2070 fag bit [MCHL), 12} ‘when equal and clears the zero flag when unequal hoe Mt Loads the contenis of memory loeaton HL into ue load AC and E from MatHL) 1 Me the accumlalor, and tha contents of memory MHL + 1) localion KL + 1, into ragistor E ° Loads immediate data Ig 10 ty ini the [ue [screamer [ofofefela[a]s [ols | wer bene scout, Vere! skp function avetable | Lands the contents of the memory focaion LADR 8 | Load AC kom M direct AC & [M(8)] specified by immediate data Ip to I7 into the accumulator Stores tha contonls of fhe accumulate ia Stores the contents of the. accumulator in Store AC end E to Maj) we Ne mamary leesion HL, and the contents of ragstar E, in memory lncaton HL 1 Loads the contents of tha memory lection species by to ino the sccumulalor arn es [|| [oe | Loeds the conlns of te mamary keaton Specited by tp into the accumulator and ineromens the lower ritbie o! te coresponting memory location data pointer. Ua top| | 128 ORL (DAL) + tor Low | | The zero flag is set according to the date pointer increment operation. Londs he contanis of he memory locaton Apecid by 19 ino the accumulator ond ‘ocremenis tho tower ibbla of the comesponding memory location dala pone. Uv eeg, p | Lead AG tom Mleg) ten DPL & (OP) - 1 or Fg a ‘The zero flag is set according fo Ihe dale poinlar dacromert operon, Exchanges the contents of the accumulator with tha comnts of he memory locaton spocifed yo exes Aw Mo 0) a ee po |e | a No. 3928—19/24
LC66354A, LC66356A, LC66358A Exchanges th contents of he accumulator wih the contents of the maory lcalon specified ay & and incramens the lower nibble of Ine comesponding memory location data pointer cw 89) Mea ee Exchange AC with Meg) then DPL © (OPL) + 1 oF a ee The 267 fag is set according fo the dala ponte iermont oparaon. Exchangos tho conten of the secumuistor with the contents of the momary lection species by 1 and decrements the lowar nibble ol the corresponding memory ‘cation date pointe: ow oo Ma [mow Te XA rag, 0 | Exchange AC wth Mira) tron DRL & (0%) - 1 oF ee ‘The zero flag is set according to the dala poinler decrement operation, Exchanges the contents of tha accumulator with Exchange AC with M direct {AC} e> (Mia) tho conlants of the memory localion specited by immediale data 19 to I7 Loads inmate data lg 0 [7 ino register E, Load E and AC with ined Ee tbs : A “ “ jslslefe/e)|s/s] «| we be’ somo “wee Loads the upper nible of the memory location . spacifed by the program counter {he lower 8 ara, | Band tbl daa tom program E, AG. [ROMIPCH, € AC)| | bits ar replaced by the contents of ragiser & and the accumula) info register E, and the uppet rible, no he ocular loads te upper nibble of the memory feation . fecifed by the program coun: te Fewer @ rap | Geee ble da hom progam Eth ard 5 € [ROMIPCH, | sie wm rapiaced by the conlents ol register E }OM han output to Pe and PS ACI ‘and tho accumulate} info port P4, and the upper nibble, into pon PS Clears the contents of the uppar ritbe of dela Lead OPH with zero end DPL DPH © 0, DPL &— fy la It ‘9 | poinlor DPHL and loads immediats data Ip 10 19 with (mediate data inlo the lower nibble of data poinier OP Loads immediale data I 1 Ig inlo the upper teat OPH wn medals das fefs[e[efsfe[ifs] = [esewe | sivle et dee peinter DP |_| a Leads inmodat deta Io 1 1g int the lowar Jue [mwonomomeman [Taf e [felis] e [enone | re ot San ponte OP |_| yg | bowd OPH, OPL wits immediate | 9 DPH + 716 5 Loads inmeeiato data Ip 1 17 into the data u ata Cy Dee poner DPHL owl ie Load DPx, DPy wilh immediale | 4 1 DPX + I7 Ig Is le. Loads immediate data Ip to 17 into the auxiliary cata bh Pye HRD dais pormar DPxY [ pnts contenis ot the lower nibble of a eee DOGG oa mms [smear ees fe | Decramants the contents of the lower rib ol [= formers [oot fel felefe[ | fae ot ate porte DP BF 1 Ineramests fo conlens of the lower ebb ol jr freemeor —feefef feted [| «| oe ome sexary gain peer OPXY : Decremants tha contents of fo lower nibble of Fl Geeta Oe ony Pe - satiny cals porter OPXY | Copies te conlents of tho accumula: into te fm frwrcwom — Lififelefsfefelal = | oH 06) wpper neve of daa peter OP |_| Copies the contonts of the uppor nibble of dats ™ Taner OPH AC PeeEEEE ET = | wee om ports: DPHL ine he accumu Exchanges the contents of the accumulator with Exchange AC with DPH (AC) > (OPH) ‘the conlents of the upper nibble of data pointer: PHL Cones the contnts of he lower nibble of data Pe fewer EEE RELL | mee Bonlr OPHL ino te sccundlter | No. 3928—20/24
LC66354A, LC66356A, LC66358A D Copies te contents of te accumulator into tho mene’ PEE BEBEET | aa ara" [| Exchanges tho contants of fe accumulator wih AL Exchange AC with DPL (ac) 4 10° the conlens of the lower nibble of dala pointer OPAL Copies te contents of to accumuiao into the fe fmwremon [iti detefale [fs] | ane sen ee ey ee Oe |_| Copies the contents of the upper nile of ™ freworme Lefeysfafelifal = | “eee covery de poner DFxy ine he eecunvater Exchanges the conlonls of the accumulator with Exchonge AC wih DPX (49) 4 (Px) the contents of to upper nibble of aviary dala poner DPxy
4 Copies the conlenis of the sccuruisor ito he
1 Copies the conlonis of th lower nibble of
fre fone PR Ysisfeps tele eee uriay 6a por DPXY ino He sesundar | Exchanges the contens ol he accumultr with xay Exchange AC with OPY (ac) 4 (0Py) the contents of the lower nile of aviary data poner DPXY form forme Pelt lsfelepsp fees “nin eines |_| from [ower dele Dispel [eee | cont tet weiss oye | . Jumps witin the same bark fo the address Poe eo a 6 Po ‘peced by the program courier (he loner 12 , bits are replaced by immediats data Po to Py1) Jumps within the curenk page to he actress spea | 20. the edges stored at 4 Poa Rar eee vey | spac by te program counter (he lower 8 E ond AC in the curent page q , bis are oplced by the contents ol reser E PC3 to 0 & (AC) and tho accumula) P POI end 11 & 0, CAL er 8 P10 to 0 + Pyo 1 Po, | Calls a subroutine at the addtess apecied by e Mais) « (CF, ZF, Po te Pio ° PCI2 to 0}, SPH (SP) — 4 PoI2 to 6, PCI HOH Call eubrouine in the zero P PCS to 2 — Py fo Po, Calls a subroutine witin page 0 of bank 0 et Page ° Mase) — (CF, ZF, the odtoss species by Po t» P3 PCI2 to 0), SP SP - 4 ee Pushes the contents of he register spaced by ig and iy onlo the stack and decrements the stack poitor by 2 Push reg on Ma(SP) ; SP (SP) = 2 Tee Increments ho sisck ponir by 2, pops the conlels off the slack and moves the centers into be register spoctad by io and iy POP rag | Pop req off MSP) So RSI Poo eT | «ff | No. 3928—21/24
LC66354A, LC66356A, LC66358A q SP oS) + 4 eum trom a subroutine or an ilemupt aT Retum from subroutine Pom asPy fence routro, bul doos ect reste the state ios of bi 00 and cary flags SP & (57) «4, Raens om a subroutine of an ilerapl atl Relum trom inerupt subroutna PC © Mais. CF. Senco rovtre, including the sila of the zero | 2F, CF 2 & (MASP) and cary fags Tesls the bit speciied by immeriato data 'g PC7 to 0 « Py Pe P5 Py Py | and ty of the accumualer and, # so, branches BAB wos | Branch on AC bi Pe Py Poi (AC, @) = t witin tho same page to the address spociog by Po Pr tle Tesis to bit speciiod by immediate data ‘9 BNAe PCT 10 0 + Pr 5 Ps Py P5 | and 1; of he accumulser and, if not sot esr Branch on no AC bit Pye Pe Py Pol (AC, @} = 0 | branches wihin tho samo page to the adstess “ye specified by Po to P7 j Tesls tha bit speciiod by immediate data 'g PCT to 0 + Pr 6 Ps Py Py | and ty of memory Inesden HL and, il sat, BMI2 dor | Branch on M it 4 Pe Py Po ll MUL}, 2] = + | branches within tha same page to tha adscess 7 speciled by Po to Pr j . Tesis the bit species by immedat deta anmee PCT 0 0 + Pr 5 Ps Py Py | and ty of memory lecaben HL and, i rot st, adr Branch on oo M Bi ia Pa Ps Po i (ML), 2] = 0 | tranches within the same page to the adeeatt 7 spcifed by Po to P7 Tosis tho bit spacitod by immedaw sta ‘9 and 11 of the por speciied by the coninis of 1 un} . tho lower nile of data pointer OP HL and, i BP ader | Branch on pont bi ° |e Fe Pr By TOPS, alc 1 | baneas win to sane page the 7 ro 2 Py Po ua address spectiad by Po to Pz. When tollowed by bank instucfons, the interat conrolregsters se aso vald (readonly regs Tests the bit spectted by immediais data tg and 11 of the por speciad by tho conznts of : 7 poy | the lowor nile of data pointer DP. and, Bure | Branch on no pont ti P Fe Pe Boy OES, Bl co | 3 204 arches winn he sare oope to be 1 2 Pa Po i [POOPY adorass specitod by Po to P7. When ‘olowed Dy bank istuctons, the intaral conto rages | ae also valid (readonly registers 1 a Tests the cary fag and, it sot, branchos win BC der | Branch on CF P Pepe TIGA) eto | te Same nage b the adress spected by Po 1 2 Pr Po it ted to Py 1 Texts the camry fag and, if na set. branches BNC adr | Brench on no CF P Fe Pe DTI) Ot | win he sane pape to be adress species 7 m by Po to Py Taxis the zo fag and, it sot brarenes witin 82 adte | Branch on ZF Boe ho TO yet 8 | tho same page to tho adress spected by Fo Pa Py Pit 2F) = 1 bis
1 Tests the ze0 fag and, il not sel branches
BAZ addr | Braneh on 90 ZF P Beer Pe Teo. t 7 | win te sane page to te ads spcted 7 by Po i Py 1 Pr Pe. Tests tne tag speciled by no lo ng and, its, BFnt addr | Branch on tog tt P Beene Tere te | taehes win the same pogo the acess 5 2 Pa Poi speciied by Pp to Pr
1 Tests the flag spociiod by ng 10 79 and, if not
BNFr« | Branch on no Hag it P iH Pee aT doe tT? | a8 branches win the sane page he as 7 , 2 Pr Poi (Fn) © adéress speciied by Po to Py [>_[rrmewe [ele] fefefelefe] «| ee oan eee le | Loads the contnts of to input pom speciiod Input port lo AC AG & [PIDPL by te contors of the ower ribo of cate | ZF pointer OPHL into the eccumiator Loads the contents of the input port species Input pon lo M MUL) + {P(OPU) by the conten of the lower nibble of data poitar DPHL into memory lcaton HL Loads the conan of the input pot species [ros | ame we lel e[e fale fafel = | were 2 nna a 1 oy sense | (input ports 4 end § to E and . . Loads the conans ol input prs PA and PS [es | AG copectiny PEERE PELL | forage 8 imo ror E and he acral, respeetol No. 3928—22/24
LC66354A, LC66356A, LC66358A Loads the contents of the accumulator into the Outout AC 12 pon 1 + | poy © ac ‘ulpu pot species by fe coien's of the lower nibble of data pointer OPH. Loads be contri of mameryleaton HL ito Output M to port PIOPL) — [MIHU)) the ouput port specised by the lower nibble of data pointer OPH. Lods te contort of fa eccurulac ito he oust AC pat Ge erfepe stele = | ree ae ESS ee Outout E and AC to porte 4 _ «| Leeds th contr of rogitar & andthe [ors | and 5. respeciesly Pig} + (E), PIS) & (AC) sceumulater ilo ports P& and PS, respectively Sols the bil spacifed by immediate data tp and ‘SPB [PIDPL), 12] 9 ty of the output port specified by the lower nile of doa poirae DP. (ear fe taped by Irmece dala tp RP 12 {PIOPU, 2] H 0 ‘aed |; of the outpul port specilied by the lower nibble of data pointer OPHL ANDPOR | AND por wit immediate data FIPS 1 Po) (PD ee ere ne on i, ot then output ‘S00 19 1 |g and loads the resull into the port i 0 Takes the logical OF of the contents of the: ORDA | OR po wih mete daw | 1 > PiFs 1 Fob «= IPIPS ¥ + | cot specied by Po to Pa wih mediate daa ia ouput By : nwo 15 and leads th res ino te por Wiles e conti of memory leatone HL and WITMO- TIMERO + [MQ{HL}] and (AC) | HL + 1 and the contents of the accumulalor ilo the Siar 0 resad reget! Wiles te conan of register € and te [ioe oe ee a eG wt [amet || Funds te cones of he ner 9 cour ilo aria atit) and AC = (TMERO) | momory eatone KL and HL { and te eam Reads te canons ol fe Unet + coun: ito [row [owes PPP L STL | ieee man serewanc ee || Inlerrupt control instructions ‘Takes the logical OR of tho interrupt mask with ; ° inmesiats eal ip (and, kr BS fal a rate inp HGH 1 tn erases fe corpo eves iteais Takes logis! OR of to intrypt mate wih zu «| sable inoruat LOW ° eo. e (EOL) +4 ines aa 0 an 2, al oe inert ° ‘Takes the logical AND of the interrupt mask OH ie | Disable interupt HIGH ° EDK © (GOH) era ot sanpanen mes cae fo (aipoding o2ive HIGH intone Toes the loge AND of the inert mask OL a | Disabieinerupt LOW DL © (EDU) eee oe corresponding actve-LOW interrupts Wes te cons of raiser E ard he “ [meer PPB ERE EL | ee eee lacatinncidadanadashel Reads be conants cl he slack poi ino No. 3928—23/24
LC66354A, LC66356A, LC66358A lee Oe er fe PSS ees soe Teme TT t= PEREEEED ee perme TERED EEL femme feos [ CS CSan HG el fe [woe PEELE PEEL: eam women iid 1 1 Selects the memory bank specified bj [es few TTDI De] + Jrwnne Psamarsareees [| Note The range of values for i2 in the SB instruction varies according to the device. Refer to the LC66S Jump Optimizing Cross Assembler Manual, MM No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power contro! systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. WM Anyone purchasing any products described or contained herein for an above-mentioned use shall ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. {1 Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production, SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. No. 3928—24/24