LC662106A

LC665304A SANYO | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 26

Technical content

22897HA (OT) No. 5485-1/26 Overview The LC665304A, LC665306A, LC665308A, LC665312A, and LC665316A are 4-bit CMOS microcontrollers that integrate on a single chip all the functions required in a system controller, including ROM, RAM, I/O ports, a serial interface, 16-value comparator inputs, timers, interrupt functions, and an optional sub-oscillator circuit. These microcontrollers are available in a 48-pin package. Features and Functions

• On-chip ROM capacitiy of 4, 6, 8, 12, and 16 kilobytes, and an on-chip RAM capacity of 512 · 4 bits.
• Fully supports the LC66000 Series common instruction set (128 instructions).
• I/O ports: 42 pins
• A sub-oscillator circuit can be used (option) This circuit allows power dissipation to be reduced by operating at lower speeds.
• 8-bit serial interface: two circuits (can be connected in cascade to form a 16-bit interface)
• Instruction cycle time: 0.95 to 10 µs (at 3 to 5.5 V)
• Powerful timer functions and prescalers — Time limit timer, event counter, pulse width measurement, and square wave output using a 12-bit timer. — Time limit timer, event counter, PWM output, and square wave output using an 8-bit timer. — Time base function using a 12-bit prescaler.
• Powerful interrupt system with 8 interrupt factors and 8 interrupt vector locations. — External interrupts: 3 factors/3 vector locations — Internal interrupts: 5 factors/5 vector locations
• Flexible I/O functions 16-value comparator inputs, 20-mA drive outputs, inverter circuits, pull-up and open-drain circuits selectable as options.
• Optional runaway detection function (watchdog timer)
• 8-bit I/O functions
• Power saving functions using halt and hold modes.
• Packages: DIP48S, QIP48E (QFP48E)
• Evaluation LSIs: LC66599 (evaluation chip) + EVA800/850-TB662YXX2 LC66E5316(on-chip EPROM microcontroller) Package Dimensions unit: mm 3149-DIP48S unit: mm 3156-QFP48E 0.48 1.05 1.78 2.53 46.0 15.240.51min 3.8 5.1max 4.25 13.8 0.25 241 2548 Preliminary SANYO: DIP48S [LC665304A/665306A/665308A/665312A/665316A] (STAND OFF) 1.5 17.2 17.2 1.5 1.5 1.5 1.6 1.614.0 0.35 15.60.8 1.0 1.0 3.0max 2.70 0.1 0.15 11 2 1348 14.0 SANYO: QFP48E [LC665304A/665306A/665308A/665312A/665316A] LC665304A, 665306A, 665308A, 665312A, 665316A SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN Four-Bit Single-Chip Microcontrollers with 4, 6, 8, 12, and 16 KB of On-Chip ROM CMOS LSI No. 5485

Note: * Under development No. 5485-2/26 LC665304A, 665306A, 665308A, 665312A, 665316A Type No. No. of ROM capacity RAM Package Featurespins capacity LC66304A/306A/308A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66404A/406A/408A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66506B/508B/512B/516B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64A LC66354A/356A/358A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66354S/356S/358S 42 4 K/6 K/8 KB 512 W QFP44M LC66556A/558A/562A/566A 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E LC66354B/356B/358B 42 4 K/6 K/8 KB 512 W DIP42S QFP48E Low-voltage high-speed versions LC66556B/558B/562B/566B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E 3.0 to 5.5 V/0.92 µs LC66354C/356C/358C 42 4 K/6 K/8 KB 512 W DIP42S QFP48E 2.5 to 5.5 V/0.92 µs LC662104A/06A/08A 30 4 K/6 K/8 KB 384 W DIP30SD MFP30S LC662304A/06A/08A/12A/16A 42

4 K/6 K/8 K/12 K/16 KB512 W DIP42S QFP48E

LC662508A/12A/16A 64 8 K/12 K/16 KB 512 W DIP64S QFP64E LC665304A/06A/08A/12A/16A 48 4 K/6 K/8 K/12 K/16 KB512 W DIP48S QFP48E Dual oscillator support 3.0 to 5.5 V/0.95 µs LC66E308 42 EPROM 8 KB 512 W DIC42S QFC48 with window with window LC66P308 42 OTPROM 8 KB 512 W DIP42S QFP48E LC66E408 42 EPROM 8 KB 512 W DIC42S QFC48 with window with window LC66P408 42 OTPROM 8 KB 512 W DIP42S QFP48E LC66E516 64 EPROM 16 KB 512 W DIC64S QFC64 with window with window LC66P516 64 OTPROM 16 KB 512 W DIP64S QFP64E LC66E2108 * 30 EPROM 8 KB 384 W LC66E2316 42 EPROM 16 KB 512 W DIC42S QFC48 with window with window LC66E2516 64 EPROM 16 KB 512 W DIC64S QFC64 with window with window LC66E5316 52/48 EPROM 16 KB 512 W DIC52S QFC48 with window with window LC66P2108 * 30 OTPROM 8 KB 384 W DIP30SD MFP30S LC66P2316 * 42 OTPROM 16 KB 512 W DIP42S QFP48E LC66P2516 64 OTPROM 16 KB 512 W DIP64S QFP64E LC66P5316 48 OTPROM 16 KB 512 W DIP48S QFP48E OTP 4.0 to 5.5 V/0.95 µs Window evaluation versions 4.5 to 5.5 V/0.92 µs Window and OTP evaluation versions 4.5 to 5.5 V/0.92 µs On-chip DTMF generator versions 3.0 to 5.5 V/0.95 µs Low-voltage versions 2.2 to 5.5 V/3.92 µs Normal versions 4.0 to 6.0 V/0.92 µs

We recommend the use of reflow soldering techniques to solder-mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques). No. 5485-3/26 LC665304A, 665306A, 665308A, 665312A, 665316A DIP48S P20/SI0 P21/SO0 P22/SCK0 P23/INT0 P30/INT1 P31/POUT0 P32/POUT1 VSS OSC1 OSC2 VDD RES PE0/XT1 PE1/XT2 TEST P33/HOLD P40/INV0I P41/INV0O P42/INV1I P43/INV1O P50 P51 P52 P53/INT2 P13 P12 P11 P10 P03 P02 P01 P00 PD3/AN4/INV4O PD2/AN3/INV4I PD1/AN2/INV3O PD0/AN1/INV3I PC3/INV2O PC2/INV2I PC1 PC0 P83 P82 P81/DS1 P80/DS0 P63/PIN1 P62/SCK1 P61/SO1 P60/SI1 LC665304A 5306A 5308A 5312A 5316A QFP48E LC665304A 5306A 5308A 5312A 5316A 37P02 P01 1P32/POUT1 P00 2VSS PD3/AN4/INV4O 3OSC1 PD2/AN3/INV4I 4OSC2 PD1/AN2/INV3O 5VDD PD0/AN1/INV3I 6RES PC3/INV2O 7PE0/XT1 PC2/INV2I 8PE1/XT2 PC1 9TEST PC0 P33/HOLD P83 P40/INV0I P82 P41/INV0O

24 P81/DS1

Differences between the LC6653XX Series and the LC663XX Series For other differences and details, see the data sheets for the individual products. No. 5485-4/26 LC665304A, 665306A, 665308A, 665312A, 665316A Item LC6630X Series LC6635XB Series LC6653XX Series(Including the LC66599 evaluation chip) System differences 65536 cycles 16384 cycles 16384 cycles• Hardware wait time (number of About 64 ms at 4 MHz (Tcyc = 1 µs) About 16 ms at 4 MHz (Tcyc = 1 µs) About 16 ms at 4 MHz (Tcyc = 1 µs)cycles) when hold mode is cleared

• Value of timer 0 after a reset (Including the value after hold mode Set to FF0. Set to FFC. Set to FFC. is cleared)
• Inverter array None (Tools are handled with None Yesexternal devices.)
• Buffer array (data shaper circuit)None (Tools are handled with None Yesexternal devices.)
• Sub-oscillator None None Yes (option)
• Three-value inputs/comparator Yes Yes Only a 16-value comparatorinputs
• Three-state output from P31 None None Yesand P32
• Using P0 to clear halt mode In 4-bit groups In 4-bit groups Can be specified for each bit. None for INT3, INT4, and INT5.
• External extended interrupts (Tools are handled with external None for INT3, INT4, and INT5. None for INT3, INT4, and INT5. devices.) Shared with INT2 Shared with INT2 • Other P53 functions (Tools are handled with external Shared with INT2 (The logic is inverted.)devices.)
• 3.0 to 5.5 V/0.95 to 10 µs Differences in main characteristics• LC66304A/306A/308A • 3.0 to 5.5 V/0.92 to 10 µs (When the main oscillator is
• Operating power-supply voltage 4.0 to 6.0 V/0.92 t 10 µs • LC6635XA operating) operating)
• Pull-up resistors P0, P1, P4, and P5: about 3 to 10 kΩ P0, P1, P4, and P5: about 3 to 10 kΩ P0, P1, P4, and P5: about 100 kΩ
• P2 to P6 and PC: 15-V handling • P2 to P6 and PC: 15-V handlingAll ports: normal voltage handling• Port voltage handling • P0, P1, PD, PE: Normal voltage • P0, P1, PD, PE: Normal voltage (7-V handling provided)handling handling SYSTEM CONTROL RAM STACK (512W) SP E A ROM 4K/6K/8K/12K/16KB PC POUT0 SI0 SO0 SCK0 INT0 INT1, INT2 PIN1, POUT1 INVxO INV xI (x=0 to 4) FLAG INTERRUPT CONTROL MPX MPX TIMER1 MPX TIMER0 SERIAL I/O 0 PE PD PC E M R D P Y D P X D P L D P H P0 P1 P2 P3 P4 P5 P6 DS1 DS0 CZ ALU RES XT1 XT2 AN1 to 4 TEST OSC1 OSC2 HOLD ADC SI1 SO1 SCK1 SERIAL I/O 1 PRESCALER

No. 5485-5/26 LC665304A, 665306A, 665308A, 665312A, 665316A Pin I/O Overview Output driver type Options State after a Standby mode reset operation P00 P01 P02 P03 P10 P11 P12 P13 P20/SI0 P21/SO0 P22/SCK0 P23/INT0 P30/INT1 P31/POUT0 P32/POUT1 P33/HOLD P40/INV0I P41/INV0O P42/INV1I P43/INV1O I/O ports P00 to P03

• Input or output in 4-bit or 1-bit units
• P00 to P03 support the halt mode control function (This function can be specified in bit units.) I/O ports P10 to P13 Input or output in 4-bit or 1-bit units I/O ports P20 to P23
• Input or output in 4-bit or 1-bit units
• P20 is also used as the serial input SI0 pin.
• P21 is also used as the serial output SO0 pin.
• P22 is also used as the serial clock SCK0 pin.
• P23 is also used as the INT0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input. I/O ports P30 to P32
• Input or output in 3-bit or 1-bit units
• P30 is also used as the INT1 interrupt request.
• P31 is also used for the square wave output from timer 0.
• P32 is also used for the square wave and PWM output from timer 1.
• P31 and P32 also support 3-state outputs. Hold mode control input
• Hold mode is set up by the HOLD instruction when HOLD is low.
• In hold mode, the CPU is restarted by setting HOLD to the high level.
• This pin can be used as input port P33 along with P30 to P32.
• When the P33/HOLD pin is at the low level, the CPU will not be reset by a low level on the RES pin. Therefore, applications must not set P33/HOLD low when power is first applied. I/O ports P40 to P43
• Input or output in 4-bit or 1-bit units
• Input or output in 8-bit units when used in conjunction with P50 to P53.
• Can be used for output of 8-bit ROM data when used in conjunction with P50 to P53.
• Dedicated inverter circuit (option) I/O I/O I/O I/O I I/O
• Pch: Pull-up MOS type
• Nch: Intermediate sink current type
• Pch: Pull-up MOS type
• Nch: Intermediate sink current type
• Pch: CMOS type
• Nch: Intermediate sink current type
• Nch: +7-V handling when OD option selected
• Pch: CMOS type
• Nch: Intermediate sink current type
• Nch: +7-V handling when OD option selected
• Pch: Pull-up MOS type
• CMOS type when the inverter circuit option is selected
• Nch: Intermediate sink current type
• Pull-up MOS or Nch OD output
• Output level on reset
• Pull-up MOS or Nch OD output
• Output level on reset CMOS or Nch OD output CMOS or Nch OD output
• Pull-up MOS or Nch OD output
• Output level on reset
• Inverter circuit High or low (option) High or low (option) H H High or low or inverter I/O (option) Hold mode: Output off Hold mode: Output off Hold mode: Output off Hold mode: Output off Hold mode: Port output off, inverter output off Halt mode: Port output retained, inverter output continues Halt mode: Output retained Halt mode: Output retained Halt mode: Output retained Halt mode: Output retained Continued on next page.

No. 5485-6/26 LC665304A, 665306A, 665308A, 665312A, 665316A Pin I/O Overview Output driver type Options State after a Standby mode reset operation P50 P51 P52 P53/INT2 P60/SI1 P61/SO1 P62/SCK1 P63/PIN1 P80/DS0 P81/DS1 P82 P83 PC0 PC1 PC2/INV2I PC3/INV2O PD0/AN1/ INV3I PD1/AN2/ INV3O PD2/AN3 INV4I PD3/AN4/ INV4O PE0/XT1 PE1/XT2 I/O ports P50 to P53

• Input or output in 4-bit or 1-bit units
• Input or output in 8-bit units when used in conjunction with P40 to P43.
• Can be used for output of 8-bit ROM data when used in conjunction with P40 to P43.
• P53 is also used as the INT2 interrupt request. I/O ports P60 to P63
• Input or output in 4-bit or 1-bit units
• P60 is also used as the serial input SI1 pin.
• P61 is also used as the serial output SO1 pin.
• P62 is also used as the serial clock SCK1 pin.
• P63 is also used for the event count input to timer 1. Dedicated output ports P80 to P83
• Output in 4-bit or 1-bit units
• The contents of the output latch are input using input instructions.
• P80 is a buffer input or a zero-cross buffer input and P81 is a buffer input (options). I/O ports PC0 to PC3
• Output in 4-bit or 1-bit units
• Dedicated inverter circuits (option) Dedicated input ports PD0 to PD3
• Can be switched in software to function as 16-value analog inputs.
• Dedicated inverter circuits (option) Dedicated input ports and sub-oscillator connections I/O I/O O I/O I I
• Pch: Pull-up MOS type
• Nch: Intermediate sink current type
• Pch: MOS type
• Nch: Intermediate sink current type
• Nch: +7-V handling when OD option selected (P61 and P63 only)
• Pch: CMOS type
• Nch: Intermediate sink current type
• Pch: CMOS type
• Nch: Intermediate sink current type
• Inverter circuits can be selected as options.
• Pch: CMOS type
• Nch: Intermediate sink current type
• Pull-up MOS or Nch OD output
• Output level on reset
• CMOS or Nch OD output
• CMOS or Pch OD output
• Output level at reset
• Buffer circuit
• Zero-cross detector buffer circuit
• CMOS or Nch OD output
• Inverter circuit Inverter circuit Sub-oscillator/port PE selection High or low (option) H High or low Buffered I/O (option) H Normal input or inverter I/O (option) Selected as an option Hold mode: Output off Hold mode: Output off Halt mode: Output retained Hold mode: Port output off, buffer output off Hold mode: Port output off, inverter output off Inverter:
• Hold mode: Output off
• Halt mode: Output continues Sub- oscillator: Hold mode: Oscillator stopped Halt mode: Oscillator operates Halt mode: Port output retained, inverter output continues. Halt mode: Port output retained, buffer output continues with the buffer resistor off. Halt mode: Output retained Continued on next page.

Continued from preceding page. Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD . CMOS output: Complementary output. OD output: Open-drain output. User Options 1. Port 0, 1, 4, 5, and 8 output level at reset option The output levels at reset for I/O ports 0, 1, 4, 5, and 8, in independent 4-bit groups, can be selected from the following two options. 2. Oscillator circuit options

• Main clock Note: There is no RC oscillator option.
• Sub-clock No. 5485-7/26 LC665304A, 665306A, 665308A, 665312A, 665316A Pin I/O Overview Output driver type Options State after a Standby mode reset operation OSC1 OSC2 RES TEST VDD VSS System clock oscillator connections When an external clock is used, leave OSC2 open and connect the clock signal to OSC1. System reset input When the P33/HOLD pin is at the high level, a low level input to the RES pin will initialize the CPU. CPU test pin This pin must be connected to V SS during normal operation. Power supply pins I O I I Ceramic oscillator or external clock selection Selected as an option Hold mode: Oscillator stopped Halt mode: Oscillator operates Option Circuit Conditions and notes 1. External clock 2. Ceramic oscillator The input has Schmitt characteristics Option Circuit Conditions and notes 1. Ports PE0 and PE1

2 Sub-oscillator

(crystal oscillator) Option Conditions and notes 1. Output high at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group 2. Output low at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group OSC1 OSC1 OSC2 Ceramic oscillator DSB Input data XT1 XT2 Crystal oscillator

1. Watchdog timer option A runaway detection function (watchdog timer) can be selected as an option. 4. Port output type options

• The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be selected individually from the following two options.
• One of the following two options can be selected for P8, in bit units. No. 5485-8/26 LC665304A, 665306A, 665308A, 665312A, 665316A Option Circuit Conditions and notes 1. Open-drain output 2. Output with built-in pull-up resistor The port P2, P3, P5, and P6 inputs have Schmitt characteristics. The port P2, P3, P5, and P6 inputs have Schmitt characteristics. The CMOS outputs (ports P2, P3, P6, and PC) and the pull-up MOS outputs (P0, P1, P4, and P5) are distinguished by the drive capacity of the p-channel transistor. Option Circuit Conditions and notes 1. Open-drain output 2. Output with built-in pull- down resistor (CMOS output) DSB Output data Input data DSB Output data Input data DSB Output data DSB Output data

1. Inverter array circuit option One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PC2/PC3, PD0/PD1, and PD2/PD3. (PDs do not use option 1 because they are dedicated to inputs) No. 5485-9/26 LC665304A, 665306A, 665308A, 665312A, 665316A Option Circuit Conditions and notes 1. Normal port I/O circuit 2. Inverter I/O circuit When the open-drain output type is selected When the built-in pull-up resistor output type is selected The CMOS outputs (PC) and the pull-up MOS outputs (P4) are distinguished by the drive capacity of the p-channel transistor. If this option is selected, The I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected. DSB Output data Input data DSB Output data Input data DSB DSB Input Output Output data high Input data Output data high Input data

1. Buffer array circuit option In addition to normal port output, one of the following two options may also be selected for P80 and P81. No. 5485-10/26 LC665304A, 665306A, 665308A, 665312A, 665316A Option Circuit Conditions and notes 1. Normal port output 2. Buffer input (P80) and buffer output (P81) circuits 3. Buffer input (P80) and buffer output (P81) circuits with built-in zero-cross detection circuits When the open-drain output type is selected If this option is selected, the I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected. If this option is selected, the I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected. When the built-in pull-down resistor output type is selected (CMOS output) DSB Output data DSB Output data DSB P80 P81 Output data low Output data low DSB P80 P81 Output data low Output data low

LC665316 Series Option Data Area and Definitions LC665304A, 665306A, 665308A, 665312A, 665316A ROM area Bit Option specified Option/data relationship 7P 5 Output level at reset 0 = high level, 1 = low level 6P 4

5 Sub-oscillator option 0 = port PE, 1 = crystal oscillator

4 Oscillator option 0 = external clock, 1 = ceramic oscillator

2 P1 Output level at reset 0 = low level, 1 = high level

0 Watchdog timer option 0 = none, 1 = yes (present)

7 P13

6 P12

Output type 0 = OD, 1 = PU

5 P11

4 P10

3 P03

2 P02

Output type 0 = OD, 1 = PU

1 P01

0 P00

7 Unused This bit must be set to 0.

6 P32

5 P31 Output type 0 = OD, 1 = PU

4 P30

3 P23

2 P22

Output type 0 = OD, 1 = PU

1 P21

0 P20

7 P53

6 P52

Output type 0 = OD, 1 = PU

5 P51

4 P50

3 P43

2 P42

Output type 0 = OD, 1 = PU

1 P41

0 P40

Unused This bit must be set to 0. 3FF4H

3 P63

2 P62

Output type 0 = OD, 1 = PU

1 P61

0 P60

Unused This bit must be set to 0. 3FF5H

3 P83

2 P82

Output type 0 = OD, 1 = PD

1 P81

0 P80

Unused This bit must be set to 0. 3FF6H Unused This bit must be set to 0. Continued on next page.

Continued from preceding page. No. 5485-12/26 LC665304A, 665306A, 665308A, 665312A, 665316A ROM area Bit Option specified Option/data relationship Unused This bit must be set to 0. 3FF7H

3 PC3

2 PC2

Output type 0 = OD, 1 = PU

1 PC1

0 PC0

7 Unused This bit must be set to 1.

6 Buffer output 0 = used, 1 = none

5 Buffer output with zero-cross bias input 0 = used, 1 = none

4 PD3

3 PD1

2 PC3 Inverter output 0 = inverter output, 1 = none

1 P43

0 P41

Unused This bit must be set to 0. 3FF9H Unused This bit must be set to 0. Unused This bit must be set to 0. 3FFAH Unused This bit must be set to 0. Unused This bit must be set to 0. 3FFBH Unused This bit must be set to 0. Unused This bit must be set to 0. 3FFCH Unused This bit must be set to 0. 3FFDH Reserved. Must be set to predefined data values. This data is generated by the assembler. 3 If the assembler is not used, set this data to ‘00’. Continued on next page.

Continued from preceding page. Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that pin apply. 2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed. 3. Sink current (Applies to P8 and PD when either the CMOS output specifications or the inverter array specifications have been selected.) 4. Source current (Applies to all pins except P8 and PD for which the pull-up output specifications, the CMOS output specifications, or the inverter array specifications have been selected. Applies to PD pins for which the inverter array specifications have been selected.) Contact your Sanyo representative for the electrical characteristics when the inverter array or buffer array options are specified. 5. We recommend the use of reflow-soldering techniques to solder-mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering spray techniques). No. 5485-13/26 LC665304A, 665306A, 665308A, 665312A, 665316A ROM area Bit Option specified Option/data relationship 3FFEH Reserved. Must be set to predefined data values. This data is generated by the assembler. 3 If the assembler is not used, set this data to ‘00’. 3FFFH Reserved. Must be set to predefined data values. This data is generated by the assembler. 3 If the assembler is not used, set this data to ‘00’. Parameter Symbol Conditions Ratings Unit Note Maximum supply voltage V DD max V DD –0.3 to +7.0 V VIN1 P2, P3 (except for the P33/HOLD pin), –0.3 to +7.0 V 1 Input voltage P61, and P63 VIN2 All other inputs –0.3 to V DD + 0.3 V 2 VOUT 1 P2, P3 (except for the P33/HOLD pin), –0.3 to +7.0 V 1 Output voltage P61, and P63 VOUT 2 All other inputs –0.3 to V DD + 0.3 V 2 ION 1 P0, P1, P2, P3 (except for the P33/HOLD pin), 20 mA 3P4, P5, P6, P8, PC, PD1, PD3 Output current per pin –IOP 1 P0, P1, P4, P5 2 mA 4 –IOP 2 P2, P3 (except for the P33/HOLD pin), 4m A 4P6,P8, and PC –IOP 3 P41, P43, PC3, PD1, PD3, P81 10 mA 4 S ION 1 P4, P5, P6, P8, PC 75 mA 3 S ION 2 P0, P1, P2, P3 (except for the P33/HOLD pin), 75 mA 3 Total pin current PD1, PD3 S IOP 1 P4, P5, P6, P8, PC 25 mA 4 S IOP 2 P0, P1, P2, P3 (except for the P33/HOLD pin), 25 mA 4PD1, PD3 Allowable power dissipation Pd max Ta = –30 to +70°C: DIP48S (QFP48E) 600 (430) mW 5 Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C

Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified. Note: 1. Applies to pins with open-drain specifications. However, VIH2 applies to the P33/HOLD pin. When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins. 2. PC port pins with CMOS output specifications cannot be used as input pins. Contact your Sanyo representative for the allowable operating ranges for P4, PC, and PD when the inverter array is used, and for P8 when the buffer array is used. 3. Applies to pins with open-drain specifications. However, V IL3 applies to the P33/HOLD pin. P2, P3, and P6 port pins with CMOS output specifications cannot be used as input pins. No. 5485-14/26 LC665304A, 665306A, 665308A, 665312A, 665316A Parameter Symbol Conditions min typ max Unit Note Operating supply voltage V DD VDD 3.0 5.5 V Memory retention supply voltage VDD HV DD : During hold mode 1.8 5.5 V VIH1 P2, P3 (except for the P33/HOLD pin), 0.8 VDD +7.0 V 1P61, and P63: N-channel output transistor off Input high-level voltage V IH2 P33/HOLD, P60, P62, RES, OSC1: 0.8 VDD VDD V1N-channel output transistor off VIH3 P0, P1, P4, P5, PC, PD, PE: 0.8 VDD VDD V2N-channel output transistor off VIL1 P2, P3 (except for the P33/HOLD pin), P6, VSS 0.2 VDD V3RES, and OSC1: N-channel output transistor off Input low-level voltage VIL2 P0, P1, P4, P5, PC, PD, PE, TEST: VSS 0.2 VDD V2N-channel output transistor off VIL3 P33/HOLD: V DD = 1.8 to 5.5 V V SS 0.2 VDD V When the main oscillator is operating 0.4 4.20 MHz Operating frequency fop (10) (0.95) (µs ) (instruction cycle time) (Tcyc) When the sub-oscillator is operating 30 32.768 100 kHz [External clock input conditions] OSC1: Defined by Figure 1. Input the clock Frequency f ext signal to OSC1 and leave OSC2 open. 0.4 4.20 MHz(External clock input must be selected as the oscillator circuit option.) OSC1: Defined by Figure 1. Input the clock Pulse width t extH, textL signal to OSC1 and leave OSC2 open. 100 ns(External clock input must be selected as the oscillator circuit option.) OSC1: Defined by Figure 1. Input the clock Rise and fall times t extR, textF signal to OSC1 and leave OSC2 open. 30 ns(External clock input must be selected as the oscillator circuit option.)

Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified. No. 5485-15/26 LC665304A, 665306A, 665308A, 665312A, 665316A Parameter Symbol Conditions min typ max Unit Note P2, P3 (except for the P33/HOLD pin), IIH1 P61, and P63: V IN = +7 V, with the output 5.0 µA 1 Nch transistor off P0, P1, P4, P5, P6, PC, OSC1, RES, and Input high-level current IIH2 P33/HOLD (Does not apply to PD, PE, PC2, 1.0 µA 1PC3, P61, and P63.): VIN = VDD , with the output Nch transistor off IIH3 PD, PE, PC2, PC3: VIN = VDD , 1.0 µA 1with the output Nch transistor off IIL1 Input ports other than PD, PE, PC2, and PC3: –1.0 µA 2VIN = VSS , with the output Nch transistor off IIL2 PC2, PC3, PD, PE0: VIN = VSS , –1.0 µA 2Input low-level current with the output Nch transistor off PE1 (When used as a port; does not apply IIL4 when the sub-oscillator option is selected.): 20 µA 1 VIN = VSS P2, P3 (except for the P33/HOLD pin), VDD – 1.0 Output high-level voltage V OH 1 P6, P8, and PC: IOH = –1 mA P2, P3 (except for the P33/HOLD pin), VDD – 0.5P6, P8, and PC: IOH = –0.1 mA Value of the output pull-up resistor RPO P0, P1, P4, P5 30 100 150 kΩ 4 VOL 1 P0, P1, P2, P3, P4, P5, P6, P8, and PC 0.4 V 5 Output low-level voltage (except for the P33/HOLD pin): IOL = 1.6 mA VOL 2 P0, P1, P2, P3, P4, P5, P6, P8, and PC 1.5 V(except for the P33/HOLD pin): IOL = 8 mA IOFF 1 P2, P3, P61, P63: VIN = +7 V 5.0 µA 6 Output off leakage current I OFF 2 Does not apply to P2, P3, P61, P63, and P8.: 1.0 µA 6VIN = VDD IOFF 3 P8: V IN = VSS –1.0 µA 7 [Schmitt characteristics] Hysteresis voltage V HyS 0.1 VDD V High-level threshold voltage Vt H P2, P3, P5, P6, OSC1 (EXT), RES 0.5 V DD 0.8 VDD V Low-level threshold voltage Vt L 0.2 VDD 0.5 VDD V [Ceramic oscillator] Oscillator frequency f CF OSC1, OSC2: Figure 2, 4 MHz 4.0 MHz Oscillator stabilization time f CFS Figure 3, 4 MHz 10.0 ms [Crystal oscillator] Oscillator frequency f XT XT1, XT2: Figure 2, when the sub-oscillator 32.768 kHzoption is selected, 32 kHz Oscillator stabilization time f XTS Figure 3, when the sub-oscillator option is 1.0 5.0 sselected, 32 kHz [Serial clock] Cycle time Input tCKCY 0.9 µs Output 2.0 Tcyc Low-level and high-level Input t CKL 0.4 µs pulse widths Output t CKH 1.0 Tcyc Rise an fall times Output t CKR , tCKF 0.1 µs [Serial input] Data setup time t ICK 0.3 µs Data hold time t CKI 0.3 µs [Serial output] SO0, SO1: With the timing of Figure 5 and Output delay time t CKO the test load of Figure 5. Stipulated with respect 0.3 µs to the falling edge (fl) of SCK0 or SCK1. SI0, SI1: With the timing of Figure 4. Stipulated with respect to the rising edge (›) of SCK0 or SCK1. SCK0, SCK1: With the timing of Figure 4 and the test load of Figure 5. Continued on next page.

Continued from preceding page. Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the CMOS output specifications are selected.When the port option is selected for PE. 2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected. 3. With the output Nch transistor off for CMOS output specification pins. (Also applies when the Pch open-drain option is selected for P8.) 4. With the output Nch transistor off for pull-up output specification pins. 5. When CMOS output specifications are selected for P8. 6. With the output Nch transistor off for open-drain output specification pins. 7. With the output Pch transistor off for open-drain output specification pins. 8. Reset state Comparator Characteristics at Ta = –30 to +70°C, VSS = 0 V Note: 1. Does not include the quantization error. Figure 1 External Clock Input Waveform No. 5485-16/26 LC665304A, 665306A, 665308A, 665312A, 665316A Parameter Symbol Conditions min typ max Unit Note [Pulse conditions] INT0: Figure 6, conditions under which the INT0 INT0 high and low-level t IOH, tIOL interrupt can be accepted, conditions under 2 Tcycwhich the timer 0 event counter or pulse width measurement input can be accepted High and low-level pulse widths tIIH, tIIL INT1: Figure 6, conditions under which 2 Tcycfor interrupt inputs other than INT0 the corresponding interrupt can be accepted PIN1 high and low-level tPINH , tPINL PIN1: Figure 6, conditions under which the 2 Tcycpulse widths timer 1 event counter input can be accepted RES high and low-level tRSH , tRSL RES: Figure 6, conditions under which reset 3 Tcycpulse widths can be applied. VDD : 4-MHz ceramic oscillator 4.0 8.0 mA Operating current drain I DD OP VDD : 4-MHz ceramic oscillator, VDD = 3.0 to 4.0 V 3.0 5.0 8 VDD : 4-MHz external clock 4.0 8.0 mA VDD : 4-MHz ceramic oscillator 2.0 3.5 mA VDD : 4-MHz ceramic oscillator, VDD = 3.0 to 4.0 V 1.0 2.0 VDD : 4-MHz external clock 2.0 3.5 mA Halt mode current drain I DDHALT VDD : 32 kHz (main oscillator stopped), 10 100sub-oscillator: crystal µA VDD : 32 kHz (main oscillator stopped), 10 50sub-oscillator: crystal, VDD = 3.0 to 4.0 V Hold mode current drain I DDHOLD VDD : VDD = 1.8 to 5.5 V 0.01 10 µA Parameter Symbol Conditions min typ max Unit Note Threshold voltage V THCM VDD = 3.0 to 5.5 V V SS VDD V Input voltage V INCM AN1 to AN4: VDD = 3.0 to 5.5 V V SS VDD V Conversion time T CCM VDD = 3.0 to 5.5 V 20 ms VDD = 4.0 to 5.5 V 30 µs textL OPEN (OSC2)OSC1 textRtextF VSS VDD 0.2VDD 0.8VDD 1/fext textH External Clock

Figure 2 Ceramic Oscillator Circuit Figure 3 Oscillator Stabilization Period Table 1 Guaranteed Ceramic Oscillator Constants External capacitor type Table 2 Guaranteed Crystal Oscillator Constants Figure 4 Serial I/O Timing Figure 5 Timing Load Figure 6 Input Timing for the INT0, INT1, INT2, PIN1, and RES pins No. 5485-17/26 LC665304A, 665306A, 665308A, 665312A, 665316A External capacitor type Built-in capacitor type

4 MHz C1 = 33 pF ± 10% 4 MHz

(Murata Mfg. Co., Ltd.) C2 = 33 pF ± 10% (Murata Mfg Co., Ltd) Rd = 220 Ω ± 5% CSA4.00MG Rd = 220 Ω ± 5% CST4.00MG (Kyocera Corporation) C2 = 33 pF ± 10% (Kyocera Corporation) KBR4.0MS Rd = 0 Ω KBR4.0MES 32 kHz C1 = 18 pF ± 10% (Seiko Epson) C2 = 18 pF ± 10% C-002RX Rd = 470 kΩ ± 5% tI0H tI1H tPINH tRSH tI0L tI1L tPINL tRSL 0.8VDD 0.2VDD OTE OSC2OSC1 C1 C2 Rd XT2 Crystal oscillatorI XT1 C1 C2 Rd Ceramic oscillator /n00 /n01/n03 VDD OSC 0V Oscillator unstable period tCFS Stable oscillation Operating VDD minimum value tICK tCKI tCKL tCKR tCKCY tCKH tCKF 0.8VDD (input) VDD -1 (output)0.2VDD (input) SCK0 SCK1 SI0 SI1 SO0 SO1 0.4VDD (output) 0.8VDD 0.2VDD tCK0 VDD -1 0.4VDD C=50pF TEST point R=1kΩ O

LC66XXXX Series Instruction Table (by function) Abbreviations: AC: Accumulator E: E register CF: Carry flag ZF: Zero flag HL: Data pointer DPH, DPL XY: Data pointer DPX, DPY M: Data memory M (HL): Data memory pointed to by the DPH, DPL data pointer M (XY): Data memory pointed to by the DPX, DPY auxiliary data pointer M2 (HL): Two words of data memory (starting on an even address) pointed to by the DPH, DPL data pointer SP: Stack pointer M2 (SP): Two words of data memory pointed to by the stack pointer M4 (SP): Four words of data memory pointed to by the stack pointer in: n bits of immediate data t2: Bit specification PCh: Bits 8 to 11 in the PC PCm: Bits 4 to 7 in the PC PCl: Bits 0 to 3 in the PC Fn: User flag, n = 0 to 15 TIMER0: Timer 0 TIMER1: Timer 1 SIO: Serial register P: Port P (i4): Port indicated by 4 bits of immediate data INT: Interrupt enable flag ( ), [ ]: Indicates the contents of a location ‹ : Transfer direction, result : Exclusive or : Logical and : Logical or +: Addition –: Subtraction —: Taking the one's complement No. 5485-18/26 LC665304A, 665306A, 665308A, 665312A, 665316A t2 11 10 01 00 Bit 2 3 22 21 20

No. 5485-19/26 LC665304A, 665306A, 665308A, 665312A, 665316A Continued on next page. Instruction code Affected Mnemonic Operation Description status Note D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 bits [Accumulator manipulation instructions] CLA Clear AC 1000 0000 1 1 AC ‹ 0 Clear AC to 0. ZF Has a vertical (Equivalent to LAI 0.) skip function. DAA Decimal adjust AC 1100 1111 22 AC ‹ (AC) + 6 Add six to AC. ZFin addition 0010 0110 (Equivalent to ADI 6.) Decimal adjust AC 1100 1111 AC ‹ (AC) + 10 DAS in subtraction 0010 1010 2 2 (Equivalent to Add 10 to AC. ZF ADI 0AH.) CLC Clear CF 0001 1110 1 1 C F ‹ 0 Clear CF to 0. CF STC Set CF 0001 1111 1 1 C F ‹ 1 Set CF to 1. CF CMA Complement AC 0001 1000 1 1 A C ‹ (AC) Take the one’s complement ZFof AC. IA Increment AC 0001 0100 1 1 A C ‹ (AC) + 1 Increment AC. ZF, CF DA Decrement AC 0010 0100 1 1 A C ‹ (AC) – 1 Decrement AC. ZF, CF Rotate AC right AC 3 ‹ (CF), RAR through CF 0001 0000 1 1 ACn ‹ (ACn + 1), Shift AC (including CF) right. CF CF ‹ (AC0) Rotate AC left AC 0 ‹ (CF), RAL through CF 0000 0001 1 1 ACn + 1 ‹ (ACn), Shift AC (including CF) left. CF, ZF CF ‹ (AC3) TAE Transfer AC to E 0100 0101 1 1 E ‹ (AC) Transfer the contents of AC to E. TEA Transfer E to AC 0100 0110 1 1 A C ‹ (E) Transfer the contents of E to AC. ZF XAE Exchange AC with E 0100 0100 1 1 (AC) « (E) Exchange the contents of AC and E. [Memory manipulation instructions] IM Increment M 0001 0010 1 1 M (HL) ‹ Increment M (HL). ZF, CF[M (HL)] + 1 DM Decrement M 0010 0010 1 1 M (HL) ‹ Decrement M (HL). ZF, CF[M (HL)] – 1 IMDR i8 Increment M direct 1100 0111 2 2 M (i8) ‹ [M (i8)] + 1 Increment M (i8). ZF, CFI7 I6 I5 I4 I3 I2 I1 I0 DMDR i8 Decrement M direct 1100 0011 2 2 M (i8) ‹ [M (i8)] – 1 Decrement M (i8). ZF, CFI7 I6 I5 I4 I3 I2 I1 I0 SMB t2 Set M data bit 0000 11t 1 t0 1 1 [M (HL), t2] ‹ 1 Set the bit in M (HL) specified by t0 and t1 to 1. RMB t2 Reset M data bit 0010 11t 1 t0 1 1 [M (HL), t2] ‹ 0 Clear the bit in M (HL) ZFspecified by t0 and t1 to 0. [Arithmetic, logic and comparison instructions] Add the contents of AC and AD Add M to AC 0000 0110 1 1 AC ‹ (AC) + M (HL) as two’s complement ZF, CF[M (HL)] values and store the result in AC. Add the contents of AC and ADDR i8 Add M direct to AC 1100 1001 2 2 AC ‹ (AC) + [M (i8)]M (i8) as two’s complement ZF, CFI7 I6 I5 I4 I3 I2 I1 I0 values and store the result in AC. Add the contents of AC, ADC Add M to AC with CF 0000 0010 1 1 AC ‹ (AC) + M (HL) and C as two’s ZF, CF[M (HL)] + (CF) complement values and store the result in AC. Add the contents of AC and ADI i4 Add immediate data 1100 1111 22 AC ‹ (AC) + the immediate data as two’s ZFt o A C 0010 I 3 I2 I1 I0 I3, I2, I1, I0 complement values and store the result in AC. Subtract the contents of AC CF will be zero if SUBC Subtract AC from M 0001 0111 1 1 AC ‹ [M (HL)] – and CF from M (HL) as two’s ZF, CF there was a with CF (AC) – (CF) complement values and store borrow and one the result in AC. otherwise. And M with AC then AC ‹ (AC) Take the logical and of AC ANDA store AC 0000 0111 1 1 [M (HL)] and M (HL) and store the ZF result in AC. Or M with AC then AC ‹ (AC) Take the logical or of AC and ORA store AC 0000 0101 1 1 [M (HL)] M (HL) and store the result ZF in AC. Number of bytes Number of cycles

Continued from preceding page. No. 5485-20/26 LC665304A, 665306A, 665308A, 665312A, 665316A Continued on next page. Instruction code Affected Mnemonic Operation Description status Note D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 bits [Arithmetic, logic and comparison instructions] Exclusive or M with AC ‹ (AC) Take the logical exclusive or EXL AC then store AC 0001 0101 1 1 [M (HL)] of AC and M (HL) and store ZF the result in AC. And M with AC then M (HL) ‹ (AC) Take the logical and of AC ANDM store M 0000 0011 1 1 [M (HL)] and M (HL) and store the ZF result in M (HL). Or M with AC then M (HL) ‹ (AC) Take the logical or of AC and ORM store M 0000 0100 1 1 [M (HL)] M (HL) and store the result ZF in M (HL). Compare the contents of AC and M (HL) and set or clear CF and ZF according to the result. CM Compare AC with M 0001 0110 1 1 [ M (HL)] + (AC) + 1 ZF, CF Compare the contents of AC and the immediate data I

3 I2 I1 I0 and set or clear CF

and ZF according to the result. CI i4 Compare AC with 1100 1111 22 I 3 I2 I1 I0 + (AC) + 1 ZF, CFimmediate data 1010 I 3 I2 I1 I0 ZF ‹ 1 Compare the contents of DP L CLI i4 Compare DP L with 1100 1111 22 if (DPL) = I3 I2 I1 I0 with the immediate data. ZFimmediate data 1011 I 3 I2 I1 I0 ZF ‹ 0 Set ZF if identical and clear if (DPL) ≠ I3 I2 I1 I0 ZF if not. ZF ‹ 1 if (AC, t2) = [M (HL), Compare the corresponding CMB t2 Compare AC bit with1100 1111 22 t2] bits specified by t0 and t1 in ZFM data bit 1101 00t 1 t0 ZF‹ 0 AC and M (HL). Set ZF if if (AC, t2) ≠ [M (HL), identical and clear ZF if not. t2] [Load and store instructions] LAE Load AC and E from 0101 1100 1 1 AC ‹ M (HL), Load the contents of M2 (HL) M2 (HL) E ‹ M (HL + 1) into AC, E. LAI i4 Load AC with 1000 I

3 I2 I1 I0 1 1 AC ‹ I3 I2 I1 I0

Load the immediate data ZF Has a vertical immediate data into AC. skip function LADR i8 Load AC from M 1100 0001 2 2 AC ‹ [M (i8)] Load the contents of M (i8) ZFdirect I 7 I6 I5 I4 I3 I2 I1 I0 into AC. S Store AC to M 0100 0111 1 1 M (HL) ‹ (AC) Store the contents of AC into M (HL). SAE Store AC and E to 0101 1110 1 1 M (HL) ‹ (AC) Store the contents of AC, E M2 (HL) M (HL + 1) ‹ (E) into M2 (HL). Load the contents of M (reg) into AC. The reg is either HL or XY Load AC from depending on t LA reg M (reg) 0100 10t 0 0 1 1 AC ‹ [M (reg)] ZF Number of bytes Number of cycles Magnitude CF ZFcomparison [M (HL)] > (AC) 0 0 [M (HL)] = (AC) 1 1 [M (HL)] < (AC) 1 0 Magnitude CF ZFcomparison I3 I2 I1 I0 > AC 0 0 I3 I2 I1 I0 = AC 1 1 I3 I2 I1 I0 < AC 1 0 reg T 0 HL 0 XY 1

Continued from preceding page. No. 5485-21/26 LC665304A, 665306A, 665308A, 665312A, 665316A Continued on next page. Instruction code Affected Mnemonic Operation Description status Note D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 bits [Load and store instructions] Load the contents of M (reg) into AC. (The reg is either HL ZF is set Load AC from M (reg) AC ‹ [M (reg)] or XY.) Then increment the according to the LA reg, Ithen increment reg 0100 10t 0 11 2 D P L ‹ (DPL) + 1 contents of either DPL or DPY. ZF result of or DPY ‹ (DPY) + 1 The relationship between t0 incrementing and reg is the same as that DP L or DPY. for the LA reg instruction. Load the contents of M (reg) into AC. (The reg is either HL ZF is set Load AC from M (reg) AC ‹ [M (reg)] or XY.) Then decrement the according to the LA reg, Dthen decrement reg 0101 10t 0 11 2 D P L ‹ (DPL) – 1 contents of either DPL or DPY. ZF result of or DPY ‹ (DPY) – 1 The relationship between t0 decrementing and reg is the same as that DP L or DPY. for the LA reg instruction. Exchange the contents of M (reg) and AC. The reg is either HL or XY Exchange AC with depending on t XA reg M (reg) 0100 11t 0 0 1 1 (AC) « [M (reg)] Exchange the contents of M (reg) and AC. (The reg is ZF is set Exchange AC with (AC) « [M (reg)] either HL or XY.) Then according to the XA reg, I M (reg) then 0100 11t 0 11 2 D P L ‹ (DPL) + 1 increment the contents of ZF result of increment reg or DP Y ‹ (DPY) + 1 either DPL or DPY. The incrementing relationship between t0 and DP L or DPY.reg is the same as that for the XA reg instruction. Exchange the contents of M (reg) and AC. (The reg is ZF is set Exchange AC with (AC) « [M (reg)] either HL or XY.) Then according to the XA reg, D M (reg) then 0101 11t 0 11 2 D P L ‹ (DPL) – 1 decrement the contents of ZF result of decrement reg or DP Y ‹ (DPY) – 1 either DPL or DPY. The decrementing relationship between t0 and DP L or DPY.reg is the same as that for the XA reg instruction. XADR i8 Exchange AC with 1100 1000 2 2 (AC) « [M (i8)] Exchange the contents of AC M direct I 7 I6 I5 I4 I3 I2 I1 I0 and M (i8). LEAI i8 Load E & AC with 1100 0110 22 E ‹ I7 I6 I5 I4 Load the immediate data i8 immediate data I 7 I6 I5 I4 I3 I2 I1 I0 AC ‹ I3 I2 I1 I0 into E, AC. Load into E, AC the ROM data RTBL Read table data from0101 1010 1 2 E, AC ‹ at the location determined by program ROM [ROM (PCh, E, AC)] replacing the lower 8 bits of the PC with E, AC. Output from ports 4 and 5 the Read table data from Port 4, 5 ‹ ROM data at the location RTBLP program ROM then 0101 1000 1 2 [ROM (PCh, E, AC)]determined by replacing the output to P4, 5 lower 8 bits of the PC with E, AC. [Data pointer manipulation instructions] Load DPH with zero LDZ i4 and DPL with 0110 I 3 I2 I1 I0 11 DP H ‹ 0 Load zero into DP H and the immediate data DPL ‹ I3 I2 I1 I0 immediate data i4 into DPL. respectively LHI i4 Load DPH with 1100 1111 22 D P H ‹ I3 I2 I1 I0 Load the immediate data i4 immediate data 0000 I 3 I2 I1 I0 into DPH . LLI i4 Load DPL with 1100 1111 22 D P L ‹ I3 I2 I1 I0 Load the immediate data i4 immediate data 0001 I 3 I2 I1 I0 into DPL. LHLI i8 Load DPH , DPL with 1100 0000 22 DP H ‹ I7 I6 I5 I4 Load the immediate data into immediate data I 7 I6 I5 I4 I3 I2 I1 I0 DP L ‹ I3 I2 I1 I0 DL H , DPL. LXYI i8 Load DPX, DPY with 1100 0000 22 DP X ‹ I7 I6 I5 I4 Load the immediate data into immediate data I 7 I6 I5 I4 I3 I2 I1 I0 DP Y ‹ I3 I2 I1 I0 DL X, DPY. Number of bytes Number of cycles reg T 0 HL 0 XY 1

Continued from preceding page. No. 5485-22/26 LC665304A, 665306A, 665308A, 665312A, 665316A Continued on next page. Instruction code Affected Mnemonic Operation Description status Note D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 bits [Data pointer manipulation instructions] IL Increment DP L 0001 0001 1 1 D P L ‹ (DPL) + 1 Increment the contents ZFof DPL. DL Decrement DP L 0010 0001 1 1 D P L ‹ (DPL) – 1 Decrement the contents ZFof DPL. IY Increment DP Y 0001 0011 1 1 D P Y ‹ (DPY) + 1 Increment the contents ZFof DPY. DY Decrement DP Y 0010 0011 1 1 D P Y ‹ (DPY) – 1 Decrement the contents ZFof DPY. TAH Transfer AC to DP H 1100 1111 22 D P H ‹ (AC) Transfer the contents of AC 1111 0000 t o D P H . THA Transfer DP H to AC 1100 1111 2 2 AC ‹ (DPH ) Transfer the contents of DPH ZF1110 0000 t o A C . XAH Exchange AC 0100 0000 1 1 (AC) « (DPH ) Exchange the contents of AC with DPH and DPH . TAL Transfer AC to DP L 1100 1111 22 D P L ‹ (AC) Transfer the contents of AC 1111 0001 t o D P L. TLA Transfer DP L to AC 1100 1111 2 2 AC ‹ (DPL) Transfer the contents of DPL ZF1110 0001 t o A C . XAL Exchange AC 0100 0001 1 1 (AC) « (DPL) Exchange the contents of AC with DPL and DPL. TAX Transfer AC to DP X 1100 1111 22 D P X ‹ (AC) Transfer the contents of AC 1111 0010 t o D P X. TXA Transfer DP X to AC 1100 1111 2 2 AC ‹ (DPX) Transfer the contents of DPX ZF1110 0010 t o A C . XAX Exchange AC 0100 0010 1 1 (AC) « (DPX) Exchange the contents of AC with DPX and DPX. TAY Transfer AC to DP Y 1100 1111 22 D P Y ‹ (AC) Transfer the contents of AC 1111 0011 t o D P Y. TYA Transfer DP Y to AC 1100 1111 2 2 AC ‹ (DPY) Transfer the contents of DPY ZF1110 0011 t o A C . XAY Exchange AC 0100 0011 1 1 (AC) « (DPY) Exchange the contents of AC with DPY and DPY. [Flag manipulation instructions] SFB n4 Set flag bit 0111 n 3 n2 n1 n0 1 1 Fn ‹ 1 Set the flag specified by n4 to 1. RFB n4 Reset flag bit 0011 n 3 n2 n1 n0 1 1 Fn ‹ 0 Reset the flag specified ZFby n4 to 0. [Jump and subroutine instructions] PC13, 12 ‹ This becomes JMP Jump in the current 1110P 11P10P9 P8 PC13, 12 Jump to the location in the PC12 + (PC12) addr bank P 7 P6 P5 P4 P3 P2 P1 P0

22 PC11 to 0 ‹ same bank specified by the immediately

immediate data P12. following a BANK instruction. Jump to the address PC13 to 8 ‹ Jump to the location JPEA stored at E and AC 0010 0111 1 1 PC13 to 8, determined by replacing the in the current page PC7 to 4 ‹ (E), lower 8 bits of the PC PC3 to 0 ‹ (AC) by E, AC. PC13 to 11 ‹ 0, PC10 to 0 ‹ CAL Call subroutine 0101 0 P 10P9 P8 22 P10 to P0, Call a subroutine.addr P 7 P6 P5 P4 P3 P2 P1 P0 M4 (SP)‹ (CF, ZF, PC13 to 0), SP ‹ (SP)-4 PC13 to 6, PC10 ‹ 0, CZP Call subroutine in the 1010 P

3 P2 P1 P0 12 PC5 to 2 ‹ P3 to P0, Call a subroutine on page 0

addr zero page M4 (SP) ‹ in bank 0. (CF, ZF, PC12 to 0), SP ‹ SP-4 BANK Change bank 0001 1011 1 1 Change the memory bank and register bank. Number of bytes Number of cycles

Continued from preceding page. No. 5485-23/26 LC665304A, 665306A, 665308A, 665312A, 665316A Instruction code Affected Mnemonic Operation Description status Note D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 bits [Jump and subroutine instructions] Store the contents of reg in M2 (SP). Subtract 2 from SP after the store. PUSH Push reg on M2 (SP)1100 1111 22 M2 (SP) ‹ (reg) r e g 1111 1i 1 i0 0 SP ‹ (SP) – 2 Add 2 to SP and then load the POP 1100 1111 S P ‹ (SP) + 2 contents of M2(SP) into reg. reg Pop reg off M2 (SP)1110 1i 1 i0 0 22 reg ‹ [M2 (SP)] The relation between i1i0 and reg is the same as that for the PUSH reg instruction. Return from SP ‹ (SP) + 4 Return from a subroutine or RT subroutine 0001 1100 1 2 PC ‹ [M4 (SP)] interrupt handling routine. ZF and CF are not restored. Return from interrupt SP ‹ (SP) + 4 Return from a subroutine or RTI routine 0001 1101 1 2 P C ‹ [M4 (SP)] interrupt handling routine. ZF ZF, CF CF, ZF ‹ [M4 (SP)] and CF are restored. [Branch instructions] PC7 to 0 ‹ Branch to the location in the BAt2 Branch on AC bit 1101 00t 1 t0 22 P7 P6 P5 P4 same page specified by P7 to addr P 7 P6 P5 P4 P3 P2 P1 P0 P3 P2 P1 P0 P0 if the bit in AC specified by if (AC, t2) = 1the immediate data t1 t0 is one. PC7 to 0 ‹ Branch to the location in the BNAt2 Branch on no AC bit1001 00t 1 t0 22 P7 P6 P5 P4 same page specified by P7 to addr P 7 P6 P5 P4 P3 P2 P1 P0 P3 P2 P1 P0 P0 if the bit in AC specified by if (AC, t2) = 0the immediate data t1 t0 is zero. PC7 to 0 ‹ Branch to the location in the BMt2 1101 01t 1 t0 P7 P6 P5 P4 same page specified by P7 to addr Branch on M bit P7 P6 P5 P4 P3 P2 P1 P0

22 P 3 P2 P1 P0 P0 if the bit in M (HL) specified

if [M (HL),t2] by the immediate data t1 t0 = 1 is one. PC7 to 0 ‹ Branch to the location in the BNMt2 1001 01t 1 t0 P7 P6 P5 P4 same page specified by P7 to addr Branch on no M bitP7 P6 P5 P4 P3 P2 P1 P0 if [M (HL),t2] by the immediate data t1 t0 = 0 is zero. Internal control registers can also be tested by PC7 to 0 ‹ Branch to the location in the executing this P

7 P6 P5 P4 same page specified by P7 to instruction

BPt2 Branch on Port bit 1101 10t 1 t0 22 P 3 P2 P1 P0 P0 if the bit in port (DPL) immediately after addr P 7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] specified by the immediate a BANK = 1 data t 1 t0 is one. instruction. However, this is limited to registers that can be read out. Internal control registers can also be tested by PC7 to 0 ‹ Branch to the location in the executing this P BNPt2 Branch on no Port bit1001 10t 1 t0 22 P 3 P2 P1 P0 P0 if the bit in port (DPL) immediately after addr P 7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] specified by the immediate a BANK = 0 data t 1 t0 is zero. instruction. However, this is limited to registers that can be read out. Number of bytes Number of cycles Continued on next page. reg i 1 i0 HL 0 0 XY 0 1 AE 1 0 Illegal value 1 1

Continued from preceding page. No. 5485-24/26 LC665304A, 665306A, 665308A, 665312A, 665316A Continued on next page. Instruction code Affected Mnemonic Operation Description status Note D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 bits [Branch instructions] PC7 to 0 ‹ Branch to the location in the BC addr Branch on CF 1101 1100 22 P7 P6 P5 P4 same page specified by P7 to P7 P6 P5 P4 P3 P2 P1 P0 P3 P2 P1 P0 P0 if CF is one.if (CF) = 1 PC7 to 0 ‹ Branch to the location in the BNC Branch on no CF 1001 1100 22 P7 P6 P5 P4 same page specified by P7 to addr P 7 P6 P5 P4 P3 P2 P1 P0 P3 P2 P1 P0 P0 if CF is zero.if (CF) = 0 PC7 to 0 ‹ Branch to the location in the BZ addr Branch on ZF 1101 1101 22 P7 P6 P5 P4 same page specified by P7 to P7 P6 P5 P4 P3 P2 P1 P0 P3 P2 P1 P0 P0 if ZF is one.if (ZF) = 1 PC7 to 0 ‹ Branch to the location in the BNZ Branch on no ZF 1001 1100 22 P7 P6 P5 P4 same page specified by P7 to addr P 7 P6 P5 P4 P3 P2 P1 P0 P3 P2 P1 P0 P0 if ZF is zero.if (ZF) = 0 PC7 to 0 ‹ Branch to the location in the BFn4 1111 n 3 n2 n1 n0 P7 P6 P5 P4 same page specified by P0 to addr Branch on flag bitP7 P6 P5 P4 P3 P2 P1 P0

22 P3 P2 P1 P0

P7 if the flag (of the 16 user if (Fn) = 1 flags) specified by n3 n2 n1 n0 is one. PC7 to 0 ‹ Branch to the location in the BNFn4 1011 n 3 n2 n1 n0 P7 P6 P5 P4 same page specified by P0 to addr Branch on no flag bitP7 P6 P5 P4 P3 P2 P1 P0 P7 if the flag (of the 16 user if (Fn) = 0 flags) specified by n3 n2 n1 n0 is zero. [I/O instructions] IP0 Input port 0 to AC 0010 0000 1 1 A C ‹ (P0) Input the contents of port ZF0 to AC. IP Input port to AC 0010 0110 1 1 A C ‹ [P (DPL)] Input the contents of port ZFP (DPL) to AC. IPM Input port to M 0001 1001 1 1 M (HL) ‹ [P (DPL)] Input the contents of port P (DPL) to M (HL). IPDR i4 Input port to 1100 1111 2 2 AC ‹ [P (i4)] Input the contents of ZFAC direct 0110 I 3 I2 I1 I0 P (i4) to AC. Input port 4, 5 to 1100 1111 E ‹ [P (4)] Input the contents of ports IP45 E, AC respectively 1101 0100 22 AC ‹ [P (5)] P (4) and P (5) to E and AC respectively. OP Output AC to port 0010 0101 1 1 P ( D P L) ‹ (AC) Output the contents of AC to port P (DPL). OPM Output M to port 0001 1010 1 1 P ( D P L) ‹ [M (HL)] Output the contents of M (HL) to port P (DPL). OPDR i4 Output AC to 1100 1111 2 2 P (i4) ‹ (AC) Output the contents of AC port direct 0111 I 3 I2 I1 I0 to P (i4). Output E, AC to port1100 1111 P (4) ‹ (E) Output the contents of E and OP45 4, 5 respectively 1101 0101 22 P (5) ‹ (AC) AC to ports P (4) and P (5) respectively. Set to one the bit in port SPB t2 Set port bit 0000 10t 1 t0 1 1 [P (DP L), t2] ‹ 1 P (DP L) specified by the immediate data t1 t0. Clear to zero the bit in port RPB t2 Reset port bit 0010 10t 1 t0 1 1 [P (DP L), t2] ‹ 0 P (DP L) specified by the ZF immediate data t1 t0. And port with P (P 3 to P0) ‹ Take the logical AND of P (P3 ANDPDR immediate data then1100 0101 2 2 [P (P 3 to P0)] to P0) and the immediate data ZFi4, p4 output I3 I2 I1 I0 P3 P2 P1 P0 I3 to I0 I3 I2 I1 I0 and output the result to P (P3 to P0). Or port with P (P 3 to P0) ‹ Take the logical OR of P (P3 ORPDR immediate data then 1100 0100 2 2 [P (P 3 to P0)] to P0) and the immediate data ZF i4, p4 output I3 I2 I1 I0 P3 P2 P1 P0 I3 to I0 I3 I2 I1 I0 and output the result to P (P3 to P0). Number of bytes Number of cycles

Continued from preceding page. No. 5485-25/26 LC665304A, 665306A, 665308A, 665312A, 665316A Instruction code Affected Mnemonic Operation Description status Note D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 bits [Timer control instructions] TIMER0 ‹ [M2 (HL)],Write the contents of M2 (HL), WTTM0 Write timer 0 1100 1010 1 2 (AC) AC into the timer 0 reload register. 1100 1111 Write the contents of E, AC WTTM1 Write timer 1 1111 0100 2 2 TIMER1 ‹ (E), (AC) into the timer 1 reload register A. M2 (HL), Read out the contents of the RTIM0 Read timer 0 1100 1011 1 2 AC ‹ (TIMER0) timer 0 counter into M2 (HL), AC. RTIM1 Read timer 1 1100 1111 2 2 E, AC ‹ (TIMER1) Read out the contents of the 1111 0101 timer 1 counter into E, AC. START0 Start timer 0 1100 1111 2 2 Start timer 0 counter Start the timer 0 counter.1110 0110 START1 Start timer 1 1100 1111 2 2 Start timer 1 counter Start the timer 1 counter.1110 0111 STOP0 Stop timer 0 1100 1111 2 2 Stop timer 0 counter Stop the timer 0 counter.1111 0110 STOP1 Stop timer 1 1100 1111 2 2 Stop timer 1 counter Stop the timer 1 counter.1111 0111 [Interrupt control instructions] MSET Set interrupt master1100 1101 2 2 MSE ‹ 1 Set the interrupt master enable flag 0101 0000 enable flag to one. MRESET Reset interrupt 1100 1101 2 2 MSE ‹ 0 Clear the interrupt master master enable flag 1001 0000 enable flag to zero. EIH i4 Enable interrupt high1100 1101 2 2 EDIH ‹ (EDIH) i4Set the interrupt enable flag 0101 I 3 I2 I1 I0 to one. EIL i4 Enable interrupt low1100 1101 2 2 EDIL ‹ (EDIL) i4Set the interrupt enable flag 0100 I 3 I2 I1 I0 to one. DIH i4 Disable interrupt high1100 1101 2 2 EDIH ‹ (EDIH) i4Clear the interrupt enable ZF1001 I 3 I2 I1 I0 flag to zero. DIL i4 Disable interrupt low1100 1101 2 2 EDIL ‹ (EDIL) i4Clear the interrupt enable ZF1000 I 3 I2 I1 I0 flag to zero. WTSP Write SP 1100 1111 2 2 SP ‹ (E), (AC) Transfer the contents of E, 1101 1010 A C t o S P . RSP Read SP 1100 1111 2 2 E, AC ‹ (SP) Transfer the contents of SP 1101 1011 t o E , A C . [Standby control instructions] HALT HALT 1100 1111 2 2 HALT Enter halt mode.1101 1110 HOLD HOLD 1100 1111 2 2 HOLD Enter hold mode.1101 1111 [Serial I/O control instructions] STARTS Start serial I O 1100 1111 2 2 START SI O Start SIO operation.1110 1110 WTSIO Write serial I O 1100 1111 2 2 SIO ‹ (E), (AC) Write the contents of E, 1110 1111 A C t o SIO. RSIO Read serial I O 1100 1111 2 2 E, AC ‹ (SIO) Read out the contents of SIO 1111 1111 into E, AC. [Other instructions] Consume one machine cycle NOP No operation 0000 0000 1 1 N o operation without performing any operation. SB i2 Select bank 1100 1111 2 2 PC13, PC12 ‹ I1 I0 Specify the memory bank.1100 00I 1 I0 Number of bytes Number of cycles

No. 5485-26/26 LC665304A, 665306A, 665308A, 665312A, 665316A This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. n No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n Anyone purchasing any products described or contained herein for an above-mentioned use shall: À Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: \` Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.