LC6543N SANYO | Alldatasheet
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CC6543N/F/L, 6546N/F/L | ; CMOS LSI SINGLE-CHIP 4-BIT MICROCOMPUTER FOR SMALL-SCALE CONTROL-ORIENTED - APPLICATIONS Overview \\ The LC6543N/F/L, LC6546N/F/L belong to our single-chip 4-bit microcomputer LC6500 series fabicated using CMOS process technology and are suited for use in small-scale control-oriented applications. Their basic architecture | and instruction set are the same, Application areas include audio equipment (tape deck, player, etc.), office equipment, ‘communications equipment, car equipment, home appliances as well as circuits so far formed with the standard logic circuits and applications where the number of controls is small. The LC6543N/F/L, LC6546N/F/L have relation to the LC6543C/H, LC6546C/H. The C version can be replaced by N version, and the H version by F version (a part of the function is different). The L version is added as a low voltage version. The following show the careful difference of C ‘ and N version when you replace C version with N version. Poe version TT Nversion _|* 2-pin cRsixed srequency oscillator with |“ -pin Coscilation [exist [___not exist __]**Otheroptions shown ntabioon thee, z C1=C2=330pF C1=C2=220pF : 3 Reon Re2.2kQ G |800kHz] MURATA C1=C2=220pF C1=C2=100pF . & R=0Q ‘ R=0Q R=2.2kQ . " (Note) The suffix of recommend oscillation is changed C version and N version, but the characteristics are no change. * Features 1) CMOS technology for a low-power operation (with instruction-controlled standby function) 2) ROM/RAM. 1LC6543N/F/L ROM : 2K x 8bits, RAM : 128 x 4bits LC6546N/F/L ROM: 1K x 8bits, RAM: 64 x 4bits 3) Instruction set : 80 instructions common to the LC6500 series 4) Wide operationg voltage range form 2.2V to 6.0V (L version) 5) Instruction cycle time of 0.92us (F version) 6) On-chip serial 1/O port . Continued on next page. SANYO believes information herein is accurate and reliable, but no guarantees are made or imphed regarding its use or any infring- 1 ‘coments of intellectual property rights or other rights of third parties. . Specifications and information herein are subject to change without notice. TOKYO OFFICE Tokyo Blidg., 1-10, 1 Chome, Vena, Taito-ku, TOKYO, 110 JAPAN NOB93JN A8-9833, 9835 B8-0329 No, 4364-1/43
LC6543N/F/L, LC6546N/F/L ee _ Continued from preceding page. - ; ; ~ 7) Flexible 1/O port ~ 2 © Number of ports : 7 ports/25 pins max. * All ports : Input/output common Input/output voltage 15V max. (open drain type) Output current 20mA max. (sink current) (LED direct drivable) : Option selectable for your intended system A. Open drain output, pull-up resistor : Single-bit select for all ports B. Output level at the reset mode 34-bit select of H/L level for port C/D 8) Interrupt function Vectored interrupt by timer overflow (instruction-testable) Vectored interrupt by INT pin or completion of transmit/ receive at serial I/O port (instruction testable) . 9) Stack level : 4 levels (common with interrupt) 10) Timer : 4-bit prescaler + 8-bit programmable timer 11) Clock oscillation option selectable for your intended system. * Oscillator option : 2-pin RC oscillaion (N, L version) . 2-pin ceramic resonator oscillation, 1-pin external clock input (N,F,L version) * Predivider option : No predivider, 1/3 predivider, 1/4 predivider (N, L version) 12) Burst pulse (64 x cycle time) output function : Function Table [ten | ENN eee 2048 x 8 bits (43N) 2048 x 8 bits (43F) 2048 x 8 bits (43L) | | ecieseaeo | imseueusn | Sewennuas | . 64x 4 bits (46N) “64x 4 bits (46F) 64 x4 bits (46L) E{_instructionset_ | BO . P S| Stacklevel Pa by HALT instruction by HALT instruction by HALT instruction g g E £2 6.0us (VDD23V) Resonator RC (850kHz,400kHz typ.) RC (400kHz typ.) 4MHz) 4MHz) Bier] Package | DIPSV ink type, MEPSOS_| DIPSDshvink type, MFPOOS | —DIPSO sive type, MPSOS | (Note) Information on the resonator and oscillation circuit constants will be presented as soon as the recommended circuit is determined. No, 4364-2/49
LO6S43N/F/L, LC6S46N/F/L___ Pin Assignment : ~ : Common to DIP « MFP BEREEEERS ESB a BB . AUSSI USI WSO SOULS RS ESS SW SS ad Kd ed ! LCES46N/F/L : Pago eaee
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Be é 4 £ Fy Ly Package Dimensions 2 3073A (unit : mm) 3061 (unit : mm) So poocoonpopoope <9 . aS 15°3 3 UT AAR TA 2 2 vcacataletelatelsdetatstslately i 4 6 a 2 ob 0% 0.95 ae 178 : SANYO : MFP30S SANYO : DIP30S No, 4364-3/49
LO6543N/F/L, LG6546N/F/L ee SSSSSSSSSSSsssssSSSSSSSSSSsssssSsSSSSSSSee Pin Name OSC1,OSC2 : C,Ror ceramic resonator for OSC PG0-3: Input/output common port G 0-3 . RES : Reset : PIO: Input/output common port 10 PAO3 : Input/output common port A 0-3 TEST : Test . PCO-3 : Input/output common port C 0-3 INT —: Interrupt request pin PD03 : Input/output common portD 0-3 SI: Serial input pin 7 PEO-3 : Input/output common portE 0-3 SO : Serial output pin PF 0-3 : Input/output common portF 0-3 SCK : Serial clock input/output pin (Note) * The SI, SO, SCK, and INT pins are common to the PFO to PF3 pins respectively. ° The OSC2 pin and PI0 pin are common to each other, but are mutually exclusive. Either pin user-selectable. System Block Diagram LC6543N/F/L, LC6S46N/F/L PA0-a>) Pot A K=> PAM a .
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5 register <—> vo 4 : PFOSIO-$- higher digit [Pea g] [Pon | <— vss ; { PRAASCRo&—> PGO3 PIO t Note 1 ‘- PF3/ANT © Note 1. The Pi0 pin and OSC2 pin are common to each other, but are mutually exclusive. Either pin is user- selectable. RAM : Data memory ROM : Program memory F : Flag Pc : Program counter WR: Working register INT _ : Interrupt control AC: Accumulator IR : Instruction register ALU : Arithmetic and logic unit I.DEC : Instruciton decoder - DP: Data pointer CE,CSF: Carry flag, carry save flag - E : E register ZF, ZSF: Zero flag, zero save flag CTL : Control register EXTF : External interrupt request flag OSC : Oscillator TMF: Internal interrupt request flag Ts: Timer . STS: -Status register No, 4364-4/49
EC6S43N/F/L, LC6546N/F/L —_— ee Development Support Tools - —. : . : The following are available to support the program development for the LC6543, LC6546. we a (1) User's Manual tate “LC6554 Series User's Manual” No. 21B (2) Development Tool Manual . For the EVA-410 system, refer to the desciption of Development support tool in "LC6554 Series Use's Manual". For the EVA-800 system, refer to “EVA-800. LC6554 Series Development Tool Manual”. (3) Development Tools : A. For program development (EVA-410 system) 1. MS-DOS for host system (Note 1) . 2. MS-DOS base cross assembler : <LC65S.EXE> 3. Evaluation kit (EVA-410C) : 4. Evaluation kit target board (EVA-TB6543/46), evaluation chip (LC6594) B. For program evaluation 1. New piggyback (LC65PG43/46-A) 2. Piggyback (LC65PG43/46) © Small package © The socket for pin-to-pin conversion is required. : © The socket for pin-to-pin conversion is not required. For detailed information on how to use it, . refer to page 32 of this catalog. 3. During development EPROM built-in microcomputer (LC65E43) Note. For notes for program evaluation, do not fail to refer to ‘5-3-4, Notes when evaluating programs for , the LC6543/46" in "LC6554 Series User's Manual”, EVA-410 System Piggyback to EVA-410 LCESP GAIA “> ‘Small Package EPROM (2722 or 2764) ‘The socket for pin-to-pin convertion a kod, fal emo EPROM | PAP-40-0382 ; ett | [eke] SVs INFP-soA-o11 gS NFP-80A-0112| Sen cusp) er) one o Nee-san-0100 ‘To application syatern shesspasss - } Tre noel pope EPROM (2732 or 2764) ‘conversion is required. , (ZL = . 0.695mm pkch oO nano flex cable > x
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LIK eal) ~ re board (78438) Al ‘conversion board i J {Bockat for pie-lo-pin * pipsos Read- Witte adisptor tor 2764 conversion) Evaluation Kit Target Board eure : : (EVA TBES43 / 48) ara mn SS To application sysiom . No, 4364-5/49
__LOB543N/F/L, LOSS46N/F/L. a C. For program development (EVA-800 system) - Soo bee r . . “” “4. MS-DOS for host system (Note 1) ‘ 3. Evaluation chip : LC6594 Sa 4, Emulator : EVA-800 emulator and evaluation boards . : Appearance of Development Support System EVA-800 System . “Host processor control program “TH | : —— a7 = MS-DOS personal computer y &> = Cc EVA-B00 or EVA-B50 : omutator (note 2) Lee LY ten ip tow x oN EVAR00-TBS2OZ2/54N4948 ———, — a NFP5OA . User's sppiication board po : (Note 1) MS-DOS : Tradmark of Microsoft Corporation (Note 2) The EVA-800 is a general term for emulator. A suffix (A, B,...) is added at the end of EVA-800 as the EVA-800 is improved to be a newer version. Do not use the EVA-800 with no suffix added. No. 4364-6/49
. LO6S43N/F/L, LCB546N/F/L__ — eee ' Pin Description — : . | VDD Power supply pa a 1 | OSCT © Pin for externally connecting RC, 1) 1-pin external clock input ceramic resonator for system 2) 2-pin RC OSC : clock generation. 3) 2-pin ceramic resonator ¢ For 1-pin external clock input, osc the PI0/OSC2 pin is used as 1/O | 4) Predivider option : port P10, 1. No predivider . : © For 2-pin RC OSC, 2-pin ceramic] 2.1/3 predivider . resonator OSC, the PI0/OSC2 3. 1/4 predivider pin is used as OSC pin OSC2. : | PAOtoPA3 Input/} ¢ 1/0 port AO to3 1) Open drain type output |*"H"output (Out: output| 4-bit input (IP instruction) 12) With pull-up resistor put Nch transis- 4-bit output (OP instruction) 1), 2): Specified bit by bit | tor: OFF) Single-bit decision (BP, BNP . : instruction) Single-bit set/reset (SPB, RPB instruction) © Standby is controlled by PA3 . (or PAO to 3). a ¢ The PA3 (or PAO to 3) pin must be free from chattering during thd HALT instruction execution cycle} PC Oto PC3 Input/| *1/O port CO to 3 11) Open drain type output | ¢ "H" output output} Same as for PAO to 3 (Note) °"L" output * Option permits output at the —_‘[2) With pull-up resistor (Option - reset mode to be "H” or "L". 13) Output at reset mode:"H"| selectable) (Note) No standby control 14) Output at reset mode:"L" function is provided. #1), 2): Specified bit by bit : . © 3), 4): Specified ina ' group of 4 bits press [oe sewers Pee : output| Same as for PCO to 3 to3 | | PEOtoPE3 Input/| 1/0 port £0 to 3 '1) Open drain type output | ¢"H"output (Out- output] 4-bit input (IP instruction) 12) With pull-up resistor put Neh transi: 4-bit output (OP instruction) 11), 2) : Specified bit by bit | tor: OFF) Single-bit set/reset (SPB, RPB : instruction) Single-bit decision (BP, BNP . instruction) © PEO: With burst pulse (64Tcyc) output function No. 4364-7/49
~LCB543N/F/L, LC6S46N/F/L eee [PinName | Pins[ 1/0 | Function [Option Reset Mode _| ' | PFO/SI Input/ | ¢1/O port RD to3 Same as for PED to 3 Same as for PEO PF1/SO0 output Same as for PEO to 3 (Note) to3 PF2/SCK © PFO to 3: Common with serial Serial port : PF3/ iNT . interface, INT input. Disable Progaram-selectable Interrupt source: SI ¢¢¢ Serial input port iNT SO ¢¢¢ Serial output port . | SCK ¢¢ Serial clock input/output INT ¢¢ Interrupt request input | - 4-bit/8-bit serial input/output is program-selectable. — (Note) No burst pulse output ° ‘ function is provided. PG 0to PG3 Input/ | *1/O port G0 to3 Same as for PEO to 3 Same as for PEO . output | Same as for PEO to 3 (Note) to3 . (Note) No burst pulse output function is provided. . PI0/ OSC2 Input- | I/O port 10 Same as for PGO to 3 ‘Same as for PGO joutput/ | Same as for PGO to 3 to3 output | ¢ Single-bit configuration : * For 2-pin OSC, this pin is used as the OSC2 pin, providing no : function as 1/O port. RES * Systen reset input For power-up reset, C is con- nected externally. © For reset restart, "L” level is applied for 4 clock cycles or more. “ ‘ema a Normally connected to VSS Oscillator circuit option [OptionName [Circuit Conditions,ete. 1. External clock o8c1 The PI 0 / OSC2 pin is used as port noe Dn. . 2. 2-pin RC OSC can ose1 The PI 0 / OSC2 pin is used as OSC . pin OSC2, providing no function as Puiosce port. a a <b ; 3. Ceramic fy osc’ The P10 / OSC2 pin is used as OSC resonator OSC Fi aa pin OSC2, providing no function as basins SI pwrosce port. oo ose sam a No, 4364-8/49
__LCB543N/F/L, LCB546N/F/L —_[—— SSeS ~ Predivider Option 1..No predivider © Applicable to all of 3 OSC options. a/) * The OSC frequency, external clock do not Ct tose exceed 1444kHz. (LC6543N, 6546N) oO ¢ The OSC frequency, external clock do not exceed 4330kHz. (LC6543F, 6546F) * The OSC frequency, external clock do not exceed 1040kHz. (LC6543L, 6546L) : 2.1/3 predivider + Applicatable to only 2 OSC options of . O fore ey Sia i external clock, ceramic resonator OSC. O48 ees * The OSC frequency, external clock do not exceed 4330kHz. 3.1/4 predivider - * Applicatable to only 2 OSC options of Ct sose ial fared external clock, ceramic resonator OSC. oO * The OSC frequency, external clock do not exceed 4330kHz. Note : The OSC option and predivider option are summarized below. Full care must be exercised. Table of OSC, predivider Option of LC6543N/46N, 43F/46F and 43L/46L | LC6S43N, L6546N Frequency Predivider Option [VDD Range Remarks aa bir ie Ceramic resonator OSC 400kHz. 1/1 (10 ps) 3to6V | Unusable with 1/3, 1/4 al 800kHz 1/165 ps) 4to6V 1/3 (15 ps) 4to6V 1/4 Q0 ps) 4to6V | he MHz 1/1 4 ps) 4t06V 1/4 (16 ps) 4to6V - 1/3 (3 ps) 4to6V | Unusable with 1/1 predivider 1-pin external clock 200kto 667kHz 1/1 (20 to 6s) 3t06V 600k to 2000kHz 1/3 (20 to 61s) 3to6V . 800k to 2667kHz, 1/4 (20 to 6s) 3to6V . 200k to 1444kHz 1/1 (20 to 2.771s)| 4 to 6V : 600k to 4330kHz 1/3 (20 to 2.7718)| 4 to 6V 800k to 4330kHz 1/4 (20 to 3.70us)| 4 to 6V External clock by 2-pin Same as above RC OSC circuit pin RC Used with 1/ipredivider,recommended| _3to 6V . constants. If used with other than recommended constants, the frequency, predivider option, VDD range must be the same as for 1-pin external clock. External clock input to the | The ceramic oscillation circuit cannot be driven by external clock. RC option. No. 4364-9/49
LC6543N/F/L, LC6546N/F/L ee SSeSSSeSeSFSSSSSSSSSSFFFFFese LC6543F, L6546F 7 [ Ceramic resonator Osc __| 4MHz | vim [aStoev [Cd [i-pin exeral cock | 200k Mab: | 1/1 010 09%a)] 45t96V | External clock input to the The ceramic oscillation circuit cannot be driven by external clock. ceramic oscillation circuit To drive the circuit with external clock, select the external clock option. LC65431, L65461. . Circuit Configuration Frequency Predivider Option [VDD Range Remarks [oe [ee [Game | Ceramic resonator OSC - | 400kHz 1/1 (10 ps) 22to6V | Unusable with 1/3, 1/4 ee | ee ee | 800kHz ~ 1/1 5 ps) 22to6V 1/3 (15 ps) 22to6V 1/4 (20 ps) 22 to 6V MHz 1/1 @ ps) 22 to 6V 1/3 (12 ps) 22to6V 1/4 (16 ps) 2.2 to 6V ae | 1/4 (4 ps) 22to6V | Unusable with 1/1, 1/3 ee ee 1-pin external clock 200k to 1040kHz 1/1 (20 to 3.84us)| 2.2 to 6V 600k to 3120kHz 1/3 (20 to 3.84y1s)| 2.2 to 6V 800k to 4160kHz 1/4 (20 to 3.84ys)| 22to 6V External clock by 2-pin | Same as above feocese 2-pin RC Used with 1/1predivider,recommended constants. If used with other than recommended constants, the frequency, predivider option, VDD range must be the same as for 1-pin external clock. External clock input to the | The ceramic oscillation circuit cannot be driven by external clock. . ceramic oscillation circuit | To drive the circuit with external clock, select the external clock option or the 2-pin RC option. Option of ports C, D Output Level at the Reset Mode For input/output common ports C, D either of the following two output levels may be selected in a group of 4 bits during reset by option. Option of Port Output Configuration For each input/output common port, either of the following two output configurations may be selected by option . T. Open drain output * Unapplicable to port PI0/OSC2 when 2-pin RC OSC or ceramic LP a “mE 2. Output with pull-up [>o resistor — | No. 4364-10/49
LC6543N/F/L, LC6546N/F/L eee 1. Absolute Maximum Ratings at Ta=25°C, VSS=0V [Parameter [Symbol [Conditions [Fins [Limite [at] . | Maximum VDD 0.3 to +7.0 Vv Ee ed ee ae ee a a [vig | ress -03t0vppi03 Tv ~ { PApur/output [viogy | Port of OD iype| O3t0v5 TV | | | voltage [Vio@ |__| Pon of PU ype| 03:0 VDD+03 [Vv] Peak output | IOP 1/0 port “20 +20 _ mA jeer | fe current 100 ms XIOAG) | Total current of PCO to 3, PCOto3 PDO to3,PEOto3 (*2) PDO to3 -15 to +100 mA PEO to-3 ZIOAQ) Total current of PFO to 3, PFOto3 PIO PGO to 3, PAO to 3, PIO PGOto3 +15 to +100 mA (2) PAO to3 Allowable Ta=-40 to +85°C | 250 mW power (DIP package) | Operating Topg ~40 to +85 °c wom | | Storage Tstg, -55 to +125 °C fimene [Ef Pe 2, Allowable Operating Conditions at Ta=-40 to +85°C, VSS=0V, VDD=3.0 to 6.0V fee [om om ieee] : [_min. [typ] max. [unit _| Operating VDD VDD Vv supply voltage Standby VST RAM, register hold VDD P, e? fy fami feo | P| | voltage OFF (except 10) eee ore | [ocowe | | OFF of OD type Output Neh Tr. INT, SCK, SI, 10 |0.8VDD ian OFF of PU type | VIG) | Extemalclockmodg osc fosvpp]{_vop [ v | voltage OFF | vid | OutputNchTr.0FF] stodPor | vss | |ozsvop| v | Ba in iid il OFF No. 4364-11/49
LO6543N/F/L, LCBS46N/F/L [Pee [ee Sm ee ee [_min. | typ. | max. [unit _| “L'jevelinput [VIL) | OutpueNenTeorr| Sto6[INTSCKSi_| vss | [o2vpp] v__| mode DD=4 to 6 External clock 3t0 6 [OSC1 Pe] | o2vpD| Vv mode [ving | vp-4to6[resr | vss [| foavppy v | jv) [| | toe ftesr | vss | pzsvpp] v | - [vitg f Wppeatoe [Res | vss [| fo2svop[_v__ | [virgo | TS to fRES | vss | jo2vpp| v_ | Operating fre- | fop When the 1/3 yess eT 1444 [kHz quency (Teyc) or 1/4 predivider| (20) (2.77) us) (cycle time) “| option is selected VDD=3 to 6 200 667 khz clock must not (20) (6.0) (us) exceed 4.33MHz. External clock conditions Fig.1. Frequency When clock DD=4 to 6 | OSC1 200 4330 kHz exceeds 1.444 3to6 200 2667 kHz 1/4 predivider 3t06 180 3to6 100 Oscillation guar- anty constants 2-pin RC Cext Fig.2 VDD=3 to 6| OSC1, OSC2 22045% pF oscillation Cext Fig.2 VDD=4 to 6] OSC1, OSC2 2204574 pF Rext Fig.2 'VDD=3 to 6} OSC1, OSC2 1241% kQ Rext” Fig.2 OSC1, OSC2 4.74194 kQ : Ceramic [ig atte . 3, Electrical Characteristics at Ta=-40 to +85°C, VSS=0V, VDD=3.0V to 6,0V iad [_min. |” typ. | max. [unit | “H"-Jevel input | IH(1) Output Nch Tr. OFF Port of OD type +5.0 HA current (including OFF leak current of Nch Tr.) VIN=+13.5V WH) External clock mode, +10 [pA pre [amano =o eee eel eT current . VIN=VSS me eer eee [| . VIN=VSS ite [vinevss So TIL@) External clock mode, ee was | [| “Hlevel output) VOHG) | IOH=50pA Port of PU type roy | . voltage VDD=4.0 to 6.0V [WOH | TOH-iqua [Pon ofPUype WDDOS! | | v_| No. 4364-12/49
LC6543N/F/L, LC6546N/F/L Pem [ ome eee [min | yp | max [unit ae haa focmcnetee fe —t Ppa voltage VOL(2) IOL=imA, IOL of each port: 05 v pee [ieee || Hysteresis VHIS RESINTSCK, 0.1VDD Vv voltage ‘$1, OSCI of schmitt type(*4) Current Output Neh Tr. OFF at * | dissipation operating, Port=-VDD 2-pin RC oscillation | IDDOP(1) | Fig.2 fose=850KHz (TYP) VDD 15 mA : VDD=4 to 6V : [1DDOPA) |Fig.2fosc-oodizayP) | vpbp | | 10 | 4 | ma | “in [ee fee resonator VDD=4 to 6V VDD=4 to 6V [wooPG) |Figs4o0diz | vpp | | to | 2s | ma | |;por@) [Figs s00KHz vDD=1tosv |vpp || | as [4 | ma | External clock | IDDOP(7) | 200kHz to 667kHz, VDD 15 mA 1/1 predivider 600kHz to 2000kHz, 1/3 predivider 800kHz to 2667kHz, 1/4 predivider IDDOP(@) | 200kHz to 1444kHz, VDD 20 mA 1/1 predivider 600kHz to 4330kHz, ; 1/3 predivider 800kHz to 4330kHz, 1/4 predivider, VDD=4 to 6V Sten [trace wos | dams | S| Bs | mode Port=VDD VDD=3V| VDD 0.025 pA Oscillation characteristics Ceramic OSC Frequency fCFOSC Fig.3 fo=400kHz OSC1,OSC2 | 384 400 416 kHz 5) Fig.3 fo=800kHz,VDD=4 to 6V] OSC1,OSC2 | 768 800 832 kHz_ Fig.3 fo=IMHz VDD=4 to 6V} OSCi,OSC2 | 960 1000 1040 kHz . - Fig.3 fo=4MHz,1/3 predivider, OSC1,OSC2 | 3840 4000 4160 kHz 1/4 predivider_ VDD=4 to 6V Stable time tCFS Fig.4 fo=400kHz 10 Fig.4 fo=800kHz,1MHz,4MHz, 10 1/3 predivider, 1/4 predividey VDD=4 to 6V. 2-pin RC fMOSC | Fig.2 Cext=220pF + 5% osc1,osc2 | 619 144 | kHz oscillation Fig.2 Rext=4.7kQ41% de Frequency VDD=4 to 6V ee || Fig.2 Rext=12kQ41% VDD=3 to 6V No. 4364-13/49
_LOSS43N/F/L, LC6S46N/F/L_ eee Po eT el [aie [yp [ma [ni Pull-up resistance 1/O port pull-up| RPP VDD=5V Port of PU kQ resistance type External reset 2 characteristics Reset time «RST See Fig5. Pin capacitance |Cp f=1MHz Other than pins Serial Clock Input clock | tCKCY(1) | Fig.6 VDD=4t06 | SCK 3.0 ps cycle time SK 120 ps cycle time (*6) mia level pulse width SK 4.0 | fe | level pulse width | | Onput clock "H” |}CKH(2) | Fig.6 SCK 32x TCYC us level pulse width pe | Serial input . Dataholdtine [CK [Rg S| Serial output Outputdelay |tCKO Specified for 05 time 4 of SCK Nch OD only, 20 oS External 1kQ, ; External 50pF, Fig.6 Pulse output lecy | width Period, Nch OD only, +10% “L'Jevel pulse External 1k, External S0pF ee ee width £10% — (*1) When oscillated internally under the oscillating conditions in Fig.4, up to the oscillation amplitude generated is allowable. (*2) Average over the period of 100ms. (*3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 (or PAO to 3) pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the 2-pin RC oscillation option or external clock oscillation option : has been selected. —- (5) fCFOSC: oscillation frequency. There is a tolerance of approximately 1%.between the center frequency at the ceramic resonator mode and the nominal value presented by the ceramic resonator supplier. For details, refer tothe specification for the ceramic resonator. (*6) TCYC=4 x system clock period No, 4364-14/49
_LC6543N/F/L, LC6S46N/F/L a osci (OSC2) ee - ~ OPEN : . . External clock nec ete eee e ne een econ e enn een een en een nennnenneeenenseseeneetensees-ee VDD we teeee eee ne ben nw nnn n nnn n nen eens fee e een ene e Perce eeeeee eee 0.8 VDD ste te ene ene anne | none ee ee eee pene fine een nneenee feces |e-e--eeeee-= O.2VDD. text textFe_toxt text oo Fig. 1 External Clock Input Waveform Osc1 osca osci osc2 - R ot - Cext Rext i _- : : St fon] ~~ c2 Fig. 2 2-pin RC Oscillation Circuit Fig. 3 Ceramic Resonator Oscillation Circuit VDD sectec cece ew eee reeeeereerereeeneeee Lower limit of operating VOD . - Osc ~ - Stabilized OSC Unstabilized : OSC period tCFS Fig. 4 Oscillation Stabilizing Period No. 4364-15/49
_ LO6543N/F/L, LC6546N/F/L_ Table 1 Constants Guaranteed for we Ceramic Resonator OSC soe : 4MHz (Murata) 33pF#10% : . ‘ . CST400MGW dbuiltinc)[ R [02 | . . : 4MHz (Kyocera) 33pF#10% KBR4.0MSA 33pF#10% KBR4.0MKS (built-inc) [| R [02 | ‘MHz (Murata) 100pF#10% TE CSB1000} [ R [22a CRES (0.1, F) MHz (Kyocera) J00pF+10% KBR1000F 100pF+10% {| R | o2 | 800kHz (Murata) Fig. 5 Reset Circuit CSBB00} [ c2 | 100pF110% [rR 2202 | (Note) When the rise time of the power supply is 0, ‘800kHz (Kyocera) 100pF#10% the reset time becomes 10msto100msat KBR800F 100pF+10% CRES=0.1,F, If the rise time of the power | KR] oo | supply is long, the value of CRES must be 400kHz (Murata) 220pF£10% increased so that the reset time becomes CSB400P 220pF#10% 10ms or more. [ R [22x09 | 400kHz (Kyocera) 330pF10% KBR400BK 330pF+10% . . [rf om} icKcy : . , ( o8vDD : .2V0D ss = . _ et el a oI pc “—" cKO _ . 50 pF % {oe > . a Fig. 6 Serial Input/Output Timing PCy . ae The load conditions are , =-- ome] 0.25VDD the same as in Fig. 6. Fig.7 Pulse Output Timing at Port PEO No. 4364-16/49
LC6543N/F/L, LC6546N/F/L ~ RC Oscillation Characteristics of the LC6543N, LC6546N ~ _ . . Fig. 8 shows the RC oscillation characteristic of the LC6543N, 6546N. For the variation range of RC OSC frequency of the LC6543N, LC6546N, the following are guaranteed at the external constants only shown below. | 1) VDD=3.0V to 6,0V, Ta=-40°C to +85°C : External constants Cext = 220 pF Rext =12kQ. 305 kHz < fMOSC s 546 kHz 2) VDD=4.0V to 6.0V, Ta=-40°C to +85°C . Cext = 220 pF . Rext = 4.7 kQ. 619kHz < FMOSC 1144kHz ‘ * Ifany other constants than specified above are used, the range of Rext=3kQ to 20kN, ; Cext=150pF to 390pF must be observed. (See Fig.8.) (*7): The oscillation frequency at VDD=5.0V, Ta=+25°C must be in the range of 350kHz to 750kHz. (8): The oscillation frequency at VDD=4.0 to 6.0V, Ta=-40°C to +85°C and VDD=3.0V to 6.0V, Ta=-40°C to 85°C must be within the operation clock frequency range. i {MOSC-Rext Sy These characteristic curves are ron Sx given for reference only without: ' ATES aurantes. : § TIN ESS SG : zw 6+ KES “y tf TT i 2 5s. | Ts [| {| [Ty i g ,L L_TISN Pt Tt g 7 2 jo, ||} NANT | YOD=5 (Vv) ‘Tan25, ‘ 100 aie SA : 2 3.4 5 * 10 2 3°45 100 i Rext [ka] Fig. 8 RC Oscillation Frequency Data (Typ.) Jane . . ' a No. 4364-17/49
LC6S43N/F/L, CCES46N/F/L AO | . t | 1, Absolute Maximum Ratings at Ta=25°C, VSS=0V : [Parameter [Symbol [ Conditions [in| _Uimis ‘| _anit_] Output voltage OSC2 Allowable up to Vv : voltage generated [impetveteee | Wi) _} __f osc) | asevpoets |v [way [ =i Tas, S| ato veo |v _| Input/output | vioa) [| Portof OD type] 03toxs Tv | Peak output 1/0 Port -2to +20 mA Average output Per pin over the period of || 1/O Port -2to +20 mA XIOA() | Total current of PCOto3, | PCOto3 PD0to3,PEOto3 (#2) | PDOto3 -15 to +100 mA PEO to 3 XIOA(2) | Total current of PFO to 3, CP0to3 PIO PGOto3, PAO to3, Pl0(*2) | PGOto3 -15 to +100 mA . PAO to3 Allowable Ta=-40 to +85°C mW power (DIP package) (MFP package) Operating 40 to +85 °C temperature Storage Tstg 55 to +125 °c fegemwe | | a 2. Allowable Operating Conditions at Ta=-40 to +85°C , VSS=0V, VDD=4.5 to 6.0V : Parameter Symbol Conditions Pin ae ed a ree Operating VDD VDD 45 v supply voltage} ee ed A Dc voltage = voltage (except 10) ee eee (except 10) of OD type VIR) Output Neh Tr. OFF INT, SCK, Si, 10 | 0.8VDD ane of PU type a - [vise | Exemalciockmode | osci__[osvpp| | vop | v_| No. 4364-18/49
- LO6543N/FIL, LC6S46N/F/L_ ee [ee [ome epee [ain [eyp-| max [ont] » ["LMevelinput [VILG) | OutputNehTr.OFF [Por [vss | oavpp |v | voltage | viL@ | OutputNehTr.OrF [INTSCK SI [vss | [o2svpp] v__ | - [vii [esr [vss | | oavop |v | [ving [RES vss | fozsvpp| Vv __ | . Operating fOP 200 4330 kHz : frequency (Teyc) (20) (0.92) (us) * External clock conditions Frequency —_| text sci 200 kHz Pulse width textH, textl] ¢ Fig. 1 Osci 69 ns: Rise/fall time «| textR, textF} OSC1 ns Oscillation guar- ceramic Fig.2 See Table 1. resonator OSC ee eed eee [Tai [op [max [anit] “H"-level input | MH) Output Neh Tr. OFF Port of OD type +5.0 BA current (including OFF leak current of Nch Tr.) VIN=+135V a a VIN=VDD current VIN=VSS. VIN=VSS [aie | vineves [REST | to TT a ee VIN=VSS “Level output| VOL) [TOLet0mA Pore TT as Tv port : ImA or less Hysteresis VHIS RES INT,SCKSI 0.1VDD Vv voltage OSC1 of schmitt . type (*4) No. 4364-19/49
__LCO6543N/F/L, LC6S46N/F/L__ a led eee [an [ap [ma] a] Current dissipation Ceramic IDDOP()| Fig.2. 4MHz VDD 25 mA External clock | IDDOP(2)} 200kHz to 4330kHz VDD 25 mA |. “1 Output Neh Tr. OFF at Operating mode , Port=VDD , | Standby mode | IDDst | Output Nch Tr. OFF VDD=6V | VDD 0.05 BA. Port=VDD. VDD=3V_|VDD 0.025 A + | Oscillation characteristics Ceramic resonator OSC Frequency £CFOSC Fig.2 fo=4MHz (*5) OSC1,OSC2 | 3840 4000 kHz Stubletime [CRS__| Fig3fociMBz | Ss 10 ms | Pull-up ' | resistance I/O port pull- | RPP VDD=5V |Port of PU 4 kQ up resistance type External reset ' | characteristics Serle | | lems | Pin capacitance | Cp f=1MHz, other than pins 10 premses[f | ismenamens | | | | LF | Serial clock iate = Fl [T at Cycle time a ee » | Cycle time 6) Input clock +CKL() Fig.5 SCK 10 ps “L"-level pulse width Output clock | tCKL(2) Fig.5 32xTcYq Hs “Level pulse width “H"-level pulse width ‘Output clock | tCKH(2) SCK 32x TCYq ps “H"-level pulse width Data setup time | tICK Specified for t of SCK 05 Bs . [Datahold time [eCKI TT Rig8 oss No. 4364-20/49
LC6543N/F/L, LC6546N/F/L__” ee Fatameer | Symbol Conditions , [min [ yp. [ma [an : | Serial output Output delay | «CKO Specified for | of SCK 05 ys time Nch OD only, External 1kQ. External 50pF , Fig. 5 Pulse output Period «PCY Fig.6 64x TCYC Bs “H'Jlevel TCYC=4 x System clock 32x TCYC BS Pulse width Period 10% “L"-level tPL Nch OD only, External 1k 32x TCYC ps Pulse width External 50pF £10% (*1) When oscillated internally under the oscillating conditions in Fig.2, up to the oscillation amplitude generated . is allowable. (*2) Average over the period of 100ms, . (3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 (or PAO to 3) pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the external clock oscillation option has been selected. (#5) {CPOSC : Oscillatable frequency. (*6) TCYC=4 x System clock period . osct (OSC2) ; OPEN a External clock : ceceeeeeeee lf ceeeeceeeeeeeeeeeeceedheceeeeeeeeen eedeeeeeeereseres 0.8 VDD noc eeeeceneefeee Yee nee ee cee ecedeeeeeccececes fesse eeeceeeeeees O.2SVDD text! ext textH text : Fig.1. External Clock Input Waveform : No. 4364-21/49
Table 1. Constants Guaranteed for s! » Z [input cna Load cirevit, «1k. : rae 0.3VDD the same as in Fig. 5.
LC6543N/F/L, LC6S46N/F/L_ une - 1, Absolute Maximum Ratings at Ta=25°C, VSS=0V Maximum VDD max VDD 0.3 to 7.0 Vv Pempaing | eT | gegen || rete EL. ae | ee | : [vig J Test RES | 03t0vDD+03 [Vv | ‘ Jinputfoutput | vioay | | Port of OD type| 0300415 | Vv ; voltage | ViO@ | Portof PUtype| O3tovDD03 | Vv | oe | me ee | current current 100ms YIOA() | Total curren of PCD to 3, PCO to3 t PDO to 3,PE0 to 3 (*2) PDO0to3 -15to +100 mA PEO to3 : XIOA(2)_| Total curren of PFO to 3, CHO to3 PIO : PGO to 3 PAO to 3, PIO PGOto3 -15 to +100 mA (2) PAO to3 Allowable Pd max(1) | Ta=-40 to +85°C mW power @IP_package) ' | dissipation Pd max(2) | Ta=-40 to +85°C Pm (MFP package) Operating Topg 40 to +85 °C temperature foo | | 2. Allowable Operating Conditions at Ta=-40°C to 85°C, VSS=0V, VDD=2.2 to 6.0V [ min. | typ. | max. | unit _| el eee supply voltage| “H’-level input | VIH() ‘Output Nch Tr. OFF Port of OD type |0.7VDD +135 voltage me | (except 10) - VIHQ) Output Neh Tr. OFF Port of PUtype | 0.7VDD PTY | we [estore tecem | , eo loge PL of OD type of PU type [wine [RES fosvpp] [vp | Vv | No. 4364-23/49
_ LCBS43N/F/L, LC6S46N/F/L : | min. [typ[ max. unit | - [*Levelinput | viay | OutputNehTr.OFF [Por vss | ozvpp[v_ | “| voltage [_vicay | Output Neh r.oFF __[INTScK si | vss_[ | o2vpp{ v__ | | vila) | Externalelock osca ves {| ossvpp] v—_ | [ving [esr vss P| oavpp |v ving) [RES vss || oavpp| v_ | Operating fOP When the 1/4 predivider 200 1040 kHz frequency (Teyc) option is selected, clock must (20) (3.84) (Us) (cycle time) not exceed 4.16MHz. External Clock conditions Frequency text Fig.1 When clock exceeds OSC1 200 4160 kHz Pulse width | textH, w= '1.040MHz, the 1/3 or 1/4 Osci 100 ns Rise/fall time | textR, textF }} predivider option is selected.| OSC1 100 ns Oscillation guaranteed constants | 2pin RC Cext Fig.2 O8C1, OSC2 22045% pF . | oscillation Rext 1241% kQ come | PP oscillation | 3. Electrical Characteristics at Ta=-40 to +85°C, VSS=0V, VDD=2.2 to 6.0V Condition Pin [aie [yp [mex [| ; | “H'develinput | IIH@) Output Nch Tr. OFF Port of OD type +5.0 BA current (including OFF leak current of Nch Tr.) : VIN=+13.5V i . THQ) Osc1 +10 [A current VIN=VSS PM Nimes OF eee] ee VIN=VSS [ue [vinevss RES as | to Ta ail VIN=VSS Ea ec voltage “Llevel output] VOLG) [1OL=3mA [Por Ta oe ee 1mA or Jess Hysteresis VHIS /RES,INT,SCK,SI 0.1VDD) v voltage OSC1 of Schmitt pe (*4) No, 4364-24/49
LC6543N/F/L, LC6S46N/F/L Parameter Symbol Conditions [aie ve. [me [ ae] Current Output Nch Tr, OFF at 2-pin RC OSC | IDDOP() | Fig.2 fOSC=400kHz (TYP) | VDD 10 4 mA Ceramic OSC | IDDOPQ) | Fig.3 4MHz, 1/4predivider| VOD || 20 | 4 | ma [pore [Peon | | VDD=2.2V | wpporw | Figs ook — fvpp | a0 | 25 | ma | | DOPE) | Figs BOKHe —tvpp | 5 | 40 | ma | External clock | IDDOP(6) | 200kHz to 1024kHz, VDD 25 mA 1/1 predivider 600kHz to 3120kHz, 1/3 predivider 800kHz to 4160kHz, 1/4 predivider Standby mode | IDDst Output Nch Tr. OFF Port=eVDD__ VDD=2.2V | VDD 0,025 |_ 5 A Oscillation characteristics . Ceramic OSC Frequency | {CFOSC | Fig.3 fo=400kHz OSC1, OSC2 364 | 400 | 416 | kHz (5) | Fig.3 fo=800kHz OSCI, OSC2 768 800 |. 832 kHz Fig.3 fo=IMHz OSC1, OSC2 960 1000 | 1040 kHz . Fig.3 fo=4MHz, OSC1, OSC2 3840 | 4000 | 4160 kHz 1/4 predivider Stable time tCFS. Fig.4 fo=400kHz. eee EE AMHz, 1/4 predivider 2-pin RC OSC Frequency Fig.2 Cext=220pFi5% OSC1, OSC2 546 | kHz Fig2 Rext=12kQt1% Pull-up resistance 1/O port pull- |_ RPP VDD=5V | Port of PU type ka up resistance External reset Reset time tRST See Fig. 5. ems [eeecmes | LLY | to be tested, VIN=VSS : No, 4364-25/49
"_LO6S43N/F/L, LC6546N/F/L fee [ee See he ee [aim | yp. [mac [uni Serial clock Cycle time - Cycle time . (16) [| Input clock +CKL(1) Fig.6 SCK ps "L'level pulse width Output clock | tCKL@) Fig.6 SCK 32x TCYC| ys pulse width Input clock tCKH() Fig.6 SCK us "H"-level pulse width Output clock | tCKH(2) | Fig.6 ; SCK 32x TCYC bs “H'-level pulse width Serial Input . oo CO time Data hold tCKI Fig.6 05 ps time : Serial Output : : Output delay | CKO Specified for | of SSK 20 | ps time Nch OD only, External 1kQ) Fig.6 External 50pF Pulse output leer | pulse width Period 410% "Level tPL Nch OD only, External 1kQ} PEO 32x TCYC ps pulse width : External 50pF| #10% (*1) When oscillated internally under the oscillating conditions in Fig.3, up to the oscillation amplitude generated is allowable. : (*2) Average over the period of 100ms. (3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. - The PA3 (or PAD to 3) pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the 2-pin RC oscillation option, or external clock oscillation option has been selected. (*5) f{CFOSC : Oscillatable frequency. (*6) TCYC=4 x System clock period No, 4364-26/49
_LC6543N/FIL, LC6546N/F/L SaSnerarae i osc (oscz) aE wee . OPEN ‘ : External clock a oe oe be ; aeeceeceenen|ceeeeeseeeceeseceetee poseeeeeeeead|seceteeeeecseeese OB VDD . . . cececesecere {eee eeeeeceeeeeedfecedpeceeeeeeeeeefaced|eeeeeeeenees O.SVDD text hextFh¢_ text text a Fig. 1 External Clock Input Waveform osci osc2 Osct osc2 R i Cext Rext ] : oo Coramie — C1 7 ~— c2 : Fig. 2 2-pin RC Oscillation Circuit Fig. 3, Ceramic Resonator Oscillation Circuit VDD wees eee eee Pee ecee nen eneneneneeeeeee= Lower limit of operating VDD osc Stabilized OSC Unstabilized a OSC period - tCFS Fig.4 Oscillation Stabilizing Period ; No. 4364-27/49
_ LO6543N/F/L, LC6S546N/F/L_ Table 1 Constants Guaranteed for : ; _ Ceramic Resonator OSC . 4MHz (Murata) 33pF£10% CSA4.00MGU | C2 | 33pF#10% CST4.00MGWU (builtin [ R | 0a | MHz (Murata) 100pF+10% CSB1000] 100pFt10% RES { R [220 | CRES (=0.1 IMHz (Kyocera) TOOpF+10% (044A) KBR1000F 100pF+10% ar 800KHz (Murata) O0pF10% : Fig. 5 Reset Circuit CSB800) 100pF10% | R{ 220 | (Note) When the rise time of the power supply is 0, 800KHz (Kyocera) 100pF#10% the reset time becomes 10ms to 100ms at KBR800F 100pF+10% CRES=0.1pF. If the rise time of the power [ R;| oO | supply is long, the value of CRES must be 400kHz (Murata) 220pF+10% increased so that the reset time becomes CSB400P 220pF+10% 10ms or more. PR 220 | 400kHz (Kyocera) 330pF#10% KBR400BK 330pF+10% [| R[ oa | texcy . 0.BVDD . yl text voD tCKO. SOpF - ° —_—_s i Fig. 6 Serial Input/Output Timing Poy . : ‘ o2svDD same as in Fig. 6. Fig7 Pulse Output Timing at Port PEO No. 4364-28/49
LO6S43N/F/L, LC6546N/F/L RC Oscillation Characteristic of the LC6543L, 6546L - Fig. 8 shows the RC oscillation characteristic of the LC6543L, 6546L. For the variation range of RC OSC ' frequency of the LC6543L, 6546L, the following are guaranteed at the external constants only shown below. . VDD=2.2V to 6.0V, Ta=-40°C to +85°C. . External constants Cext = 220 pF - Rext = 12kQ 284 kHz s fMOSC < 546 kHz . If any other constants than specified above are used, the range of Rext=3kQ. to 20kQ, Cext=150pF to 390pF must be observed. (See Fig. 8.) (*7): The oscillation frequency at VDD=5.0V, Ta=+25°C must be in the range of 350kHz to 500kHz. . (8): The oscillation frequency at VDD=2.2 to 6.0V and Ta=-40°C to +85°C must be within the operation clock frequency range. IMOSC-Rext : IN N | These characteristic curves are ‘000 SS given for reference only without § ERE SS C86 ics, _.
7 ESN ERNE
zw e/- +SNES *y 2 5-1] wwe g ,e_ LTS | of Ty | Q 2 ,/ 11) NAN ETT — Ww ee Tees 400 bi PLN N 2.3465 10 2 345 100 . . Rext [ko] Fig. 8 RC Oscillation Frequency Data (Typ.) . No. 4364-29/49
LC6543N/F/L, LC6546N/F/L Notes for Standby Function Application The .C6543/46 provide the standby function called HALT mode to minimize the current dissipation when the program is in the wait state. The standby function is controlled by the HALT instruction, PA pin, RES pin, and serial transfer completion signal. A peripheral circuit and program must be so designed as to provide precise control of the standby function. In most applications where the standby function is performed, voltage regulation, instantaneous break of power, and external noise are not negligible. When disigning an application circuit and program, whether or not to take some measures must be considered according to the extent to which these factors are allowed. This section mainly describes power failure backup for which the standby function is mostly used. A sample application circult where the standby function Is performed precisely is shown below and notes for circuit design and program design are also given below, . When using the standby function, the application circuit shown below must be used and the notes must be also fully observed. {f any-other method than shown in this section is applied, it is necessary to fully check the environmental conditions such as power failure and the actual operation of application equipment. 1, HALT moda release conditions 1-1, Supplementary description of release by serial transfer completion signal. On completion of serial transfer, the HALT mode is released and the execution of the program starts with an Instruction immediately following the HALT instruction. This function can be used to execute the program only when serial transfer occurs, placing the program in the wait state when no serial transfer occurs. This function is effective in reducing the current dissipation or clock noise. ° — Notes — © Release by the serial transfer completion signal is available only when the RC mode Is used for system clock generation; and unavailable when the ceramic resonator mode is used. © On completion of serial transfer, the HALT mode is released unconditionally. In an application, such as . capacitor backup application, where the current dissipation must be kept as low as possible during backup and serial transfer by external clock is also used, the HALT mode is released when serial data is transferred externally during backup. 1-2, Summary of HALT release conditions The HALT mode setting, release conditions are shown in Table 1. Table 1 HALT mode setting, release conditions HALT mode setting conditions HALT mode release conditions HALT instruction 1 Reset (Low level is applied to RES.) Provided that PAg 2 Low level is applied to PA3 (PA to PAg or PAgis program-selectable) is (PA3 to PAg or PA is program-selectable.) at high level. 3 Serial transfer completion. Note) HALT mode release conditions 2, 3 are available only when the RC mode is used for system clock generation; and unavailable when the ceramic resonator mode is used. No, 4364-30/49
LC6543N/F/L, LC6546N/F/L 2. Proper cares in using standby function : When using the standby function, an application circuit and program must be designed with the following in mind, {1) The supply voltage at the standby state must not be less than specified. {2) Input timing and conditions of each control signal (RES, port A, serial transfer) must be observed at the standby initiate/release state. (3) Release operation must not be overlapped at the time of execution of the HALT instruction. A sample application where the standby function is used for power failure backup is shown below as a concrete method to observe these notes. A sample application circuit, its operation, and notes for program design are given below. Sample application where the standby function is used for power failure backup Power failure backup is an application where power failure of the main power source is detected and the HALT instruction is executed to cause the standby state to be entered. The current dissipation is minimized and a backup capacitor is used to retain the contents of the internal registers for a certain period of time. After power is restored, @ reset occurs automatically and the execution of the program starts at address OOOH of the program counter (PC). Shown below are sample applications where the program selects or not between power-ON reset and reset after power is restored, notes, measures for instantaneous break of AC power, and notes for serial transfer. 2-1, Sampel application 1 where the standby function is used for power failure backup, - Shown below is a sample application where the program does not select between power-ON reset and reset after power is restored. 2-1-1. Sample application circuit — (1) Fig. 2-1 shows a sample application where the standby function is used for power failure backup, ve 01 100 e [Re ac R1(50) power . source: "0! . (up to Voo R2(10k) 1F) 06543746 PXxiNote) Yoo RR3(47k earn) ne R (500k) (10k); (yP) RES RS YI C21 uF) . (82k) (K) 1 Vss . Re: (12ky (Note) Normal input ports other than PAg Fig. 2-1. | Sample application — (1) where the standby function is used for power failure backup No, 4364-31/49
LC6543N/F/L, LC6546N/F/L. 2-1-2, Operating waveform in sample application circult — (1) ~ The operating waveform in the sample application circuit in Fig. 2-1 is shown in Fig, 2-2, The mode Is roughly divided as follows: (a) Power-ON reset (b) Instantaneous break of main power source (c) Return from power failure backup . . vt v+ . (alak | Saleanaiedaneieiats 4 seeeiiataiaiaiedeitniels a atekeneieeneate 9 V+TRON aed os Wf Px — = ° Tone Pee j Sin ES VI - ae “as Pp & 7 j 4
7 Ve Px 7 Ve Pre Bt |Z
Indeterminate X. Reset" X Normal mode X Reset (Normal mode )}+---{_Rieset_X Normal mode nye {a) Power ON reset {b} Instantaneous Instantaneous break {iii} . break {i), (ii) HALT instruction sy proce ccc nonce SS == y ‘ } — . \\ J une aT] NM Res Va. Pxx / a Ty nn A . HALT mode I Return from power fare bck Return fi failure back HALT instruction {€} Return from power felure Backup V+TRON: V+ value when TR is turned ON/OFF Fig, 2-2 Operating waveform in sample application circuit — (1) 2-1-3, Operation of sample application circuit — (1) (a) At the time of power-ON reset After power rises, a reset occurs automatically and the execution of the program starts at address OOOH : of the program counter (PC). : — Note — This sample application circuit provides an indeterminate region where no reset occurs before the operating Vbb range is entered. ee No, 4364-32/49
LC6543N/F/L, LC6546N/F/L {b) At the time of instantaneous break (1) When the Pxx Input voltage does not meet Vi_ (the Pxx input level does not get lower than Input threshold level Vj_) and the RES input voltage only meets VIL: A reset occurs in the normal mode, providing the same operation as power-ON reset. (ii) When both of the Pxx input voltage and RES input voltage do not meet VIL: The program continues running in the normal mode. . (lil) When both of the Px x input voltage and RES input voltage meet ViL: When two pollings do not regard the Px x input voltage as “L" level, the HALT mode is not entered and a reset occurs. When two pollings regard the Px x input voltage as “L” level, the HALT mode is entered and after power is restored a reset occurs, releasing the standby mode. {c) At the time of return from power failure backup After power is restored, a reset occurs, releasing the standby mode. 2-1-4. Notes for design of sample application circuit — (1) @ V+ rise time and C2 Make the time constant (C2, R) of the reset circuit 10 times as long as the V* rise time. (R: ON-chip resistor, 500kohms typ.} Make the V* rise time shorter (up to 20ms). @ RilandCt Make the R1 value as small as possible. Make the C1 value as large as possible according to the backup time calculated. (Fix the R1 value so that the C1 charging current does not exceed the power source capacity.) @ = R2and R3 Make the “H”-level input voltage applied to the Pxx pin equal to Vpp. @ R4 : Fix the time constant of C2 and R4 so that C2 can discharge during the period of time from when V* gets tower than V+TRON (TR OFF) at the time of instantneous break until the Pxx input voltage gets lower than VIL (because release by reset is not available after the HALT mode is entered by instantaneous break), e@ RS and R6 Make V+ (VBE#0.6V is obtained by R5 and R6) when the reset circuit works (Tr ON) more than (operating Vpp min + Vg of diode D1}. Observing this note, make V*as low as possible to provide a reset early enough after power-ON, @ Backup time The normal operation continues with a relatively high current dissipation from when power failure is detected : by the Px x until the HALT instruction Is executed, Fix the C1 value so that the standby supply voltage is held during backup time of set + above-mentioned time, 2-1-5. Notes for software design © Design the program so that port Ag to Ag cannot be used for standby release and port Ag is brought to “H” level at the standby mode. @ Check a standby request by polling the input port twice. (Example) BP1 AAA 71st polling RCTL 3 interrupt inhibit BPI AAA :2nd polling . HALT Standby AAA: : . 2-2, Sample application 2 where the standby function is used for power failure backup Shown below is a sample application where the program selects between power-ON reset and reset after power Is restored. No. 4364-33/49
LC6543N/F/L, LC6S46N/F/L 2-2-1, Sample application clrcuit — (2) (No Instantaneous break in power source) ~ Fig. 2-3 shows a sample application where the standby function is used for power failure backup. . yw «ot 100v 8 om @ || ot power» 60) tre Yoo Vo PXX{Note) om Y Re (SENSE) . (up to 1F)] RB (100k) “pret (100k) .06543/46 Yoo R (500k) Ra (ry) (10) RES 172 02 RB (EF) Vss : (82k) i TRI R6 ) (Note) Normal input ports other than PAg (2h) Fig. 2-3. Sample application — (2) where the standby function is used for power failure backup 2-2-2. Operating waveform in sample application cifcuit — (2) The operating waveform in the sample application circuit in Fig. 2-3 is shown in Fig. 2-4. The mode is roughtly divided as follows: (1) Power-ON reset (2) Return from power failure backup vt Cog TT TI V+TRON ociiiomeie’ y -_ y fi SE son fe | 7 Px. fav in Indeterminate X Reset \\\\y Normal mode Power—ON reset Pxxe"L" is detected. . ve ———— V+tRow vi Yoo aN ae \\L erm nee A ees 7 ‘ | a Nv Pre Vu. Pex Bo / 7 \\ {|Z — ff HALT mode SS Return from power failure backup. HALT instruction Pxx="H” ts detected. V+TRON: V+ value when TRI Is turned ON/OFF. Fig, 2-4. Operating waveform in sample application circuit — (2) . No. 4364-34/49
LCB543N/F/L, LC65S46N/F/L "2.2.3, Operation of sample application circuit — (2) * . (a) At the time of power-ON reset . The operation and notes are the same as for sample application circuit — (1), except that after reset release Pxx="L” is program-detected to decide program start after initial reset. (b) Standby initiation When one polling regards the Px x input voltage as “L”’ level, the HALT mode is entered, {c) At the time of return from power failure backup After power is restored, @ reset occurs, releasing the standby mode. After standby release Pxx="H” is program-detected, deciding program start after power is restored. — Note — If power is restored after Vpp during power fallure backup gets lower than Vjy on the Pxx, Pxx="L" may . be program-detected, deciding program start after initial reset. 2-2-4, Notes for design of sample application circuit — (2) e@° R2and R3 Fix the R2 value so that R2>R1 is yielded and fix the R3 value so that 1g of TR2 is limited. @ R4 There is no severe restriction on the R4 value, but fix it so that C2 can discharge quickly. Other notes are the same as for sample application circuit — (1). 2-2-5. Notes for software design © Design the program so that port Ag to A2 cannot be used for standby release and port Ag is brought to “H"” : level, @ Check a standby request by polling the input port once. . {Example} . BPI AAA Polling HALT Standby AAA: : No, 4364-35/49
LC6543N/F/L, LC6546N/F/L 2-3. Sample application 3 where the standby function is used for power failure backup, . —_— 2-3-1, Sample application circult — (3) (There is an instantaneous break in power source.) Fig, 2-5 shows a sample application where the standby function is used for power failure backup. [Re¢}—+- woov : D1 . AC Ri (50) power Voo TR2 source 7 RXxX(Note) cr ah 3 Yl. (SENSE) Kup to 1F) “] (100k) (100k Loes43/46 (12k) Voo {) tra (500K) tty are vr (10%) Res TIL.C2 (1 F) RS Vss (82k) fo K) tat (Note) Normal input ports other than PAg (12k) Fig. 2-5, Sample application — (3) where the standby function is used for power failure backup 2-3-2. Operating waveform in sample application circuit — (3) The operating waveform in the sample application circuit in Fig. 2-5 is shown in Fig. 2-6. The mode is roughly divided as follows: (1) Power-ON reset (2) Instantaneous break of main power source (3) Return from power failure backup ve (ana [Renee | ne po aA VtTaION Se = { T Ty —— — . ar a ae Vl wea ML 1/ — I ey | 7 it | + vtrnaow Ye | 1 Poll va Pex | HK vermont 7 [7 ex Tt. FF vn es Va Pac I V/ 1 or | Wd Normal cade \\ Feast yf Nerrat wade)( Reset YM Normal mode V---( Reset Nore! mode nit wi Powe—oNo | Oceana | [PBFA ote dont xxe ET Bes Pxxe"H" is detected, HALT instruction {Pxx="L" is detected.) wee process nec cee e eee ‘1 aN Yo ver je ‘ | “7 Via Py \\ ial ia Pax Yt i Lf : Virasow ee Pxx Fly Vu FES Lan end) Vy norte YO mode Wp-=- == ~ ALT mode __ Hest YC Normal mode ——— | (3) Return from power HALT instruction (Pxx="L" Is detected.) failure backup Pxx="H" Is detected. V+TRION: V+ value when TR} is turned ON/OFF V+TR3ON: V+ value when TRS is turned ON/OFF Fig. 2-6. Operating waveform in sample application circuit — (3) ; eS No, 4364-36/49
LC6543N/F/L, LC6546N/F/L 2-3-3. Operation of sample application circuit — (3) ae (a) At the time of power-ON reset : The operation and notes are the same as for sample application circuit — {2) {b) At the time of instantaneous break (i) When the Pxx input voltage does not meet Vi_ (the Pxx Input level does not get lower than input threshold level V}__) and the RES Input voltage only meets VjL: A Teset occurs in the normal mode. After reset release Pxx="'H” is program-detected, deciding program start after instantaneous break, __ (ii) When both of the Px x input voltage and RES input voltage do not meet Vii: The program continues running in the normal mode, (iii) When both of the Px x input voltage and RES input voltage meet VIL: When two pollings do not regard the Pxx input voltage as “L” level, the HALT mode Is not entered . and a reset occurs. When two pollings regard the Px x input voltage as "L” level, the HALT mode is entered and after power is restored a reset occurs, releasing the standby mode, After standby release Pxx="H” is program- detected, deciding program start after instantaneous break, (c) At the time of return from power failure backup The operation and notes are the same as for sample application circuit ~ (2) 2-3-4, Notes for design of sample application circuit ~ (3) e@R3 Bias resistance of TR2 © R7 and R8 Fix the R7 and R8 values so that TR3 is turned ON/OFF at approximately 1.5V of V+. Other notes are the same as for sample application circuit — (1) 2-3-5, Notes for software design Same as for sample application circuit ~ (1) 2-4, Notes (1) for providing serial transfer Notes for providing power failure backup and serial transfer This application assigns top priority to power failure backup. When power failure backup is provided, serial transfer may not be provided normally. (1) When the internal clock is used for the serial clock: Execute the serial transfer start instruction immediately before executing the HALT instruction. If this is done during serial transfer, the power failure backup mode is entered without normal transfer. (2) When the external clock is used for the serial clock: When power failure Is detected, it is most prioritized that the HALT mode is entered, providing power failure backup, It is necessary to design an application system where no release signal by seria! transfer completion is input to the HALT instruction execution cycle and no release signal is input during backup. 2-5. Notes (2) for providing serial transfer Notes for providing HALT and serial transfer for program standby without power failure backup This application assigns top priority to serial transfer. The following notes for system design must be observed. (1) When the internal clock is used for the serial clock: Transfer starts when it is ready on both sides. When transfer is not ready on the other side, the HALT instruction is executed to reduce the current dissipation. When transfer is ready, the HALT release signal (RES, PA) causes return from the standby mode, starting serial transfer. (2) When the external clock Is used for the serial clock: Synchronization must be provided between microcomputers to prevent the HALT instruction and HALT release signal (RSIOEND) from overlapping. When transfer is ready, the serial transfer start instruction is executed and the program Is placed in the wait state. The other side adjusts time so that no overlap occurs between the HALT instruction and transfer completion and starts serial transfer. On completion of transfer, the HALT mode is released and the program is executed with an instruction immediately following the HALT instruction. No. 4364-37/49
‘LC6543N/F/L, LCB546N/F/L Notes for Program Evaluation @ When evaluating the LC6543/46 with the evaluation chip (LC6594, LC65PG43-A/46-A, LC65PG43/46), the - following must be observed. 2-pinOSC]Plp and OSC2 share one pin | Evaluation chip has Pig and] Since input/output at Pig on (Plop/OSC2). Either of them | OSC2 separately. Pin required | evaluation chip results in dif- is selected exclusively by user | for option is selected as requir- | ference between evaluation chip option. ed. Even when OSC2 pin is | operation and mass-production _ When 2-pin OSC is selected, | selected by option, Pig circuit | chip operation, input/output at. Plp/OSC2 pin provides OSC2 | is. present and functions as | Pig Is prohibited. . . and performs no function of | complete port Plo. Plo port. Data input to Plo/OSC2 by mistake is always read as “0”. 3 selections (1/1, 1/3, 1/4) |3 selections (1/1, 1/3, 1/4) | DIV pin, 30R4 pin must be set by option available by 2 pins of DIV | according to option specified for § pin, 30R4 pin. mass-production chip, a
5 Ports C,D | Ports C, D can be brought to | Port C and port D can be | CHL pin and DHL pin must be
3 output “H" or “L" in a group of 4 | brought to “H” and “L” by | set according to option specified © | level at bits. CHL pin and DHL pin respec- | for mass-production chip. 2 | reset tively. . mode . Port PU or OD can be selected | Only OD without PU. [LC6594-applied evaluation] output bitwise. . External resistor (10kohms) on configura- evaluation board must be connect- tion ed to necessary port. . PU/OD [Piggyback-applied evaluation} Resistor must be connected to necessary port on application board, PU PU resistor brought to Hi-Z | PU resistor, being external resis- | For mass-production chip, leakage resistor (Pch Tr to turn OFF) at “L” | tor, whose impedance remains } current only flows in Pch Tr configura- | output mode. unchanged at “L”’ output mode, | at “L” output mode; for evalu- tion ation chip, current continues flowing in PU resistor at “L” output mode. No, 4364-38/49
LCB543N/F/L, LCBS46N/F/L Fe a5 Se Notes for evaluation i osc [2-pin RC OSC] [2-pin RC OSC} [2-pin RC OSC] . constants | Catalog-guaranteed constants | Different from mass-production | Frequency must be adjusted to -1 provide OSC at frequency} chip in circuit design and | OSC frequency of mass-produc- specified in catalog, characteristic, tion chip by adjusting variable resistor. 3 [2-pin ceramic resonator OSC] | [2-pin ceramic resonator OSC] [2-pin ceramic resonator OSC] . Catalog-guaranteed constants } Different from mass-production | External constants must be fine- . 2 provide OSC at frequency} chip in circuit design and | adjusted according to service H specified in catalog. characteristic. conditions.
2 Wiring capacitance may provide
unstable OSC. osc [2-pin ceramic resonator OSC] | [2-pin ceramic resonator OSC] [2-pin ceramic resonator OSC] constants | Feedback resistor is contained. | No feedback resistor is con- | For evaluation chip, feedback ~2 tained, resistor of tMohm must be connected externally. osc OSC frequency characteristic | Different from mass-production | ES, CS must be used to evaluate . 8 frequency} as indicated In catalog, chip in circuit design, and | characteristic in detail. Bal characteristic. The standby current cannot be ee evaluated in detail, However, the SB Operating} Current characteristic as indi- | Different from mass-production | standby current can be confirmed Bg) current, | cated in catalog. chip” in’ circuit design, and | roughly in the manner discussed 28} standby characteristic. later, Be sure to confirm the current standby current, Operating} Supply voltage range as indi- | Evaluation chip must be also voltage cated in catalog. used at Vpp=5Vt5% at which EPROM, other LSI are used. g Operating] Temperature range as indi- | Evaluation chip must be used at &| temper- | cated in catalog. 10°C to 40°C. § | ature Fs PortA Input/output configuration of | Input/output configuration of s input normal threshold input. low threshold input. 9] voltage Input voltage as indicated in| Different from mass-production & catalog. chip in input/output configura- 8 tion. Type No. | LC6543/46 differ in ROM,j RAM capacity is set by RAMC | SW3-2 on evaluation board Is setting RAM capacity. pin according to Type No. always placed in PA position. SW3-1 is set according to Type No. : No, 4364-39/49
LC6543N/F/L, LC6546N/F/L eee {Confirmation methods for the standby function) The standby current at the standby mode of the simulation chip can be evaluated not exactly but approximately, Then, do the following steps. {a} Confirmation of the standby state Be sure to confirm whether or not the LSI enters the standby mode when the standby conditions are satisfied. (i) When the OSC1 and OSC2 oscillation option is selected, confirm on an oscilloscope that the oscillation stops in the standby mode. (ti), Confirmation by the current dissipation Remove the EPROM when confirming whether or not the LSI enters the standby mode. The Ipp of the LSI can determine whether or not the LSI is now in the standby mode. When the LSI is in the operating mode, more than some 100HA current is transmitted, When in the standby mode, the current of the Ipp is 150uA or less if the DIV, 30R4, CHL, DHL and RAMC are all set to “H (excluding the load current). If the DIV, 30R4, ——-, etc. are all set to “L", the current of tha Ipp is approximately 20uA. (b) Confirmation by the load current Your program must be designed so that the current is not transmitted to the input/output ports prior to the execution of the HALT instruction, This can reduce the useless dissipation of the load current at the standby mode and be confirmed on an oscilloscope. (i) Design your program so that the current Is not transmitted to the output ports prior to the execution of the . HALT instruction. (ii), Design your program and peripherals so that the input ports and input/output ports are not brought to the floating state at the standby mode, If brought to the floating state, current flows in the microcomputer input circuit section, causing more current dissipation. Therefore, the backup enable time is shortened extremely in applications where the capacitor backup is used. Ceramic resonator oscillation constants when the EVA-TB6543/46 is used When developing your program using te target board EVA-TB6543/46, use the constants shown below because the ceramic resonator oscillation constants depend on the conditions for evaluation and the cable length, etc. Note) When the evaluation chip is used in the 2-pin ceramic resonator oscillation mode, no feedback resistor is contained unlike the mass-production chip. Connect a feedback resistor of 1Mohm externally as shown below. Since constants R, C are also differ from those for the mass-production chip, refer to Table shown below and adjust the capacitor value according to the stray capacitance of the circuit. Evaluation chip © [Mass-production ChIP cesaaN/F/L . - LCE5PG43/46 UC6546N/F/L osct | ee osc2 oscT osc2 ° 0 a : o pesenateg on Fenty? 7 ti) ii} 2-pin Ceramic Resonator Oscillation Circuit for Evaluation Chip and Mass-production Chip ee No, 4364-40/49
LC6543N/F/L, LC6546N/F/L Table of Ceramic Resonator Oscillation Constants when the EVA-TB6543/46 is used ~~ [| Evaivationchip (*) Mes-production Including no capacitance of chip C1= C2 standard cable standard cable { ci=c2 [oR [ cisec2 TR | anne [Coat 00wG muro [aap __| oF _{ ohm _{_si0f__[ Goh ["KBR4.0M (Kyocera) | 33pF opr | ohm | 33pF | ohm | {CSB1000D used) CSB1000K (Murata) 82pF . 220pF KBRIO00H (Kyocera) | _100pF_[82pF_ | Oohm | 2200F | Oohm | {CSBB00D used) CSB800K (Murata) B00kHz 220pF [KBREOOH (Kyocera) |" 220pF | 150pF TO ohm [7 160pF [ohm | [_csea0or "{Murate) | 330pF | 470pF [ohm | 470pF_ {| Oohm | KBR400B : (Kyocera) 330pF 390pF 0 ohm KBR400H (*) The standard cable is a cable attached to target board EVA-TB6543/46. The Table shows two cases where the capacitance of the cable is included and no capacitance of the cable is included. + Example where the capacitance of the cable is included The capacitance of the cable is included when the resonator is connected to the user’s application board through the cable from the EVA-TB6543/46. + Example where no capacitance of the cable is included No capacitance of the cable is included when the resonator is placed near the evaluation chip (on the EVA-TB6543/46). When using any other cable than the attached cable, adjust the capacitor value according to the stray capacitance. a No, 4364-41/49
LC6543N/F/L, LC6546N/F/L_ “How to use the piggyback chip (LC65PG43/46-A) — (1) Layout of pins and control pads, and External dimensions . rT Loseroceaien ee sssse GOO0GOO e8n8233 DOOOOOO Qo ze Yo @az Vee @ PESOT ergeerncy gernenmened 30) PER wo2@ aim = Y @zp rer Aes ih Prosi] 3 © 98 48 Oapreo qs 3H Prisso a @A5 a9 Oz ros q27 4p Pr2/SERIS GA Att G25 Poz qs sh PrIANTO 6 5 25) POL o* vs @ ge ef t : q poz 9 @A! oy vs @azh pce dz ob pos Gro@ a0 BB 07 @aprcr dz wp rardiegor a m pupres die mp PAZ g 18 1 Ves ¥ magne? sam] [ot Sibresr ee: Piovosoz Qin 28102 Oe poser dis ©) Gish PAD2 PADI TOP VIEW BOTTOM VIEW PAD1: Power supply pad , PAD2: Mounting pad for oscillation circuit components fa} fs H bs} aie | t= lol iy {2 i . la} ia} Hi— fs fa HE= lay lal — K— 19.0 —>t . ea 2,92 ~ [es 10.16 ee SnEe No. 4364-42/49
LC6543N/F/L, LC6546N/F/L (2) How to rhount EPROM The EPROM to be mounted should contain an already-assembled program data. To write data to the EPROM, use the EPROM writer function on the EVA-800 or EVA-410C board. The mountable EPROM is an Intel 2732, 2764 or their equivalents. EPROM (2732 or 2764) for program data (-) Ra) Bd CRO XORCHCCHONOKONCKONONONS) |O jo 10) 0} i joy jo ‘= jo) io) jo i aA! popooooSOOOOOD (3) Power supply for EPROM A typical EPROM dissipates the current of 50mA to 100mA. If the power capacity of an application product board is not sufficient, use an independent power supply circuit to provide the EPROM with the current . externally. a) At the factory shipment, the EPROM uses the same power supply circuit as the simulation chip does. To supply external current to the EPROM, the EPROM power supply selection jumpers are provided on the : reverse side of the simulation chip. At the factory shipment, the circuit connection is arranged so that current can be supplied to the EPROM through the power supply pin (Vpp pin) of the simulation chip. sgt Wired at the factory shipment tt jit o t pevers* “ use quate! {A) Connected to the GND (OV) pin. —_ Simulation chip . (B) Connected to the EPROM power supply pin. {C) Connected to the power supply pin of the simulation chip. [Note that the circuit connection is arranged at the factory shipment so that the current can be supplied to an EPROM through the simulation chip.} b) To supply current to an EPROM externally from an independent power source Disconnect pattern (B) from pattern (C). Connect the power supply pin (+5V) of an external independent power source circuit to pattern (B) and then the other pin to pattern (A)(GND). ov - +5V sde ON . reverse ue quel Simulation chip {To supply current to an EPROM from an external power source circuit.] (Note) A simulation chip Is an LS! produced in CMOS process technology. The simulation chip will suffer from a “latch up” which is specific to CMOS LSls if the voltage below the Vss level is applied to input pins and output pins, or if the voltage above the Vpp level is applied such pins. The latch up problem may damage or degrade the device. To prevent it, much care should be taken to the power supply circuit design for the simulation chip and an EPROM. . In turning on a simulation chip and an EPROM, the simulation chip should be the first and the EPROM, the second. To turn off them, the order is reversed, en No, 4364-43/49
LC6543N/F/L, LC6546N/F/L (4) Switches and pad for option selection - a) Switches for CPU-function settings On the simulation chip are provided the switches for selecting a RAM capacity, a desired CPU and its stack level, output logic level at reset for ports C and D, divider circuit's divide ratio, and P!0/OSC2 pin function, These switches are provided on the surface of the simulation chip board. The figure below shows the outline of the above switches, The switch settings will be described in the item dealing with option specification methods. . -_ ao 2 9 8 goddo000 WoOUDUU OI SILD Pin 1 position , ° fe) O° ° Switch 4 (3 or 4), ,}Selects the divide ration for the divider circuit. Switch 7 (RAMC) . . . Select a desired CPU from LC6543 and LC6546. b) Pad2 The pad 2 is provided on the piggyback LSI to mount oscillation components. Add an external resistor according to a selected oscillation option, The switch settings will be described in the item dealing with option specification methods, Top View . Osci : connected to the OSC1 pin of the LSI. P10/OSC2 _: connected to the P10/OSC2 pin of the LSI. PIO/ Vv : connected to the Vgs pin of the LSI. O oscz ° $s ssP O vs ° ° ° o osc} ° Pios : © oscz ° a ET No, 4384-44/49
LC6543N/F/L, LC6546N/F/L. (5) Option specification methods ~ a) Option specification method for oscillation circuits Oscillation circuits can be selected by using the PAD2 and CPU-function setting switches. (1) Ceramic oscillation circuit Piovosc2 * Connect the PI0/OSC2 pin with the OSC1 pin through an external 7 resistor of MQ. ima S [2] || vss * For the oscillation constants of an application board, refer to the osc1 catalog. Fine control may be needed because the ideal RC constant will change due to mounting conditions. * Switch 1. . Set it to the OFF side. pees e ef iM Switch 2 . . Set it to the ON side, *) inl i 0 0 i ial * The PIO/OSC2 pin can be used as OSC2 pin for oscillation, oun lore CPU-function setting switches {ii} 2-pins RC oscillation circuit Pl0/0SC2 * No external component is required by the PAD2, + For the oscillation constants of an application board, refer to the (2) || vss catalog. B ose! Fine control may be needed because the oscillation frequency of a mass-production LS! might differ from that of the application board. lon * Switch 1. . Set it to the OFF side. eaconod Switch 2 . . Set it to the ON side. au lore =” The P10/OSC2 pin can be used as the OSC2 pin for oscillation. CPU-function setting switches (iti) External clock circuit Plovosc2 + No external component is required by the PAD2, [2 4] vss (3) |] ose1 -wawwen | + Switch 1... Set it to the ON side. ARUOOUO Switch 2 . . Set it to the OFF side. ou OFF * The PIO/OSC2 pin can be used as the input/output PIO port. a No, 4364-45/49
LC6543N/F/L, LC6546N/F/L b) Option specification method for dividers . Dividers can be selected by using the CPU-function setting switches. . (4) 1/1 divider circuit . -~aaenon | HOWOOUU + Switch 3 .. Set it to the OFF side. Sun OFF Switch 4 . . Set it to either side. (il) "1/3 divider circuit eames anon |W eo + . a a I. | a 0 0 + Switch 3 . . Set it to the ON side. Switch 4 . . Set it to the ON side. Onn OFF . (til) 1/4 divider circuit - << n | ( i] i aa fl i] . * Switch 3. . Set it to the ON side, . PAT OFF Switch 4 . . Set it to the OFF side. ¢) Option specification method for the output logics of ports C and D at reset The output logics of ports C and D at the reset can be specified by using the CPU-function setting switches. (1) To set the logic level of port D or C at the initial reset to ‘‘H” (output OFF in case of open drain output) eo ee be * Set switch 5 or switch 6 to the ON side. ia i i ia ia inl in * The output logic level of port D or C at the initial reset . eum Orr can be specified independently. (ii) To set the logic level of port D or C at the Initial reset to “L”. =m ee | + Set switch 5 or switch 6 to the OFF side, . o i ia 0 W * 0 * The output logic level of port D or C at the initial reset oun Orr can be specified independently. d) Option specification method for evaluated CPUs Evaluated microcomputers can be specified by using the CPU-function setting switches. {1) To develop user application programs for the LC6543 microcomputers. -aneown |W OOCOUUR + Set switch 7 to the OFF side. Ouk jOFF (i) To develop user application programs for the LC6546 microcomputers. examen on |W : OUUUUOS + Set switch 7 to the ON side. , oun OFF ENN No. 4364-46/49
LC6543N/F/L, LC6546N/F/L C6543, LC6546 SERIES INSTRUCTION SET (BY FUNCTIONS) , - “Symbol “Baseripition” - : AC Accumulator MIDP] — : Memory addressed by DP (ML T:Contenss AG :Accumolatorbitt PIOPL) —:InpuVoutput port addressed by DP = rTranster and diction . cr Carry flag Pc Program counter: + Addition cml Control register STACK — ; Stack register - Subtraction or Dats pointer ™ Timer A AND E 26 regime TMF Tier (internal interrupt requeet fag v ron EXTF External Interrupt request flag As, Ha, Le : Working register Exclusive OR Fa lag bit a Fad 1Zere tisg “ Memory 107060504103020100 i [aa Jewrne [i dolo oooh | emo watammrnvarnet [a [ete Jew er [rte foo ot fp fs fermo [tech ene saemnd. |e |] a CO ep § [ou [eonotenen ae [Vv of [ef fae =0___[ tw Ateneo [J | § [ime |reement 0 Joo oo [afr [acme Firearm [zr er | § [ore —Jowenmen ac Joo o ofr ras [ifs [ac mcm [twat ontansnasemnene-1-” [2 oF [| 5 Rotate AC lett ACoMICF}.ACr+ie | The AC contents are shifted left through jf [ete eee e[ones ph feceaey™ [te | [ieee Soe T foo TT enue) [eat tomaromtmere me | [J [eat Jesctage ae win Joo @ ofr op fr fmae [Teggapens ear reoiearem ||] [imu —[incamens mw foe PO[T 1 + 0 [i [i pwon—WaSh IT [te WtOr amnewshowendei [ee [| [atin —Joweromen wm ——fo-9 VO[T 14 1 [i [1 fwOP=GWDAI—1 [rw OF eee davon’ 1, [2F_er |] [A single Bit ofthe MIOP) specified with i the TDPT pec Binary ade tents and tha result is stored in the AC. joooo| AC =1AC) + (MLOPH) [ORE cnt AC creo s ‘Add M 10 AC with CF oO oO |and the M(DP) contents is performed and [ae | _ [ooo] ee BEE tee remit ik moredintne Re Decimal adjus: AC Decimal adjust AC ‘Santas and Be MTOPY content H Exclusive of M to AC AC (AC) ¥ (M(DP)) | are exciusive-ORed and the result is stored] | | 7 In the AC. q ans OPTS g AC =(AC) A (MIDPI), gg, ANDed and the remit ie stored in the i "The AC contents and the MIDP] concent AC mincIV (M10PI)_ | fre ORod ted the ru t mored ne Compare AG with M (MIO) + IACI +1 [Teaco ue Ct and 2eee set/resat_ [ Comparison res [CFT ZF] (mop y>iacy To fo) 3 [tmorysiacy [1 [a | i (mioPiy<cacy Jt | 0] Compare AC wih [0010 Tylgiyig HIAC)+1 | the AG contents end the immediate g Compare AC min 10 0 30 dats Ialghyig are compared and the ZF and CF ore sat/resat. [Comparison reat T CFT 2F_) istetytp =a [1 | Usighiocaciy 1 To Compare OPi with [0010 ADPLIV Ig tat to | The DP, coments and the immediate immediate date o1o1 ‘daa Iglzt tg are compared. Coad AC wan “Tha ait date Talgh lg i onde To smmediate data the AC. [Estee ne em Joo [oor oft [wanmiaci | reatcoammonsonsmuenon| |_| [x= [eee ae trom [oo to foo 01 [1 [i fac (wom) | the mioricomeesaretonied insta ac] ze [| Exchange AC with M ‘0 MzMiMo ACIS [MIDP)) The AE contents and te OTT ne waa § then modity OPH DPA IDPH ¥ Bie cantante re reifcd with he rerorgt q with immediate date OM2M1Mo __| coments of (DP4y] YOMgM Mo. OM My t Exchange AC with M 0000 1AC1 5 (MIDPI) ‘The AC contents and the MIDP) coments ara exchanged. zF Exchange AC win M| (AC) = (MDP) ery a Te MOP he Exchange AC wih M. vray (AC) = (M(DP)) Tee eng Setemtagenag tte ior the | ZF Ahen decrement DP. DP. -{OP1}—1 DP, contents are decremented —1. RTBL [Read sable dave trom| oot AC E-ROM Pet sons lowcarder 8 bis ave reiaced program ROM 1PCh.E. AC) with the E and AC contents are loaded in . the AC and No. 4364-47/49
LC6543N/F/L, LC6546N/F/L.
Description
D7 060s D4 |D302 Ds Dp . ‘Lose DPu with Zero and| OPu =O The Dy and BF ore loaded wath O ard G OFe with immediate DP miatats io [the immediate data 19121; 1q respectively. i data respectively Lit data} load OPx with The DP} Is loaded with the immediate : i immediate data daa lglalylg- [ico [cones on. [vO [T Le [Jon rome [ter ememow [FF [J § [ozo —[oeeenene on Jr 0 [11 [rt [m= tomate comin deme -1— fae [J [free ae BAP Yo Tf Yor aes fei ameter F xAL Exchange AC wah tv 10 ‘Tha AC contents ond the contin of XAO |workng register Ar [1 1 1 0 FOO}0 0 tAC) (AO) ‘working register At ore excharged. xAt 1110 f0 1100 (Ac) (A Ae ata ane of Mo Ar- Az. Ma XA2 111 0§1 of0 0 (AC) S1A2) sexordloa O80, XA3 111081 1:00 (AC) 34 A3) Fi Exchange Ox with 2 “The OP contents and the contents of 5 Bs, 3. bee [So Para hashes 0 fa soo; | rte ae ee Fe title o (DPM) SSUHTY ‘eccording to a. Xba | Exchange DP with ° "Tha OP|_ contents and the content OF xu 0:10 0 |T (OPQ SCR tom, H AEB tag 83878180 Fa 0 “Tha fag epecified with BgB2B Bp & rest, Tes top ovens i ane sina pret ioetyhe 3 oe Tas sham coving te 6 H Si re Sine atone * fas Bib IMP addr} Jump in the cunent [0 11 0/1 PoPePe PCoPinPaPaP2PePs|A jump to the sddress- specified bank P7 Pe Ps Pal Ps P2Pi Po PaPaP2PiPo | With Immediate dete PyoPgPeh7Pe PaPaP ga PyPo oeaure. mp reent <0 1 ‘A jump to the address specified with Jump a ine currant PCr~0 1E.AC) | A Jump to the address spacified with” g page modilied by 8 bits are replaced by the E and AC and AC cantents occurs, i Call subroutine in the IP3P2P1Po STACK = (PCH+3 A subroutine in page 0 of bank 0 is called. 280 page PC w~6.PC1 ~0 0 . :. PCa~7~PaP21Po Call subroutine in the | 1 0 4 Ot PwPoPe STACK (PC) +2 A subroutine in bank 0 is called. 3 ze bank IP? PePePalPsP2P1 Po PCie~0 OPP SPaP? ? PePsPaP3P2P1Po [et__[Pawn ton nbomelor1 [oor oi |i[rc—istacr) [Awontomenbentaon [|_| ATL Return from mntectupt ‘Areturn from en interrupt service routine | 77 CF tounne occurs, Trait “The banks changed Seeroe ‘A pueudo 1/0 ports specified, = Branch on AC bit 0111/0 0tit6 PCr~0.— P7 PePePa | I1 # single DR of the AC specified with IP? Pq Ps Pa|P3P2P1 PO 2 PaPiPo | the immediate outa tytg ft. 8 branch 10 the address specified with the immadiat ACE) Oma PzPeP sr 4P PoP Pq within the same ope occurs, If a single bit of the AC tied wit Branch on no AC bit |O 011410 O1ito PC) -o— Pr PePsPa the mainte data tytp tO, 2 ranch 10 IP) PePsPa|PaP2P1 Po PaP2P1 Po | aha address pecified with the immediate Act=O dete PPaPsPaP ghz? Po within the same page occurs, BMI addr Branch on M bit O1VF TIO tito PC) ~0— P7PePyPa {it # single bit of the MIDP) specified with the immadiate det tytg 1, a branch to Ps PePsPalPa P2 PI Po P3P2P1Po ie eaarece specie’ nn the enoediate A (MEDP.U LIE | date P7PQPgPgPaP2? Po within the same page occu. Branch on no Mbt [0014/0 11ito PCr 0 PrPaPaPa [Tete ledate trip O-ebrerch to . P1P5 Ps Pal P P2 Ps Po) P3P2P+Po | the address specified with the immediate M(MEDP.1 119! )=20 | data PpPgPePgP Po? Pq within the mame age occur. = Ta dings DH OF pon PIOP{) wpecited BPI adar | Branch on Pot bn = OF 11/13 Otto PCr Po PePS Pe | a hs fate dee tiga Py Ps Ps Pal P2P2P1 Po PaP2P1Po | branch to the sderem spailiga withthe 1 [PIDPL tit o1J=1 | immediate data PyPeraP Pgh? Po, ‘within the same page occuri. Banc on no Fon br ]OO FT [1 Oivto|? [2] Peron PrPerane | mal eh af pq MDPGT saciid P) Pe Ps Pal Pa Pz Pr Po P3P2P1PO | branch to the addres specilicd with the N(PLOPL. tit ob =O | immediate dita P2P—PeP aP3P2P Po within the sume pegs occurs, STi vss] rem ov vme JOT 1 a [1 1 0 0 a [z|rcr-omPrPerars aie mets nit Bann ee Tar IP? PePsPa|P2P2PiPo P3P2P1 PO |data PoPePePgPaPoP 1Pq within the same ‘2°66 4° 3°21" 0! wTMe=1 page obcare tha TRAE ieee. then TMF <0 a ToOTeeeeaOQn0nanommmTmTme eee No, 4364-48/49
LC6543N/F/L, LC6546N/F/L Deeription :
101 Ds Ds 0x {020201 Op
Branch on toume 1001111100 PCr~o% PrPePsPa |M MF 0,8 Branch 0 th Me : Pp PePsPa PsP2Pi Po PaPapsPo leaPyrcberararstifo nthe ne co 1 IMF=O page occurs. The TMF le reset, then TME=0 Branch on intenuor fOd 11 PCrco=PPePaha ft the EX 3 bane ified with the . Py PePsPa PaP2P1Po [famedite ‘dete PsPghcPatats? 1 WEXTE ST ‘witha the same pope becure “The EXTE then EXTF =O _|Isramt. BNI addr | Branch on no imienup[OO 11/1104 PC7-o-— PrPePePs |i the EXIF li Os branch to P7PoPsPa [Pa P2Ps Pi STE ele iter sa 2P2Pi Po 3P2P1PO | immediate date PrPghePaPaPoP Pi 1 ExTF=O within the same pope oceur. The EXT then EXTF =O _| ferent. : ortafaryys PCr~o--PrPaPsPa | the, CF Ved Cpe te a oo PaP2P1 Po PaP2P1Po Wmedinis "date PoPaPePyPaP ohio ucr=1 within the same poe eeu. BNC addr | Branch on no CF Ce PCr~o- PrPePsrs jt Ors branch 0 sovctted. withthe P1 PePsPalPsP2P1 Po PP2PiPO | mnie ace Pye era aP2 Po
41 CF 50 ‘within the same page Sanur
Otit|tit0} PerconPrPePeha | the UF 1 a bandh wo , 4 2F=4 within the seme poge secora. Branch on no ZF oortlsrt0 PCr~o--P7P6PsPa |i the ZF G2 branch to Msres_ specifies IP? Pes Pa |P9P2 Pi Po PSP2PiPo |immesiate vdate PyPePePaPaPaP Po HW 2F eo when the some page oor. Branch on tag bt [1 1 01 [mangayno| PC? =0—P? Po PE Pa |i the flag DR of the 16 fags spaced with the romadiote dats can P> Paps PalPaP2PiPo PaP2PiPo Sornc on sre hb 4 Fost mediate deta PPP ePaPaP 2? iP thin tha same page ovosre : Branch on no theg 1001 |ngngniyng PCr ~0%P2PePsPa |! the ote cltfed withthe ineediate drt 0, bt 2 PePsPa|P3P2P1 Po P3P2P1Po ‘Toranch to thw aderae mscficd ith the
4 Fre Ieamedite data PoP aPePaPaP2P Po
within th same page Occurs - Ppp ia enw at foo oo [pT OO) f [xem trpra) on MOR, contensaretoxsnmwne] zr |] [or Jona Ac 16 ea Jo 1 0 [00.0.1 [1] [roping [iwAb oni anenirononorrh | | ofo PDP, yA aate Be in port FLOP, spaced
01 BiBe PI DPL Br Bo) 0 [Asingle BR in port PIDP;) wecifed with
the immediate date B89 & reset. Set contro egies [0010/1 100 CTL YCTLIV The bits of the control register specHed : a bats) 10.0 0 [83626180 re 83.8281 Bo | Nor” Boe lmmadiats dats 8828 8p ore ; Reset control regsie [0010/1 100 CTL M(CTLIA Tie bike of the control rapier ached : ree buts) 1001 lese2e:B0 FF | BSBr Bree | ih th mediate data 3828480 oe { Tha and AC conteras are loaded Inthe , ; nA io operrtion ti peformed, but T machine TTT the CLA Tortruction & wsed continwoutly In sich a manne os GLA, CLA, ————, the fire CLA lnnruction only i effective ard the folowing CLA instructions are chenged tothe NOP instructions. Thi ta true of the LI Instruction, No. 4364-49/49