LC6527N

LC6527N SANYO | Alldatasheet

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1) CMOS technology for a low-power operation (with instruction-controlled standby function) 2) ROM/RAM LC6527N/E/L ROM : 1K x 8bits, RAM: 64 x 4bits LC6528N/F/L ROM : 0.5K x 8bits, RAM: 32 x 4bits 3) Instruction set : 51 kinds selectable from 80 instructions common to the LC6500 series 4) Wide operationg voltage range form 2.2V to 6.0V (L version) 5) Instruction cycle time of 0.92us (F version) Continued on next page. SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg.,1-10,1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 12595JN/ NO893JN B8-0330, 0327, 0328 No. 4363-1/42

LC6527N/F/L, LC6528N/F/L Continued from preceding page. 6) Flexible 1/O port - * Number of ports : 4 ports/13 pins max. © All ports :Input/output common Input/output voltage 15V max. (open drain type) Output current 20mA max. (sink current) (LED direct drivable) * Option selectable for your intended system A. Open drain output, pull-up resistor : Single-bit select for all ports B. Output level at the reset mode : 4-bit select of H/L level for port C/D 7) Stack level : 4 levels 8) Timer : 4-bit prescaler + 8-bit programmable timer 9) Clock oscillation option selectable for your intended system * Oscillator option : 2-pin RC oscillaion (N, L version) 2-pin ceramic resonator oscillation, 1-pin external clock input (N,F,L version) * Predivider option : No predivider, 1/3 predivider, 1/4 predivider (N, L version) Function Table [tem cesemyasn Tcesaveyaer_ | kcasotaee ——. 2. ae £ 512 x 8 bits (28N) 512 x 8 bits (28F) 512 x 8 bits (28L) 3 64 x 4 bits (27N) 64 x 4 bits (27F) 64 x 4 bits (27L) JON | aiiam | Sttacem | Smee 2 5t a a as Sg[ Stacklevel [ag

68 Standby available Standby available

by HALT instruction by HALT instruction by HALT instruction z g z r 8 i 6.0us (VDD23V) 22 |_ Supply voltage | Btoev aS topv TO 22toev 5 Resonator RC (850kHz,400kHz typ.) RC (400kHz typ.) 5 ceramic (400k,800k,1MHz, ceramic 4MHz ceramic (400k, 800k, IMHz, 8 4MHz) 4MHz) bie Package | ie merie | _ Diba, ME ria, ee (Note) Information on the resonator and oscillation circuit constants will be presented as soon as the recommended circuit is determined. * MFP18 : under development No. 4363-2/42

LC6527N/F/L, LG6528N/F/L Pin Assignment Package Dimensions LC6527N/F/L 3007A LC6528N/F/L (unit : mm) Cd 10 nooo onoon i es ee osc: [7] osc2/PHo p is as en es a en Test [2 | POs %.2 . ee | vss [is] Poe Reson fat FES (4 | [15] Pot fay M VW Pao[s | [14] Po Os 12 256 Pare | Pcs Pa2(7| Poz Pas[a| Per SANYO : DIP18 voo{a| 10] PCO Ce to DIP * MFP ommon 3095-MI8IC (unit : mm) 0.15 1 to ~Do not immerse the package in the solder fLHAAAA AAA t dip tank when mounting the MFP on the substrate, : ° 3 Re: b- on FHEHREEEY i | » 6 s CE ————

5 Emon

SANYO : MFP18 (Note) The package is the reference figure without the description of the rank, Please inquire us for the formal package. No, 4363-3/42

LO6527N/F/L;-LC6528N/F/L Pin Name O8C1, OSC2 : C,Rorceramic resonator forOSC_ PHO : Input/output common port HO RES : Reset TEST : Test PA 0-3 : Input/output common port A 0-3 PC0-3 : Input/output common port C0-3 PD0-3 : Input/output common port D 0-3, System Block Diagram LC6S27N/F/L, LC6528N/F/L PAO-3 = PCO-3.——- PDO-3. PHO OSC2 sci if ft if 1} Note 1° [Note 1 <— TEST : = Port Port ‘oO! RES iti if ifi ifi <—» vop f Cons <—° vss (Note 2) STACK 1 (Note 2) STACK 2 STACK 3. VO Buffer (i STACK 4 LDEC re | te Note 1. The PHO pin or OSC2 pin is selected by the mask option. Note 2. LC6527N/F/L ROM: 1024 bytes RAM :64 words LC6528N/F/L ROM: 5i2bytes RAM:32 words No. 4363-4/42

LG6527N/FIL, LC6528N/F/L Development Support Tools ~ —_— The following are available to support the program development for the LC6527, LC6528. (1) User's Manual "LC6527, LC6528 User's Manual” No. 24-6016 ('86.10.1.) Note : Do not use "LC6523 Series User's Manual” No. 16A-7015 and No. 16-9064. (2) Development Tool Manual For the EVA-800 or the EVA-850 system, refer to "EVA-800. LC6527, LC6528 Development Tool Manual”. (3) Development Tools A. For program evaluation 1. Piggy back (LC65PG23/26) 2. 23127 ; The pin-to-pin conversion socket for the piggy back LC65PG23/26, B. For program evaluation

29 TO 27 ; The pin-to-pin conversion socket for EPROM built-in microcomputer (LC65E29)

Note. For notes for program evaluation, do not fail to refer to ‘4-3. Notes when evaluating programs’ in "LC6527, LC6528 User's Manual". to EVA-410 o EVA420 EPROM (2732 , 2764) Ov Pal La | EPAOM | FAP-40-0362 wr [ be )D | Lcss96 >) : FAP-20.0982 4a) CN} cue o AS20080 amy Piggy back é Cr) LossPazses i } “ S ca 2.54rmm pitch or eV Sen CL ba. tal cabie SS L 1pin Lp assmmpich THe Dig FGP-20-0142 removed the 10 pin and 11 pin can be used for the DIPIB. oS Co Fig. 1 Evaluation kit terget board lead (EVA-TB6523C/26C/27C/28C) a Fig. 2 Program evaluation No. 4363-5/42

LE 6527N/F/L, LC6528N/F/L C. For program development (EVA-800 or EVA-850 system) —— 1. MS-DOS for host system (Note 1) 3. Host contro! program 4, Evaluation chip : LC6596 5. Emulator : EVA-800 or EVA-850 emulator and evaluation boards EVA800-TB6527/28 D. For program development (EVA-86000 system) under development Appearance of Development Support System + Host processor contro! program “LC6SS.EXE cross assembler a SE ALY Sa) a a MS-Dos jo va personal computor A E> y Sy KS a [=] ~ EVA-800 or EVA-850 ‘emulator (not0 2) —, Nt, Gna ——— 7 Evaluation chip board yon EVA800-TBES27/28 y =, ——— An FS.20 ee soe —S "/ User's application board iz Remove the 10 and 11 pln, and use tor DIP18 (Note 1) MS-DOS : Tradmark of Microsoft Corporation Note 2) The EVA-800, EVA-850 are general term for emulator. A suffix (A, B,...) is added at the end of EVA-800 and EVA-850 as they are improved to be a newer version. Do not use the EVA-800 and EVA-850 with no suffix added. No. 4363-6/42

LC6527N/FIL, LC6528N/F/L Pin Description ~ — [PinName [Pins] W/O [Function [Option Reset Mode _ | | | osc1 1 © Pin for externally connecting RC,| 1) 1-pin external clock input} ceramic resonator for system —_|2) 2-pin RC OSC clock generation. 3) 2-pin ceramic resonator « For 1-pin external clock input, OSC the PHO/OSC2 pin is used as _| 4) Predivider option 1/0 port PHO. 1. No predivider * For 2-pin RC OSC, 2-pin ceramic] 2. 1/3 predivider resonator OSC, the PHO/OSC2 3. 1/4 predivider pin is used as OSC pin OSC2. PAOtoPA3 Input/ | + 1/O port A0to3 1) Open drain type output _|+"H"output (Out-| output | bit input (IP instruction) 2) With pull-up resistor put Neh transis. 4-bit output (OP instruction) 1), 2) : Specified bit by bit tor : OFF) Single-bit decision (BP, BNP instruction) Single-bit set /reset (SPB, RPB instruction) * Standby is controlled by PA3. * The PA3 pin must be free from chattering during the HALT instruction execution cycle. PCO to PC3 Input/ | °1/O port COto3 1) Open drain type output | "H” output output | Sameas for PAO to 3 (Note) *"L” output * Option permits output at the 2) With pull-up resistor (Option - reset mode to be "H" or "L". 3) Output at reset mode:"H" selectable) (Note) No standby control 4) Output at reset mode:"L" function is provided. * 1), 2): Specified bit by bit + 3), 4): Specified ina group of 4 bits PDOtoPD3 Input/ | *1/O port D0 to3 Same as for PCO to 3 Same as for PCO output Same as for PCO to 3 to3 PHO / OSCc2 Input/ © 1/O port HO Same as for PAO to3 Same as for PAO output Same as for PAO to 3 (Note) to3 * Single-bit configuration * For 2-pin OSC, this pin is used - as the OSC2 pin, providing no function as I/O port. (Note) No standby contro) function is provided. /RES- 1 | Input | © Systen reset input « For power-up reset, C is con- nected externally. « For reset restart, "L" level is applied for 4 clock cycles or more. TEST 1 Input | * LSI test pin Normally connected to VSS No, 4363-7/42

LCO6527N/F/L, LC6528N/F/L Oscillator circuit option 1. External clock osc The PH 0 / OSC2 pin is used as port ne ee eT : : Dime? pin O5C2, providing no function as PH /OSC2 port. wr Rext 3. Ceramic fi osc! The PH 0 / OSC2 pin is used as OSC resonator OSC fom pin OSC2, providing no function as ceramic TD psc resonator port. oe if Predivider Option 1. No predivider * Applicable to all of 3 OSC options. (1/1) * The OSC frequency, external clock do not O tose ef exceed 1444kHz. (LC6527N, 6528N) EB] | © The OSC frequency, external clock do not ° exceed 4330kHz. (LC6527E, 6528F) + The OSC frequency, external clock do not exceed 1040kHz. (LC6527L, 6528L) 2.1/3 predivider * Applicatable to only 2 OSC options of 0 BE] | external clock, ceramic resonator OSC. oO a =) | « The OSC frequency, external clock do not exceed 4330kHz. 3.1/4 predivider * Applicatable to only 2 OSC options of C18! se 3} ge 2] | external clock, ceramic resonator OSC. Oo a E81 | . The OSC frequency, external clock do not exceed 4330kHz. Note : The OSC option and predivider option are summarized below. Full care must be exercised. No. 4363-8/42

LC6527N/F/L, LC6528N/F/L Table of OSC, predivider-Option of LC6527N/28N, 27F/28F and 27L/28L LC6527N, L6528N Circuit Configuration Frequency Predivider Option [VDD Range Remarks [ Setcntenn | eer [Pours || | Ceramic resonator OSC 400kHz 1/10 ps) 3to6V Unusable with 1/3, 1/4 800kHz 1/1 G ps) 4to6V 1/3 (15 pts) 4to6V 1/4 (20 ps) 4to6V 1MHz 1/1 4 ps) 4to6V 1/3 (12 ps) 4to6V 1/4 (16 ps) 4to6V 4MHz 1/3 GB ps) 4to6V | Unusable with 1/1 predivider | vag | toe [ENE Pe 1-pin external clock 200k to 667kHz 1/1 (20 to 6s) 3 to 6V 600k to 2000kHz 1/3 (20 to 6s) 3to6V 800k to 2667kHz 1/4 (20 to 6us) 3to6V 200k to 1444kHz 1/1 20 to 2.77us)| 4to 6V 600k to 4330kHz 1/3 (20 to 2.771s)| 4to6V 800k to 4330kHz 1/4 (20 to 3.70us)| 4 to 6V RC OSC circuit 2-pin RC Used with 1/1predivider,recommended constants. If used with other than 4to 6V recommended constants, the frequency, predivider option, VDD range must be the same as for 1-pin external clock. External clock input to the} The ceramic oscillation circuit cannot be driven by external clock. ceramic oscillation circuit | To drive the circuit with external clock, select the external clock option or the 2-pin RC option. LC6527F, L6528F (Cycle Time) | CeramicresonatorOsc | 4MBz | w/t) aStosv | | t-pinexternalclock | 200kto 4330KHz | 1/1 @0t009%| a5t06v [ External clock input to the | The ceramic oscillation circuit cannot be driven by external clock. ceramic oscillation circuit To drive the circuit with external clock, select the external clock option. No, 4363-9/42

LC6527N/FIL, LC6528N/F/L LC6527L, L6528L : Circuit Configuration Frequency Predivider Option [ Sensotersin | Freee |Peerec Ceramic resonator OSC 400kHz 1/1 (10 ps) 2.2t06V | Unusable with 1/3, 1/4 800kHz 1/1 G ps) 2.2 to 6V va ese] 1/4 20 ps) 2.2 to 6V 1MHz 1/1 4s) 2.2 to 6V 1/4 (16 ps) 22 to 6V 1-pin external clock 200k to 1040kHz 1/1 (20 to 3.84p1s)| 2.2 to 6V 600k to 3120kHz 1/3 (20 to 3.84p1s)| 2.2 to 6V 800k to 4160kHz 1/4 (20 to 3.84j1s)|_ 2.2 to 6V SS RC OSC circuit 2-pin RC Used with 1/1predivider,recommended constants. If used with other than recommended constants, the frequency, predivider option, VDD Tange must be the same as for 1-pin external clock. External clock input to the j The ceramic oscillation circuit cannot be driven by external clock. ceramic oscillation circuit | To drive the circuit with external clock, select the external clock option or the 2-pin RC option. Option of ports C, D Output Level at the Reset Mode For input/output common ports C, D either of the following two output levels may be selected in a group of 4 bits . during reset by option. Option of Port Output Configuration For each input/output common port, either of the following two output configurations may be selected by option. 1. Open drain output * Unapplicable to port PHO/OSC2 when 2-pin RC OSC or ceramic HKH———_ resonator OSC is selected. 2. Output with pull-up| 1 [>° resistor ~« 5 => 4 No, 4363-10/42

LO6527N/F/L, LC6528 N/F/L 1. Absolute Maximum Ratings at Ta=25°C, VSS=0V [ Parameter | Symbol | Conditions [Ps | Limits ‘| _unt_| Maximum VDD max VDD 0.30 +7.0 Vv Pose a Output voltage | VO) OSC2 Allowable up to Vv [ove fe ee || Tnpatvolage [Vi SCS OB [ 03 0 vODWOS [VI a se ee Aa input/output [viod |__| Poof Diype| 03045 | V4 Peeps Poe [Frat | aso {| [ome [| a current 100 ms PDOto3,PHO (2) PDO to3 Allowable Pd max(1) | Ta=-40 to +85°C a he mW power (DIP package) Operating Topr 40 to +85 °C Storage Tstg “55 to +125 °C [mmo | [| * w=» Under development. Do not immerse the package in the solder dip tank when mounting the MEP on the substrate. 2. Allowable Operating Conditions at Ta=-40 to +85°C, VSS=0V, VDD=3.0 to 6.0V Symbol [_min. [typ] max. [unit _| Operating VDD VDD 3.0 Vv VST RAM, register hold 18 } |? | Vv "H"Jevel input | VIH() | Output Nch Tr. OFF] | | Port of OD type pr me] | ee Perce ee | Le (except HO) | Win@) [OutputNchTr. OFF, | HOofODtype fosvop] | +35 | Vv | | vi [OutputNchTr. OFF] [HO of PUtype [osvpp| | vpp | v_ | [vie [RES fosvpp] | vop |v | | VIH(6) |Extemalciockmodel [sci osvpp| | vop | v | voltage IVDD=4 to 6 me orn oe | | PY VDD=3 to 6 VIL@) | External clock mode| Oscl =| pe v IWDD=4 to 6 No, 4363-11/42

LC6527N/F/L, LC6528N/F/L Parameler _] Symbot a ee er rene voltage mode [ving | vb=ato6| Test | vss[ [oavpp| v_ | [vin [| vb=3t06| Test | vss|[o25vpp]_v__ | [vi [| vb=tto6| RES vss | fo2svpp[ vv | [vi) | vpp=3t06] RES | vss| J ozvpb| vv | Operating fre- | fop When the 1/3 |VDD=4to 6 200 1444 | kHz quency (cyc) or 1/4 predivider| (20) (2.77) | (us) (cycle time) option is selected, 200 667 kHz clock must not (20) (6.0) } (us) exceed 4,33MHz. External clock conditions Fig.1. Frequency _| text When clock DD=4t06| OSCi 200 4330 | kHz exceeds 1.444 3t06 200 2667 | kHz Pulse width | textH, textL] MHz, the 1/3 [VDD=4 to 6 po | 69 or 1/4 pre- 3to6 180 Rise/Fall time | textR, textF | divider option [VDD=4to 6] OSCI | | [3 Oscillation guar- - anty constants 2-pin RC Cext Fig.2 VDD=3 to 6| OSC1, OSC2 22045% pF oscillation Cext Fig.2 VDD=4 to 6|_OSC1, OSC2 22045% pF. fies [nga (Woovtwd xcxones| aoa) | a Fig2 VDD=4 to 6|_OSC1, OSC2 4.741% kQ 3. Electrical Characteristics at Ta=-40 to +85°C, VSS=0V, VDD=3.0V to 6.0V Parameter Symbol Conditions Pins ee "A-level input | MH) Output Neh Tr. OFF Port of OD type +50 | HA current (including OFF leak current of Nch Tr.) VIN=+13.5V THH(2) External clock mode, OSCI 410 | pA Oa re a “Level input | TIL) Output Neh Tr. OFF [Penerop wee) 30 | | pA phe ansas OP [Peenor | Tes TT | VIN=Vss ee vinevss Ra TIL() External clock mode, SCI “10 HA A Kee ne “H’-level output] VOH@) | IOH=-50nA Port of PU type |VDD-1.2 Vv No, 4363-12/42

LCO6527N/FIL, LC6528 N/F/L Parameter Symbol Conditions Pins | min. [ typ. [max] unit_| “Level output{ VOL) [IOL=10mAVDD=40t060V [Pot ||| TV ove Pe pacers 1mA or less Hysteresis VHIS RES, OSC] of 0.1VDD Vv voltage schmitt type(*4) Current Output Neh Tr. OFF at dissipation operating, Port=VDD 2-pin RC oscillation | IDDOP() | Fig.2fosc=850kHz (TYP) | VDD 10 mA VDD=4 to 6V [IDDOPQ) | Fig.2fosc=400KHz TYP) [| vpbb | | 08 | 25 | ma | resonator VDD=4 to 6V VDD=4 to 6V [ippore) [Fig3400KHz st vpp | 0 2 ma | [iDDoPe) | Fig.3 800KHz VDD=4to6v |vpp | | to | 26 | ma | External clock | IDDOP(7) | 200kHz to 667kHz, VDD 1.0 mA 1/1 predivider ; 600kHz to 2000kHz, 1/3 predivider 800kHz to 2667kHz, 1/4 predivider TDDOP@) | 200kHz to 1444kHz, VDD 12 3 | mA 1/1 predivider 600kHz to 4330kHz, 1/3 predivider 800kHz to 4330kHz, 1/4 predivider, VDD=4 to 6V Standby Output Neh Tr.OFF VDD=6V| VDD 005 | 10 | pA Oscillation | characteristics | Ceramic OSC | Frequency | {CFOSC_| Fig.3 fo=400kHz osc1,osc2 | 384 | 400 | 416 | kHz 3) —_| Fig3 fo-800kHz, VDD=4 to 6V| OSc1,0sc2 | 768 | 800 | 832 | kHz Fig3 fo=IMHz VDD=4to 6V| O8c1,osc2} 960 | 1000 | 1040 | kHz Fig.3 fo=4MHz,1/3 predivider| OSC1,08C2 } 3840 | 4000 | 4160 | kHz 1/4 predivider_VDD=4 to 6V Stable time | «CFS Fig-4 fo=400kKHz 10 Fig-4 fo=800kHz,1 MHz,4MHz, | 10 1/3 predivider, 1/4 predividey | VDD=4 to 6V| | on _ Reiman | meee ey oscillation Fig.2 Rext=4.7K041% Frequency VDD=4 to 6V| Fig.2 Cext-220pFi5% sci, osc2 | 30a | 400 kHz Fig.2 Rext=12k041% VDD=3 to 6 No. 4363-13/42

LO6527N/FIL, LC6528N/F/L | min. | typ. | max. | unit _| Pull-up resistance 1/O port pull-up} RPP VDD=5V_ | Port of PU 4 kQ resistance type External reset characteristics Reset time tRST See Fig.5. Pin capacitance |Cp f=1MHz Other than pins | | menses [Pewee | LL | Le | (*1) When oscillated internally under the oscillating conditions in Fig.3, up to the oscillation amplitude generated is allowable. (12) Average over the period of 100ms. (*3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the 2-pin RC oscillation option or external clock oscillation option has been selected. (*5) fCFOSC: oscillation frequency. There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic resonator. . No, 4363-14/42

LC6527N/F/L, LC6528 N/F/L osc (osc2) OPEN External clock wee eee eee eee eee cee eee eee eee eee eee ee eeeeeeeeeeeees VDD en (en Seen eennnnnnnnnnee E7010) weceeeeeeeeefeeeN cece eeceeee Pec feeeee---e---|--- Neon. O-2VDD(VDD=3-4V) 0,25VDD(VDD=4-6V) texiF oxtFlc ext text Fig. 1 External Clock Input Waveform * External clock can be used at selecting 2-pin RC option or 1-pin external clock option, and cannot be used at ceramic resonator oscillation. osc osce osci osc2 Cext Rext i Coraric C1 resonalor c2 Fig. 2 2-pin RC Oscillation Circuit Fig. 3 Ceramic Resonator Oscillation Circuit voD crorreteesdeeee cnc eececeeeessceoseees Lower limit of operating VDD Osc

7 Stabilized OSC

Fig. 4 Oscillation Stabilizing Period . No. 4363-15/42

LO6527N/F/L, LC6528N/F/L —- Table 1 Constants Guaranteed for Ceramic Resonator OSC 4MHz (Murata) CST4.00MGW gbuilt-inc) | R | 02 | 4MEz (Kyocera) KBRAOMSA KBR4.0MKSQbuilt-in©) [ R | 02 | CSB1000] [Rk [222 | CRES (=0.1 F) MHz (Kyocera) z [rR [oo | 800kHz (Murata) Fig. 5 Reset Circuit CSB800} [ R_| _2.2kQ | _—_ (Note) When the rise time of the power supply is 0, 800kHz (Kyocera) the reset time becomes 10ms to 100ms at KBR800F CRES=0.1pF. If the rise time of the power supply [eR] oO | is long, the value of CRES must be increased 400kHz (Murata) so that the reset time becomes 10ms or more. cso? Rp 2a] OOK (Kyocera) KEBRAOOBK [ rR | oo | No, 4363-16/42

LC6527N/FI/L, LC6528 N/F/L RC Oscillation Characteristics of the LC6527N, LC6528N Fig. 6 shows the RC oscillation characteristics of the LC6527N, 6528N. For the variation range of RC OSC frequency of the LC6527N, LC6528N, the following are guaranteed at the external constants only shown below. 1) VDD=3.0V to 6,.0V, Ta=-40°C to +85°C. External constants Cext = 220 pF Rext = 12 kQ 304 kHz < fMOSC < 580 kHz 2) VDD=4.,0V to 6.0V, Ta=-40°C to +85°C Cext = 220 pF Rext = 4.7 kQ 646kHz < FMOSC < 1117kHz If any other constants than specified above are used, the range of Rext=3kQ to 20kN, Cext=150pF to 390pF must be observed. (See Fig.6.) (*6) : The oscillation frequency at VDD=5.0V, Ta=+25°C must be in the range of 350kHz to 750kHz. (*7) : The oscillation frequency at VDD=4.0 to 6.0V, Ta=-40°C to +85°C and VDD=3.0V to 6.0V, Ta=-40°C to 85°C must be within the operation clock frequency range. fmosc-Rext N ‘These characteristic curves are a a I gurantes. = § CoN ES NLS, zs {COTES oy ae ee a | = s>/ TiS [ [ {yf g ,ETTIN NET TT , HESSEN EXRRNN 99 2 345 10 2 3°45 100 Rext (ka] Fig.6 RC Oscillation Frequency Data (Typ.) No, 4363-17/42

LC6527N/F/L, LC6528N/F/L 1. Absolute Maximum Ratings at Ta=25°C, VSS=0V. [Parameter | Symbol | _Condions [Pin [Limits [ont _] Output voltage | VO Osc2 Allowable up to v aa voltage generated Tapavolage [| OC Bo VOWS [Vv _| [Pree Cig oes Tnpat/ouipat [Via | ———*ds~Poreof OD ype] OSHS | Vid ge Enea [rent ee ase toes [J Peak output IOP I/O Port -2to +20 mA fee [| eee | current pm | 100ms (2) PDO to 3, PHO (2) PDO to3 power (DIP package) : (MEP package)* Operating Topg ~40 to +85 ol cae a De Storage Tstg -55 to +125 °c [apne | ee * + Under development. Do not immerse the package in the solder dip tank when mounting the MFP on the substrate, 2. Allowable Operating Conditions at Ta=-40 to +85°C, VSS=0V, VDD=4.5 to 6.0V Parameter Symbol Conditions Pin eee [me ee ee Operating VDD VDD 45 Vv supply voltage} ere pe Pe te | “H"-level input | VIH() Output Neh Tr. OFF Port of OD type ono jms |v | voltage (except HO) . me [coer ecm LY (except HO) | viHG) | Output Neh Ts. OFF | HOof ODtype [osvpp| | +135 | Vv [ via) | Output Neh Tr. OFF | HO ofPUtype [osvpp| | vop |v __| [vingy [RES osvpl | vop Tv | [viH@ | Exemalciockmode _[osci_—osvpn] [von | v | No, 4363-18/42

LC6527N/F/L, LC6528N/F/L Parameter Symbol Conditions Pin a el ee "L'levelinput [VILG) [ OutputNchTr.OFF | Pot vss_{[ osvpp{ v_| voltage --[VIL@) | Externalclockmode | osci__—— | vss_ | fo2svpp| v__ | , [vie [tes vss [| osvpp |v | [vie | SSS ~via | osvoo] —v | Operating foP 200 4330 kHz frequency Mcyc) (20) (0.92) (us) (Cycle time) External clock conditions Frequency text osci 200 kHz Pulse width textH, text] > Fig. 1 oscl 69 ns Rise/fall time | textR, textF) OSC1 ns Oscillation guar-| anteed constants ceramic Fig.2 See Table 1. resonator OSC 3. Electrical Characteristics at Ta=-40°C to +85°C, VSS=0V, VDD=4.5 to 6.0V Parameter Symbol Conditions Pin [caine [max [ani _| “H"-level input | HA) Output Nch Tr. OFF Port of OD type 45.0 BA current (including OFF leak current of Nch Tr.) VIN=+13.5V eed ieewo LT VIN=VDD. current VIN=VSS Pee inca om [Peeorey ETT VIN=VSS [ug | vinevss RS asf to [OT na | ee ee VIN=VSS "Lleveloutput| VOLO) [ ioL=10maA [Pork Ts TV | port : ImA or less Hysteresis VHIS RES, 0.1VDD| Vv voltage OSC1 of schmitt type (*4) No, 4363-19/42

LC6527N/F/L, LC6528N/F/L Parameter Symbol Conditions Pin ° ee el eee Current . dissipation Ceramic IDDOP(1)} Fig.2. 4MHz VDD 15 mA resonator OSC 41 External clock | IDDOP(2)| 200kHz to 4330kHz VDD 15 mA *1 Output Nch Tr. OFF at Operating mode Port=VDD Standby mode Output Neh VDD=6V | VDD 0.05 10 pA Tr. OFF Port=-VDD VDD=3V_|VDD 0.025 5 pA Oscillation characteristics Ceramic resonator OSC Frequency fCFOSC Fig.2 fo=4MHz (*5) OSC1, OSC2 3840 4000 4160 kHz Stabletime [rcrs | Fig3forame | TT 0 ms Pull-up resistance 1/O port pull- | RPP VDD=5V |Port of PU 4 kQ up resistance type External reset Reset time «RST See Fig. 4, Pin capacitance | Cp f=1MHz, other than pins pF (1) When oscillated internally under the oscillating conditions in Fig.2, up to the oscillation amplitude generated is allowable. (*2) Average over the period of 100ms. (3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the external clock oscillation option has been selected. (*5) £CFOSC : Oscillatable frequency. No. 4363-20/42

ceeeee cence en} ee Ne ee eee ee eee ene fee eee eee eee dene elon ee eee ees O.25VDD. Table 1. Constants Guaranteed for

LC6527N/F/L, LC6528N/F/L [Parameter — | Symbol | Conditions Pin [tims [it] Maximum VDD max VDD Vv ee adil | ad AA eee voltage generated “Inparecige PMEE epee fe [viz [Tes RES | 03t0vpp+03 | Vv | Tnpa/oupat [vio [ | Por of oD ype] oats |v Seg Enea enauies[oste wooo [VJ foe | | mee current current 100ms (12) ZIOA(2) Total current of PCO to 3, PCOto3 PHO -14 to +90 mA PDO to 3, PHO PDO to 3 (12) Allowable Pd max(1) | Ta=-40 to +85°C mW power (DIP package) dissipation Pd max(2) | Ta=-40 to +85°C mW ee | Meoroae | | ae a temperature Storage Tstg “55 to +125 °C fienpenwe |" | | CO * + Under development. Do not immerse the package in the solder dip tank when mounting the MFP on the substrate. 2. Allowable Operating Conditions at Ta=-40°C to 85°C, VSS=0V, VDD=2.2 to 6.0V | min. [typ.[ max. | unit | Operating VDD VDD 22 Vv supply voltage fpr ring| |e fee | el supply voltage “H"-level input | VIH() Output Nch Tr. OFF Port of OD type | 0.7VDD 413.5 v | ViHG) | Output Neh Tr. OFF | H00fODtype fosvop| | +135 | v | | via) | OutputNch Tr. OFF [H0ofPUtype [osvpp{ | von | v | [vino | eS fosvp] | vo | Vv | | vir) | Externalclock osc. fosvpp{ | vpp | v__ | “Litevel input | ViLG) | OutputNchTs.OrF [Por | vss_ | o2vpp{ v | voltage [| ViL@) | Externalclock sca. vss | foasvop] v | [vie [esr | vss | fo2vpp] v__| [vig [res vss TO fo2vppt vy | No. 4363-22/42

LO6527N/F/L, LC6S28N/F/L Parameter Symbol Conditions eee ed ee Operating fo? When the 1/3 or 1/4 200 1040 | KHz frequency (cyc) predivider option is selected, (20) (3.84) (us) (cycle time) clock must not exceed 4.16MHz. External Clock conditions Frequency _| text Fig.1 When clock exceeds | OSC1 200 4160 kHz Pulse width | textH, textL| 1.040MHz, the 1/3 or 1/4 oscl 100 ns Rise/fall time | textR, textF |J predivider option is selected.| OSC1 100 ns Oscillation guaranteed constants 2-pin RC Cext Fig.2 OSC1, OSC2 220+5% pF ostilaion [Ret [| —SSSSSCSC~dSSSC~idSCO oscillation. 3. Electrical Characteristics at Ta=-40°C to +85°C, VSS=0V, VDD=2.2 to 6.0V Parameter Symbol Conditions Pin _ in Top ee Ta] “Hevel input | WAG) | Output Neh Tr. OFF Port of OD type 45.0 | pA current (including OFF leak current of Nch Tr.) VIN=+13.5V VIN=VDD current VIN=VSS ea a a VIN=VSS [im@ —[vinevss RES | 5 | to | va a a i VIN=VSS i laa a voltage "level output| VOL |10i=3ma Pork TT TV al hic 1mA or less Hysteresis VHIS /RES, OSC1 of 0.1VDD} Vv voltage Schmitt type (*4) No, 4363-23/42

LC6527N/F/L, LC6528N/F/L . Parameter Symbol Conditions Pin Current Output Neh Tr. OFF at a 2-pin RC OSC | IDDOP() | Fig.2 f0SC=400kHz (TYP)_| VDD mA Ceramic OSC [ IDDOPQ) | Fig3 4MHz, 1/4predivider| VDD || a2 | as | ma | cl aaa hal VDD=2.2V [appora | Figs soz — [vpp | os | | ma | [appore) | Fig3 sok [vop | 0 | 25 | ma External clock | IDDOP(6) | 200kHz to 667kHz, VDD mA 1/1 predivider 600kHz to 2000kHz, 1/3 predivider 800kHz to 2667kHz, 1/4 predivider Standby mode Output Nch Tr. OFF ee | Port=VDD VDD=2.2V | VDD 0.025 | 5 HA Oscillation characteristics - Ceramic OSC Frequency fCFOSC Fig.3 fo=400kHz OSC1, OSC2 384 400 416 kHz (*5) Fig.3 fo=800kHz OSC1, OSC2 768 800 | 832 kHz Fig.3 fo=1MHz OSC1, OSC2 960 1000 | 1040 kHz Fig.3 fo=4MHz, OSC1, OSC2 3840 4000 | 4160 kHz 1/4 predivider Stable time tCFS Fig.4 fo=400kHz 10 ee 4MHz, 1/4 predivider 2-pin RC OSC Frequency fMOSC Fig.2 Cext=220pFt5% OSC1, OSC2 281 400 kHz Fig.2_ Rext=12k0Q+1% Pull-up resistance I/O port pull- | RPP VDD=5SV | Port of PU type 14 kQ up resistance External reset characteristics Reset time tRST See Fig. 5. aaa to be tested, VIN=VSS (*1) When oscillated internally under the oscillating conditions in Fig.3, up to the oscillation amplitude generated is allowable. (*2) Average over the period of 100ms. (*3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the 2-pin RC oscillation option, or external clock oscillation option has been selected. (*5) fCFOSC ; Oscillatable frequency. There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic resonator. No, 4363-24/42

LC6527N/F/L, LC6528N/F/L : Osci (OSC2) OPEN External clock weeecececeeeeeeeseeeeecceeeeeeeeeseceececeereeeseeeeeeresesereress VDD Se Do Cnn neSnens Sues IpEennnnnnes Beem SOnnnmnnnerns |) 0/0) text hext< text text Fig. 1 External Clock Input Waveform * External clock can be used at selecting 2-pin RC option or 1-pin external clock option, and cannot be used at ceramic resonator oscillation. OSsC1 osc2 | OSCc1 osc2 | Cext Rext Ll Ceramic Fig. 2. 2-pin RC Oscillation Circuit Fig.3 Ceramic Resonator Oscillation Circuit VDD cecterceecpeeeseetonceseeeerereceoee> Lower limit of operating VDD fadoneeneeeeeeereennenseeee= OV Osc. Stabilized OSC Unstabilized OSC period 1CFS Fig. 4 Oscillation Stabilizing Period No. 4363-25/42

LO6527N/F/L, LC6528N/F/L Table 1 Constants Guaranteed for Ceramic Resonator OSC 4MHz (Murata) CST4.00OMGWU (built-ing) [ R [| 0a | cs8i00 [RT 2.2ka | CRES (=0.1 4 F) IMHz (Kyocera) a [Ro | 800KHz (Murata) Fig. 5 Reset Circuit CSBB00} [ R | 222 | (Note) When the rise time of the power supply is 0, 800kHz (Kyocera) the reset time becomes 10ms to 100ms at KBR800F CRES=0.1)F. If the rise time of the power supply [RR | oo | is long, the value of CRES must be increased 400kHz (Murata) so that the reset time becomes 10ms or more. csbaoor [R22 | 400kHz (Kyocera) KBR400BK ; [Rr [oa No. 4363-26/42

LCO6527N/F/L, LC6528N/F/L RC Oscillation Characteristic of the LC6527L, 6528L Fig. 6 shows the RC oscillation characteristic of the LC6527L, 6528L. For the variation range of RC OSC frequency of the LC6527L, 6528L, the following are guaranteed at the external constants only shown below. VDD=2.2V to 6.0V, Ta=-40°C to +85°C External constants Cext = 220 pF Rext = 12 kQ 281 kHz < f(MOSC < 580 kHz If any other constants than specified above are used, the range of Rext=3kQ to 20kQ, Cext=150pF to 390pF must be observed. (See Fig. 6.) (*6): The oscillation frequency at VDD=5.0V, Ta=+25°C must be in the range of 350kHz to 500kHz. (*7) ; The oscillation frequency at VDD=2.2 to 6.0V and Ta=-40°C to +85°C must be within the operation clock frequency range. fMose-Rext N ‘These characteristic curves are _ a SS it gurantee. 7) 68 CONES, x ¢g/-+ S/S 7g ae ee ERNE 3 4 g i LTTE SN SS ; tT INANL 100 2 3.45 10 2 3°45 100 Rext [ka] Fig. 6 RC Oscillation Frequency Data (Typ.) No, 4363-27/42

LC6527N/F/L, LC6528N/F/L Notes for Program Evaluation + When evaluating the LC6527/28 with the evaluation chip (LC6596, LC65PG23/26), the following must be observed, Po runction Notes For evaluat om | Mass-production chip Evaluation chip 2-pin OSC PHo and OSC2 share one pin Evaluation chip has PHo and Since input/output at PHo on (PHo/OSC2). Either of them OSC2 separately. Pin required evaluation chip results in is selected exclusively by user for option is selected as difference between evaluation option. required, Even when OSC2 pin | chip operation and mass-produc- When 2-pin OSC is selected, is selected by option, PHO tion chip operation, input/ PH0/OSC2 pin provides OSC2__| circuit is present and functions | output at PHQ is prohibited. and performs no function as as complete port PHo. PHo port. Data input to PHo/OSC2 by mistake is always read as ‘'0". osc 3 selections (1/1, 1/3, 1/4) 3 selections (1/1, 1/3, 1/4) DIV pin, 30R4 pin must be set predivider by option. available by 2 pins of DIV pin, | according to option specified 30R4 pin. for mass-production chip, fa | Ports Cc, D Ports C, D can be brought to Port C and port D can be CHL pin and DHL pin must be S| output level | “H" or “L” in a group of 4 bits, | brought to “H” and “L.” by set according to option specified 6 | at reset CHL pin and DHL pin for mass-production chip, 3 mode respectively. S| Port PU or OD can be selected Only OD without PU. [LC6596-applied evaluation] output bitwise. - External resistor (15kohms) on configura- evaluation board must be con- tion PU/OD nected to necessary port. [Piggyback-applied evaluation} Resistor must be connected to necessary port on application board, PU PU resistor brought to Hi-Z PUresistor, being external For mass-production chip, resistor (Pch Tr to turn OFF) at “L" resistor, whose impedance leakage current only flows in configu- output mode, remains unchanged at ‘“L"” Pch Tr at’'L” output mode; ration output mode. for evaluation chip, current continues flowing in PU resistor at “L” output mode. osc [2-pin RC OSC} (2-pin RC OSC] [2-pin RC OSC] constants Catalog-quaranteed constants Different from mass-produc- Frequency must be adjusted to a provide OSC at frequency tion chip in circuit design and OSC frequency of mass-produc- specified in catalog. characteristic. tion chip by adjusting variable resistor. 8 [2-pin ceramic resonator OSC] | [2-pin ceramic resonator OSC) | [2-pin ceramic resonator OSC]

9 Catalog-guaranteed constants Different from mass-produc- External constants must be

£ provide OSC at frequency tion chip in circuit design fine-adjusted according to 3 specified in catalog. and characteristic, service conditions.

3 Wiring capacitance may

provide unstable OSC. Osc [2-pin ceramic resonator OSC] | [2-pin ceramic resonator OSC] | [2-pin ceramic resonator OSC] constants Feedback resistor is No feedback resistor is For evaluation chip, feedback 2 contained, contained. resistor of 1Mohm must be (Note) connected externally. Continued on next page. No. 4363-28 /42

LC6527N/F/L, LC6528N/F/L en Continued from preceding page. 8 [Function ae Notes for evaluation

88 Mass-production chip Evaluation chip

z | Osc OSC frequency characteristic Different from mass-produc- ES, CS must be used to evaluate 3 | frequency _| as indicated in catalog. tion chip in circuit design, characteristic in detail. gg and characteristic. Su ef Operating Current characteristic as Different from mass-produc- 2 current, indicated in catalog. tion chip in circuit design, Ei standby characteristic. °| current Type No. LC6527/28 differ in ROM, ROM, RAM to be used INSTC, MEMC are set y | setting RAM. according to Type No. are according to Type No. of 8 set by INSTC, MEMC. mass-production chip. £ Evaluation Input pin RSTC, which is not SW4 on evaluation board must ° chip pin provided in mass-production remain turned OFF, setting chip, is provided. Note) When the evaluation chip is used in the 2-pin ceramic resonator OSC mode, no feedback resistor is contained unlike the mass-production chip, Connect a feedback resistor of 1Mohm externally as shown below. Since constants R, C are also differ from those for the mass-production chip, refer to Table 1 and adjust the capacitor value according to the stray capacitance of the circuit. © Evie Chip Mass-production Chip * LC65PG23/26 LC6527N/F/L,6528N/F/L oscr #28727 osc2 oscl oscz Feedbac resistor Sp (im) Oo oO Ceramic Ceramic cl T resonator T c2 ci T resonator T° (i) (ii) Fig. 1 2-Pin Ceramic Resonator OSC Circuit for Evaluation Chip and Mass-production Chip No, 4363-29/42

LC6527N/F/L, LC6528N/F/L a Mass-production Evaluation chip (*) . chip Including capacitance of Including no capacitance of Ceramic resonator c1=c2 standard cable( FAS-20-03B) | standard cable( FAS-20-03B) CSA4,00MG (Murata) 30pF [eer [on | oF KBR4.OMS (Kyocera) 330F | ser {| oo | sar | on ingCSB 101 CSB1000K (Murata) (Using Goer 22k 100pF 22k KBR1000H (Kyocera) 100pF 82pF 2.2k2 | 100pF_ | 2.2k0 aooxrie| CSB200K (Murata) (Using 5BRO0?) | _120nF 2.20 180pF 2.240 M2) BRBOOH (Kyocera) 1000F 120pF 2.2k2 150pF 22k2 €S8400P (Murata) 330pF | 220pF [3.3K | 270pF 33k 400kHz| KBR400B Ken4ooH “YO?! P Tablo 1 Reference Values of Constants R, C (") Standard cable (FAS-20-03B) is a cable attached to target board EVA-TB6523C/26C/27C/28C. Table 1 shows two cases where the capacitance of the cable is included and no capacitance of the cable is included. @ Example where the capacitance of the cable is included The capacitance of the cable is included when the resonator is connected to the user's application board through the cable from the EVA-TB6523C/26C/27C/28C. © Example where no capacitance of the cable is included No capacitance of the cable is included when the resonator is placed near the evaluation chip (on the EVA- TB6523C/26C/27C/28C). When using any other cable than the attached cable, adjust the capacitor value according to the stray capacitance. : No, 4363-30/42

LC6527N/F/L, LC6528N/F/L nT C6527, 6528 INSTRUCTION SET (BY FUNCTION) Symbol —Detcription AC: Accumulator PIDP,) :tnput/output port addressed by OP, (I, 1s Contents AGL :Accumutetorbitt PC |: Program counter FTranster and diection CF Carey fag STACK — : Stock register + Edition OP Data pointer TM Timer = :Subtestion E 1 cegiter TMF Time (internal iterrupt request fing ¥ Exclusive OR “ :Memory 2F Zara flog MIOP) Memory sddrewsed by OP [__tvstoneose [aly aS 1D 7060504 [030201 00)@ Steno ef eof OO Of] [ae~0 | a ACen ae § |aecewcee pt ofoo oth porno creonmienacines Ter [| B fmecden er pr foo fifi fern fcr [cer } [Gmc femmenne ae [oo fro te fy[s acme) [reateenmonconsenenn far [| Beeline [meremen ac foooolt ys ofi|ifacmiacs The ACcontentsaretncremented +t, [ze cr |_| 23loec[oecremen ac oooolr is t|i[y [ac~caci—1 TheACcontentare decremented —1. (ZF cF |__| Fg OR ec el [cen fowcremenr foro of 10 fr [ier 0r [neon omen demmesed—1[2F eF [| i ® 5 [A single bit of the M{DP) specified with H 0000]! 0 B:Bo MiOP, By Bo) =! ByBy hat. ‘A tingle bit of the MIDP) specified with RMB bit [Reset M data bit 1 0 BiBo M{DP. B1Bo! -O 88 i reset. Ting asian of ie AG conmgos pd Add M to AC oo000 AC (AC}+ (MiDP)) | the MIDP) contents Is performed and ZF CF the cesuit |p stored in the AC. AC {ACHE (MI DPT) | Bian ae or ACoarformd and Add M to AC with CF ind tha M{DP) contents Is performed and | ZF CF 7 “Tha AC cortorts and the MIOPY coments i Exclusive of M 10 AC AC —(ACI¥ (MIOP)) are exclusive: ORed aod the result is stored § inthe The AC contents ond the WTOP] conterie 5 |™ Compare AC with M MiDP))-+ Aci +1 | re AC contents and the MOT comens | ze Cr 8 setireset, 4 [Comparison result {CF [ZF] i [oaoeryscaci 0 [-3—| 2 mor =iacr [1 [1 | :] (wppny<iacy [| 1 To} € Blalito AC contents and the immediate € [craera |compare AC win [0010 Thiglito Hiacy+1 | The ZF CF < ammedrate data o100 date Iglgiylq are compered and the ar ‘nd CF are sete, [Comparionrenit T cr [26 | [at titestacr| o [70 | Tztetitg saci | 1 [| [igtgh tocar] + | 0 Load AC with “The imamediote date 1g)ghylg Ws loaded in a {E__[seec ew [ooo [or ofr [uon-as[macmmmentnenon | | e (oad Ae trom Wo JOO 1 0 [0.001 {i | [ac (wDP) | The MDP) contre or lode Inthe AC. LDZ data] Load OP with Zero and} fa t2 ty to OPu 0 ‘The OP y and OP ore loaded with 0 and © OP. with immediate DPimialatito the Immediate data 19121 Ig respectively. g data respectively B [tH dato [toad Den with OPn= blo The OP yy Is loaded with the Immediate H immediate dala ane lilo. § [imo Tincremens ore [PT TO fom nerds [ebrenennveneemmnnd sy far P| [oem —[orcenen on [ro fe Pf foun ion-1 [Teoh amteweaisenens far [| ae BELA Transter AC 19 OW [ttt [ort |v |r [ors -1acr ihe AC contents ore tra emeory | IMP agar | Jump 011 0| 0 Pere PCaPaPaPiPePs [A lump to the sddren specified H Py PePyPa|P3P2 Pi Po PaPaP2P1Po | With immediate data PgPgP7PePeraPar2| i P,Po coun, ET Czp waar [carr subroutine an tne [101 1 [PaP2PiPo STACK —1PCI+1 | Anubroutine In page 0 called, z 1210 page PC ans PCI ~9 0

2 PCs~2e-P3P2P1Po

4g | cAt acer [car subroutine 101 0|1 0 Pare STACK(PCI+2 | Asubroutine in called ? /P7 Ps Ps Pa}P3P2P1 Po Penn

3 PoPsPaPsP2P1Po

li frantornmemfotrofeot eb pemstacn _[Amuntonenmenieosm [|| No. 4363-31/42

LC6527N/F/L, LC6528N/F/L [__tmmstenen_| 4 Function Te single DH of the AG specified with Teena nba Bar sear [Branch on AC bx fot 1 1 To 0 tita|2 [2 [PCrm~o~ Pr Peers TT ee a tt «branch Perepeeey IP) PoPsPa|P3P2P1 Po Fee eee trans apecitied uth ihe immadiat Sohewratt i oaciet das eats? ah Po wins are Tf single Bit of the AC speclied with Mownoric waa Branch on no AC pit [OO 1 140 Otrto|2 [2 | PCr~om PrPePsPa themed dt tg, era fo NOBNAS secre PrPePsPe|P3P2Pi Po 2P2P1 Po | tne address apeeifind withthe immadiate priecores We ACr=O date PaPgPgP ah gP2? Po within the meme Page occur, ch on es — | ie singe Bit ofthe MOFT soeclfied with *PePaPalPyP2 Pi Po 2°21 Po |e addres spaced ith the Immedlate w(MDP.trtol=1 [date PoPat oP aPaP2P Po within the ame page occurs 5 aa BNMI a0d'| Brancy on ro Mbit [0011/0 Vito PC1~07 P7P5PSPa ‘Nimes di nie err Py PaPs Pal Pa Pa Pi Po, P2P2P1 PO | the address specified witn the immediate A (Mi0P.t 119: )=0 | Gate PyPgPgPghgPoP Po within the weme page occurs BPI agar [Branch on Pon ba [OT 111 Otito[2]2[PCr~onPrPepsre | Ta Ma AT al toa Tek arise een Pr Pe Ps Pa|P2P2P1 Po P3P2P1Po | branch to the eddrem apecitisd with the teeth Hf (P(DPL Lito) J=1 | Immediate data PyPQPePgPaP2P Po, within the same poge occurs

2 PL) wee remo 870

BNPI addi] Brancn on no Pot br /O.O 11/1 Otrto PCr~om P7PEPS Pe ith ie Inmadlte date re D8 ‘epee Pr Pe Ps Pal Pa Pr Pr Po P2P2P* Po | Branch to the adden ecified with the ent (PCDPL. tit. =O | Immediate date PrPQPePaP sha? Po within the same page occur. _| BTM aadi| Branch on timer or1rit|{rtroo PCrmom Pi Pars Pe [iyi THE, GU a Brenih to She TM Pr P.PsPalPyP2Pi Po PaP2P: Po [ania PoPghePghaPzP Pa within the sme Ws TME = age occur Tha TAP irene, then TME =o BNTM addi Branch on no times [0011/1100 PCr~om PrPoPsPa (gine TMF HO. 8 Branch to, tha TMF PrP6Ps Pa |PaP2 Pi Po PaP2PiPO [dala P,PggP4PsP2P Po within the same ww TME=0 poge occurs. The TMF is reset then TME <0 BC ada | Branch on CF rs PorconPrPePome (Ae cE wT y Bach Pr Peps es |P2P2P1 Po P3P2P1Po | Immediate date PyPEPEP4PaP2P Po, ucrs) within the same page occur, BNC addr | Branch on a0 CF 001 1|1 111 [2 ]2[Pcr-omPrPersra [Mme ce OF ithe P1P6PsPa|P3P2Pi Po PP2P1Po |immediate data PyPQPsPaPaPaP Po «CF =0 within the same page cours. BZ agar | Branch on 2F O11 i fi 110 [2 [2 [rcr-o~PrParsra [hme Ze RTs brane we P1P6PsPalPsP2P1 Po PP2P1Po |immadiate dete PyPgPsraPaP2PiPo eta) within the same page Occurs BNZ adgr| Branch on no ZF 0011/1110 ]2 [2 {Pcrmo—Prrersre |i te Ze Os Branch 0 Pr PePs Pa lPaP2P1 Po P3P2P1Po }immediate dete P7PgPsPaPsP2P1Po 2F =O Within the same poge occurs z [1P [impr por to Ac [oo 00 [1 1 oo [1 [i [ac~(ripPun) Port PIOPL) contents re loaded Inthe AC| Z| $ [op [ovtow ac to pon 011 ofo 001 | [1 [ripen —iact The AC contents are outputted to port PIOP) : [A angie BR in port PLOP) specl ed wi wt | Set port bv < BiBol=) U

8 Vara on [Rese port bu 0 1 B:Bo PU DP 810) 0 [Asingle bit In por IOP, specified with ean ne nercion

2 the immediate dota 6 8g It reset. \\remarwe ta g eres Soop a "Fhe E end AC convert are loaded In the WHIM [wre timer TM=TEL(AC) timee. The TMF Is reset te TMF =O maton vation [No operation performed, but T machine [rr fr operator 0000|0000 [rf pte Ne sparation es *T If the CLA Instruction i used continuously i wich » manner as CLA, CLA, —————, the firs CLA instruction only is eHective and the following CLA instructions are changed {to the NOP instructions. This is alto true ofthe LI instruction. ‘The following instructions, which are included in the instruction set of the LC6523, 6526, are excluded) AND, BFn, BI, BNFn, BNI, CLI, JPEA, OR RAL, RCTL, RFB, RTI, RTBL, SCTL, SEB, X, XAH, XAQ, XA1, XA2, XA3, XD, XHO, XH1, XI, XLO, XL1, XM No. 4363-32/42

LC6527N/F/L, LC6528N/F/L C6527N/F/L, 6528N/F/L Option Code Specifying Method General Description It is requested that you should submit to us various mask options of the LC6527N/F/L, LC6528N/F/L together with the program code which are stored in an EPROM. By using our cross assembler for the LC6527, 6528, the option code can be specified interactively and stored in the EPROM. If our cross assembler is not used, specify the option code as shown below. (This is the same as the method where the cross assembler is created automatically.) The Type No. of the EPROM to be submitted is 2732 or 2764, 00H Program code area for LC6528N/F/L Program code area for LC6527N/F/L 1FFH 200H Note 1. For the LC6528N/F/L write ‘00’, 3FFH 400H Note 2 Note 2. Always write ‘00’. 800H Option code area for LC6527N/F/L, 6528N/F/L 801H 802H 803H 804H No, 4363-33/42

LC6527N/F/L, LC6528N/F/L C Version (LC6527N/L, LC6528N/L) Option Code Specifying Method Always write ‘0’ in the area of 0. 27 20 OSC mode select 00 --- No select 800k fofo] | | | | 01 Kpin external drive (1-port EXT) 10 2-pin RC OSC (2-port RC OSC) 41 2-pin ceramic resonator OSC (2-port ceramic resonator OSC) Always OSC divider select write ‘0’ 00 1/1 (Direct coupling) o1 1/3 10 «(1/4 11 -- No select Port C output level at initial reset mode Oo ‘L'-level output 1 ‘H‘-level output Port D output level at initial reset mode 0 ‘L'level output 1 ‘H‘-level output 27 20 Port A output configuration select i} Open drain output

1 Output with pull-up resistance

. Port C output configuration select 0 = Open drain output Always write ‘0’. Port D output configuration select

0 Open drain output

mw fo To tetefetetefe | Always write ‘0’. 27 20 Always write ‘0’. Port H output configuration select Note: When the 2-pin OSC mode is selected, always write ‘0’. No. 4363-34/42

LC6527N/F/L, LC6528N/F/L H Version (LC6527F, LC6528F) Option Code Specifying Method Always write ‘0’ in the area of 0. 27 20 OSC mode select 00 ~- No select

10 No select

11 2-pin ceramic resonator OSC. (2-port ceramic resonator OSC) Always OSC divider select write ‘0! 00 = =- 1/1 (Direct coupling) 01 = -- No select 10 -~-No select 11 --- No select Port C output level at initial reset mode oO ‘L’level output 1 ‘H’-level output Port D output level at initial reset mode 0 ‘L'-level output 1 ‘H'-level output 27 20 won [rs [me [re [rm [rm [ma [om [| Port A output configuration select i) Open drain output Port C output configuration select wom Co Le Lo [o [row [mm [ms [me] Always write ‘0’. Port D output configuration select i) Open drain output Always write ‘0’. 27 20 ogo ene Port H output configuration select Al . ne Pengermncen — Note: When the 2-pin OSC mode is sefected, always write ‘0’. No, 4363-35/42

LC6527N/F/L, LC6528N/F/L Notes for Standby Function Application The LC6527N/F/L, 6528N/F/L provide the standby function called HALT mode to minimize the current dissipation when the program is in the wait state. The standby function is controlled by the HALT instruction, PA pin, RES pin. A peripheral circuit and program must be so designed as to provide precise contro! of the standby function. In most applications where the standby function is performed, voltage regulation, instantaneous break of power, and external noise are not negligible. When designing an application circuit and program, whether or not to take some measures must be considered according to the extent to which these factors are allowed. This section mainly describes power failure backup for which the standby function is mostly used. A sample application circuit where the standby function is performed precisely is shown below and notes for circuit design and program design are also given below, When using the standby function, the application circuit shown below must be used and the notes must be also fully observed. if any other method than shown in this section is applied, it is necessary to fully check the environmental conditions such as power failure and the actual operation of application equipment. 1, HALT mode release conditions The HALT mode setting, release conditions are shown in Table 1. Table 1 HALT mode setting, release conditions HALT mode setting conditions HALT mode release conditions HALT instruction ® Reset (Low level is applied to RES.) Provided that PA is at high level. @ Low level is applied to PA3. Note) HALT mode release condition @ is available only when the RC mode is used for system clock generation; and unavailable when the ceramic resonator mode is used because the OSC circuit may not operate normally. 2. Proper cares in using standby function When using the standby function, an application circuit and program must be designed with the following in mind. (1) The supply voltage at the standby state must not be less than specified. (2) Input timing and conditions of each control signal (RES, PA3) must be observed at the standby initiate/release state. (3) Release operation must not be overlapped at the time of execution of the HALT instruction. A sample application where the standby function is used for power failure backup is shown below as a concrete method to observe these notes. A sample application circuit, its operation, and notes for program design are given below. Sample application where the standby function is used for power failure backup. Power failure backup jis an application where power failure of the main power source is detected and the HALT instruction is executed to cause the standby state to be entered. The power dissipation is minimized and a backup. capacitor is used to retain the contents of the internal registers for a certain period of time. After power is restored, a reset occurs automatically and the execution of the program starts at address OOOH of the program counter (PC). Shown below are sample applications where the program selects or not between power-ON reset and reset after power is restored, notes, measures for instantaneous break of AC power. No. 4363-36/42

LC6527N/F/L, LC6528N/F/L ee 2-1. Sample application 1 where the standby function is used for power failure backup Shown below is a sample application where the program does not select between power-ON reset and reset after power is restored. 2-1-1, Sample application circuit — (1) Fig. 2-1 shows a sample application where the standby function is used for power failure backup. [=}— voov S ac R160) power source eo TT up to Von R2(10k) 1F) PXX(Note) R3(47k) - Ra R (200k) (TYP) (10%) HES RS Yf1. 021 uF) (82k) () tr Vss Re. (12k) Unit (resistance: 2) (Note) Normal input ports other than PA3 Fig. 2-1. | Sample application — (1) where the standby function is used for power failure backup 2-1-2, Operating waveform in sample application circuit — (1) The operating waveform in the sample application circuit in Fig. 2-1 is shown in Fig. 2-2. The mode is roughly divided as follows: (a) Power-ON reset (b) Instantaneous break of main power source (c) Return from power failure backup vt vt yp Tre Veron ee —— — Yea <> SP

4 Vow RES VI \\ A Me RES

if' wy 7 s Ay Hy l/ Va Pex | / Vi Pox Hote VY aes! NP seem) RG | Terr ae Re \\ Rar ase CR] Ror te es {a} Power ON reset {b) Instantaneous Instantaneous break {iii) break {i}, (ii) HALT instruction cea poceccceecs esses =a iS == J NN ’ i — . Vow RES Vi. RES — es \\ [re Vi. Px / a TZ Vy HALT mode rn romeo (c) Return from power failure backup HALT instruction V*TRON: V* value when TR is turned ON/OFF Fig. 2-2 Operating waveform in sample application circuit — (1) No, 4363-37/42

LC6527N/F/L, LC6528N/F/L 2-1-3. Operation of sample application circuit — (1) {a) At the time of power-ON reset After power rises, a reset occurs automatically and the execution of the program starts at address OOOH of the program counter (PC). — Note — This sample application circuit provides an indeterminate region where no reset occurs before the operating VDD range is entered. (b) At the time of instantaneous break (i) When the Pxx input voltage does not meet Vit (the PxX input level does not get lower than input threshold level Vj_) and the RES input voltage only meets Vj: A reset occurs in the normal mode, providing the same operation as power-ON reset. (ii) When both of the Pxx input voltage and RES input voltage do not meet ViL: The program continues running in the normal mode. (iii) When both of the Pxx input voltage and RES input voltage meet VIL: When two pollings do not regard the Pxx input voltage as “’L" level, the HALT mode is not entered and reset occurs, When two pollings regard the Pxx input voltage as “L"’ level, the HALT mode is entered and after power is restored a reset occurs, releasing the standby mode. (c) At the time of return from power failure backup After power is restored, a reset occurs, releasing the standby mode. 2-1-4, Notes for design of sample application circuit — (1) e@ vt rise time and C2 Make the time constant (C2, R)} of the reset circuit 10 times as long as the V* rise time. (R: ON-chip resistor, 200kohms typ.) Make the V* rise time shorter (up to 20ms). @ RiandCi Make the R1 value as small as possible. Make the C1 value as large as possible according to the backup time calculated. (Fix the R1 value so that the C1 charging current does not exceed the power source capacity.) @ = R2and R3 Make the “H”-level input voltage applied to the Px pin equal to Vpp. ° R4 Fix the time constant of C2 and C4 so that C2 can discharge during the period of time from when V* gets lower than V*TRONITR OFF) at the time of instantaneous break until the Pxx input voltage gets lower than Vi~ (because release by reset is not available after the HALT mode is entered by instantaneous break). @ =R5 and R6 Make V+ (VgE#0.6V is obtained by R5 and R6) when the reset circuit works (Tr ON) more than (operating Vpp min + VF of diode D1). Observing this note, make V+ as low as possible to provide a reset early enough after power-ON. © Backup time The normal operation continues with a relatively high current dissipation from when power failure is detected by the Pxx until the HALT instruction is executed. Fix the C1 value so that the standby supply voltage is held during backup time of set + above-mentioned time. 2-1-5. Notes for software design © Design the program so that port Ag is brought to “‘H” level at the standby mode. @ Check a standby request by polling the input port twice. (Example) \\ BPI AAA j 1st polling BP1 AAA } 2nd polling HALT ; Standby AAA: ‘ No, 4363-38/42

LC6527N/F/L, LC6528N/F/L 2-2. Sample application 2 where the standby function is used for power failure backup Shown below is a sample application where the program selects between power-ON reset and reset after power is restored. 2-2-1. Sample application circuit — (2) (No instantaneous break in power source) Fig. 2-3 shows a sample application where the standby function is used for power failure backup. ye 100v <= oe a] en Bure GOT tre Woo Ve PXx(Note) on Y R2 (SENSE) {up to 1F}] RS (100k) (100k) Yoo R (200k)} Ra oe (yp) (on) RES Yl 02 RS (F1nF) Vss (82k) a TRI R6 &) (Note) Normal input ports other than PA3 a) Unit (resistance: 2) Fig, 2-3 Sample application — (2) where the standby function is used for power failure backup 2-2-2. Operating waveform in sample application circuit — (2) The operating waveform in the sample application circuit in Fig. 2-3 is shown in Fig. 2-4. The mode is roughtly divided as follows: {1) Power-ON reset (2) Return from power failure backup ve Wop 7 SV VPrRON iia j - y I & T\\ Son Vi. Pxx Indeterminate X_ Reset XX Normal mode —— —— Power—ON reset Pxx="L" is detected wee RES power cc eee eee eee —— — v+rron —Y +3 Yoo aN as \\L ew ar i a Vw FEE ' | a IN. vn Px Vi Pxx -fD / 7 \\ 1 7 —_— a HALT mode | / SSS ad | Return from power failure backup HALT instruction Pyxe"” is detected. V*+TRON: Vt value when TR1 is turned ON/OFF. Fig. 2-4 Operating waveform in sample application circuit — (2) No. 4363-39/42

LC6527N/F/L, LC6528N/F/L 2-2-3, Operation of sample application circuit — (2) {a) At the time of power-ON reset The operation and notes are the same as for sample application circuit — (1), except that after reset release Px x="L” is program-detected to decide program start after initial reset. (b) Standby initiation When one polling regards the Px x input voltage as ‘‘L” level, the HALT mode is entered. (c) At the time of return from power failure backup After power is restored, a reset occurs, releasing the standby mode. After standby release Px x=""H” is program-detected, deciding program start after power is restored. — Note — 1f power is restored after Vpp during power failure backup gets lower than VjH on the Pxx, Pxx="L” may be program-detected, deciding program start after initial reset. 2-2-4. Notes for design of sample application circuit — (2) @ = R2and R3 Fix the R2 value so that R2>R1 is yielded and fix the R3 value so that Ip of TR2 is limited. e R4 There is no severe restriction on the R4 value, but fix it so that C2 can discharge quickly. Other notes are the same as for sample application circuit — (1). 2-2-5. Notes for software design @ — Dsign the program so that port Ag is brought to ‘’H” level at the standby mode. @ Check a standby request by polling the input port once. (Example) H BPI AAA ;Polling HALT Standby AAA: ' No, 4363-40/42

LC6527N/F/L, LC6528N/F/L 2-3. Sample application 3 where the standby function is used for power failure backup 2-3-1. Sample application circuit — (3) (There is an instantaneous break in power source.) Fig, 2-5 shows a sample application where the standby function is used for power failure backup. ve 1o0v e Db AC Ri (50) power Re Voo source o RXX\\(Note) cr oh 3 YM ln (SENSE) (up to 1F) “7 (100k) (100k) (12k) o Yoo he GQ) 72 (200k) oz (TYP) Ra = (12k) cae) FES YL C2 (14 F)) RS Vss (82k) «’) tar Re &) (Note) Normal input ports other than PA (12k) Unit (resistance: 2) Fig. 2-5 Sample application — (3) where the standby function is used for power failure backup 2-3-2. Operating waveform in sample application circuit — (3) The operating waveform in the sample application circuit in Fig. 2-5 is shown in Fig. 2-6. The mode is roughly divided as follows: (1) Power-ON reset {2) Instantaneous break of main power source (3) Return from power failure backup ve (77795 7 > aN VttR10N SE eS > <=> SS MORES te - I A iAt MP ‘ L |; — mW Pax . A re We | Vl 4 al JS Pee Th, FE ww res Ve Pa = 7 je | iv) Normal ode Rasst YK Nermal ede) Reset WX Nera ode YO} --Cesst YY Rrmet mode ht 2 (1) Power—ON reset (2) Instantaneous (2) Instantaneouss Pye" is detected O°EaK Ui, (i) | break (ili) Px x="H"" is detected Pxx="H"" is detected. HALT instruction (Pxx="L"" is detected.) ane pore cc cern nee == —.- VtTRION oe I \\ A Vin RES ee — ‘| ry Vin Prx . v i 4

71 Ea Bo FlAw

pee. yp v HALT mode —— | | (3) Return from power HALT instruction (Px x="L" is detected) failure backup Pxx="H" is detected. VttRion: V+ value when TR1 is turned ON/OFF V+TR30N: V* value when TR3 is turned ON/OFF Fig. 2-6 Operating waveform in sample application circuit — (3) No. 4363-41/42

LC6527N/F/L, LC6528N/F/L 2-3-3. Operation of sample application circuit — (3) (a) At the time of power-ON reset The operation and notes are the same as for sample application circuit — (2) (b) At the time of, instantaneous break {i) When the Pxx input voltage does not meet Vj_ (the Px x input level does not get lower than input threshold tevel Vj_) and the RES input voltage only meets VIL: A reset occurs in the normal mode. After reset release Pxx="H" is program-detected, deciding program start after instantaneous break. (ii), When both of the Px input voltage and RES input voltage do not meet Vi_: The program continues running in the normal mode, (iii) When both of the Pxx input voltage and RES input voltage meet VIL: When two pollings do not regard the Px x input voltage as “L” level, the HALT mode is not entered and a reset occurs. When two pollings regard the Px input voltage as “’L” level, the HALT mode is entered and after power is restored a reset occurs, releasing the standby mode. After standby release Px x="'H" is program-detected, deciding program start after instantaneous break. (c) At the time of return from power failure backup The operation and notes are the same as for sample application circuit — (2) 2-3-4. Notes for design of sample application circuit — (3) e RB Bias resistance of TR2 @ =R7 and R8 Fix the R7 and R8 values so that TR3 is turned ON/OFF at approximately 1.5V of V*. Other notes are the same as for sample application circuit —{1) 2-3-5, Notes for software design Same as for sample application circuit — (1) No products descrived or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. BM Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO, LTD,, its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties, No. 4363-42/42