LC6520C

LC6520C SANYO | Alldatasheet

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© Instruction set with 80 instructions (Common to the LC6500 series) i @ ROM/RAM . : 4096 bytes/1024 bits (LC6520C/H) : 2048 bytes/512 bits (LC6522C/H) @ Instruction cycle time: 6 us (C version, Vpp = 3 to 5.5V) 2.77 us (C version, Vpp = 4 to 5.5V) 9.92 us (H version, Vp = 4.5 to 5.5V) © Serial input/output interface x 1 (4 bits/8 bits program-selectable) © 1/0 ports Input port: 4 pins Input/output common ports: 32 pins Input: input/output withstand voltage: 15 V max {all input: input/output ports) Output current: 20 mA max (all output ports) Pull-up resistance: May be contained bitwise by option. (All output ports) Output level during reset: For ports C, D, output (H or L) during reset may be specified portwise by option. Package Dimensions 3052A-Q48AIC (unit: mm) 20.0 Package Dimensions 30258-p42s!C Te oss (unit: mm) - ' s «2 2 r puedonnnngnis | * a aT; =f A ox a E> Bry — = m3 eq Sh — Ware PELE Ne: . 3 i! = bd — —— ~ — | SANYO: DIP42S TOUOLUIUH002 SANYO: QIP48A 28 SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 5202HK /4209TA/7137KI /4176KI,TS No.2076-1/29

LC6520C ,6520H ,6522C ,6522H © Interrupt function Timer interrupt: 1 INT pin or serial |/O interrupt: 1 © Stack level: 8 levels (common with interrupt) ©@ Timer: 4-bit prescaler + 8-bit programmable timer ® Burst pulse (64 x cycle time, duty 50%) output function ® Oscillator option Circuit mode: Ceramic mode, RC mode, external clock mode (200 kHz to 4.2 MHz) (Xtal OSC constants are being checked.) Predivider option: 1/1, 1/3, 1/4 ® Standby function: Standby function provided by the HALT instruction © Supply Voltage: 3 to 5.5 V (C version) 4.5 to 5.5 V (H version) © Package: DIP42 shrink type, QIP48 alP4s Pin Assignment 3 oes BEBZ2eez7F B23 BT ESS QUINT paz & = par Fes ae ed By PCO 4? PsO pas & [8 pao pa —|3 a pao Et Yootesy) Pen 14 BE PIZ rear wB 2 PO 7 matte Joe nc Pa & Sas ro 28 ?ol-pg3 eco & <-B) Pio mae ae pcr & BAS Peo 7 ee fo S Fel rez & fl Pia Pais i7 m9 NDI = ra & Apia ui Note) moo Ei ceszo “fl 0 OOH sgee ae + When mounting the QIP por A Bre . version on the board, do oe a = an not dip it in solder. | f ; + Nothing must be connected PEO a PGO Pin Name to NC pin. rer & BS PFS/iNT pin. rer & BI Pr 2iSCK OSC1, OSC2: RC, ceramic resonator, or X'tal for OSC PE & B PFI/SO INT: Interrupt esr & ~B Prossi RES: Reset ss & B FES PAO-3: Input/output common port coset & KY oscz PBO-3: Input port PCO-3: =e PDO3: PEO3: . PFO-3: Input/output common port PGO-3: P10-3: PJO-3: SCK: so: Serial Input/output port Si: TEST: Test No. 2076-2/29

LC6520C ,6520H ,6522C ,6522H Pin Description ono psf vo [toms [| a Vop Power supply Vss osci © Pin for externally connecting R, | (1) External clock input C or a ceramic resonator for (2) 2-pin RC OSC system clock generation (3) 2-pin stor OSC osc2 1] Output | © For the external clock mode, the | (4) preqiiger opti O8C2 pin is open vedivider option . 1. No. predivider 2. 1/3 predivider 3. 1/4 predivider PAg Input/output| @ Input/output common port Ag to | (1) Open drain type eH" output PAY 3. output (Output Neh PAQ 4bit input {IP instruction) (2) With pull-up transistor PA3 4-bit output (OP instruction) resistance OFF) Single-bit decision (BP, BNP (1), (2): Specified bit instructions) by bit. Single-bit set/reset (SPB, RPB instructions) ® Standby is controlled by the PAg (or PAg to 3). ® The PA3 (or PAg to 3) pin must be free from chattering during the HALT instruction execution cycle. PBo ® Input Port Bg to 3 PBy 4-bit input (IP instruction) PB2 Single-bit decision (BP, BNP PBg instructions) PCo Input/output| © Input/output common port Cg to | (1) Open drain type © “H” output PCy 3. output PC2 The functions are the same as for | (2) With pull-up e@“L” output PC3 the PAg to 3. (Note) resistance (Option- © Output ("H" or “L”) during reset (3) Output during reset: selectable) may be specified by option. (4) Output during reset: awe © (1), (2): Specified {Note) No standby control function (2) bit by bed is provided. © (3), (4): Specified in a group of 4 bits, PDo Input/output| ®@ Input/output common port Dg to | Same as for the PCg to 3.) Same as for PD1 3 the PCo to 3. PD2 The functions, options are the PD3 same as for the PCg to 3. PEo Input/output| © input/output common port Eg to | (1) Open drain type eH" output PEy 3 output (Output Nch PEQ 4-bit input (IP instruction) (2) With pull-up transistor PE3 4-bit output (OP instruction) resistance OFF) Single-bit decision (BP, BNP (1), (2): Specified bit instructions) by bit. Single-bit set/reset (SPB, RPB instructions) © PEg: With burst pulse (64T yc) output function . Continued on next page. No. 2076-3/29

LC6520C ,6520H ,6522C ,6522H " Continued from preceding page. Fovin|ree] vo | fowow mm | PFo/S! 4 |Input/output | © Input/output port Fo to 3 Same as for the PEg to 3.| Same as for the PF4/SO The functions, options are the PEQ to 3. PF2/SCK same as for the PEg to 3. However, Serial port: PF3/iNT no burst pulse output function is Disable provided. Interrupt__ © PFQ to 3: Also used for serial source: INT interface, INT input. Program- selectable. 4 bits/8 bits of serial input/output: Program-selectable Sl: Serial input port . SO: Serial output port 5CK: Serial clock input/output INT: Interrupt request input PGo Input/output | @ Input/output common port Go to | Same as for the PEg to 3.) Same as for the PG} 3 PEg to 3. PG2 The functions, options are the PG3 same as for the PEg to 3. However, no burst pulse output function is provided. Pig 4 |Input/output | © Input/output common port Ip to | Same as for the PGQ to 3.| Same as for the Ply 3 PGo to 3. Pl The functions, options are the Pig same as for the PGg to 3. Plo Input/output | © Input/output common port Jo to | Same as for the PG to 3.| Same as for the Ply 3 PGo to 3. PJo The functions, options are the PJ3 same as for the PGg to 3. Input © System reset input © For power-up reset, C is connect- ed externally. © For reset start, “L” level is appli- ed for 4 clock cycles or more. TEST Input © LSI test pin Normally connected to Vgg No. 2076-4/29

LC6520C ,6520H ,6522C ,6522H System Block Diagram RAM Pao CY ata Ky (286x6/128% 4) | ec —) PBO-3 i a Hae [ stacx 4 | & [smo s | [an fy toee | revs (rn of com PET ee 00-3 pee 0) [sare | mn | I am I ge) B0 ope BRK Ee 5. mest Oo OS [ome F288 fe, Bee! fed ee E opr s <—o Fes Ee Ao tre I fi if <— Test Oo Pao — ww : ER pods PIO-3 PI0-3 =< is RAM: Data memory ROM: Program memory F: Flag PC: Program counter WR: Working register INT: Interrupt control AC: — Accumulator IR: Instruction register ALU: = Arithmetic and logic unit I.DEC: Instruction decoder DP: Data pointer CF, CSF: Carry flag, carry save flag E: E register 2F,ZSF: Zero flag, zero save flag CTL: Control register EXTF: External interrupt request flag OSC: Oscillator TMF: Internal interrupt request flag TM: Timer STS: — Status register No, 2076-5/29

LC6520C ,6520H ,6522C ,6522H Oscillator Circuit Option [oinntne [koe 1, External Clock @ Input: Schmitt type scr af pb 2, 2-pin RC OSC © Input: Schmitt type Coxt ostt it a oscz Ret 3. Ceramic Resonator OSC cr ost H o-<}— Coramic resonator osc 2 oa c2 R © Predivider Option ae 1. No predivider © Applicable to all of 3 OSC options, © The OSC frequency, external clock = — do not exceed 1444 kHz. O81 tose of {LC6520C, LC6522¢) 3 = H @ The OSC frequency, external clock o- 6 ES do not exceed 4330 kHz. {LC6520H, LC6522H) © Refer to Table of OSC, Predivider Option (Table 2). 2. 1/3 predivider ® Applicable to only 2 options of external clock, ceramic resonator o Pa osc, fox FE] ZE| | The OSC frequency, external clock G prsdivider a do not exceed 4330 kHz. F © Refer to Table of OSC, Predivider Option (Table-2). 3. 1/4 predivider © Applicable to only 2 options of = = external clock, ceramic resonator oO 3 | tae | 2 osc. = Re SES © The OSC frequency, external clock o 8 zs do not exceed 4330 kHz. ® Refer to table of OSC, Predivider Option (Table 2). No. 2076-6/29

LC6520C ,6520H ,6522C ,6522H Options of Ports C, D Output Level during Reset For input/output common ports C, D, either of the following two output levels may be selected in a group of 4 bits during reset by option. 1, Output during reset: "H’” level All of 4 bits of ports C, D 2. Output during reset: ""L" level All of 4 bits of ports C,D Options of Port Output Configuration For each input/output-common port, either of the following two output configurations may be selected by option (bitwise). 1, Open drain type output 2. Output with pull-up resistance No, 2076.7/29

LC6520C ,6520H ,6522C ,6522H Development Support The following are available to support the LC6520, LC6522 program development. (1) User’s Manual “'LC6554 Series User's Manual” No. E21B. (Issued in December, 1987) . {2} Development Tool Manual For the EVA-410 system, refer to the description of Development Support Tools in “LC6554 Series User's Manual”. For the EVA-800 system, refer to ““EVA-800-LC6554 Series Development Too! Manual”. (3) Development Tools 1) For program development (EVA-410 system) i. MS-DOS host computer system (Note 1) ii, MS-DOS base cross assembler (LC65S.E XE) iii, Evaluation kit (EVA-410C or EVA-420) iv. Evaluation kit target board (EVA-TB6520/22/54/43/46), evaluation chip (L.C6595) 2) For program evaluation i, Piggyback (LC65PG20/22), with socket for conversion of number of piggyback pins Note. For notes on program evaluation, do not fail to refer to 5-3-1. Notes on when evaluating programs for the LC6520/22” in “LC6554 Series User's Manual’. Appearance of Application Development Tools EVA-410 System Piggyback to naan EPROM (2732 or 2764) aN a SL i a a si EPROM () FAP-40-03#2 SS mm ! we < ye . Lc6595 eee ge EF Piggyback Bette conversion awd board NFP-50A-0112 NFP-80A-0112 onal] [© Jona 7 o-0 u NFS-50A-0100. > Do J To application system Lo Piggyback ¥ wm 0.635mm-pitch flat cable {LC65PG20/22) fiittlf” Nano flex cable NFS-50A-0100 SE Conversion board CE, ST aTTTTATT VIN (TB425) CE pee (78428) Noe isi EZ \\ oars ns Evaluation Kit Target Board . Read-Write adapter for 2764 No. 2076-8/29

LC6520C ,6520H ,6522C ,6522H 3) For program development (EVA-800 system) i. IBM PC/XT, IBM PC-AT (Note 1} compatible Sanyo MS-DOS machine iii, Host control program; (EVA800.EXE) iv. Evaluation chip: LC6595 v, Emulator : EVA-800 or EVA-850 control board and evaluation chip board (Note 2) Appearance of Development Support System EVA-800 System IBM PC/XT, IBM PC-AT compatible Sanyo MS-DOS machine » Host control program (EVA800.EXE) ZS ) + Cross assembler SS (LC65S.EXE) ia S (a So Lo la 7 aaa Emulator EVA.800 or EVA-850 y Lene —~ $< Evaluation chip board PP ong EVA800-1B6520/22/54/43/46 fee CABLES > we NFP5OA Te42s User's application board (Note 1) IBM PC/XT, IBM PC-AT: Products of IBM Corporation MS-DOS: Trademark of Microsoft Corporation (Note 2) The EVA-800 is a general term for emulator. A suffix (A, B ...) is added at the end of EVA-800 as the EVA-800 is improved to be a newer version. Do not use the EVA-800 with no suffix added. No. 2076-9/29

LC6520C,6520H ,6522C ,6522H Main Specifications of the LC6520C, 6522C Absolute Maximum Ratings/Ta = 25°C, Vss = 0V unit Maximum Supply Voltage Vpp max Vpp -0.3 to +7.0 v Output Voltage Vo Osc2 Allowable up to voltage generated v Input Voltage vy) OSC1 (Note 1) —0.3 to Vppt0.3 Vv Vy (2) TEST, RES 0.3 to Vppt0.3 Vv Vy (3) PB to 3 —0.3 to +15 v Input/Output Voltage Vio (1) Port of OD type -0.3 to 415 v Vio (2) Port of PU type —0.3 to Vppt0.3 v Peak Output Current lop Input/output port —2 to +20 mA Average Output Current loa Input/output port: —2 to +20 mA Per pin over the period of 100 msec. Zloa (1) Total current of PAg to 3, PCg to 3, —30 to +140 mA PDo to 3 and PEg to 3 (Note 2) ZIoOA (2) Total current of PFg to 3, PGo to 3, —30 to +140 mA Pig to 3 and Pup to 3,(Note 2) Allowable Power Dissipation Pq max (1) DIP package, Ta = —30 to +70°C 600 mW Py max (2) QIP package, Ta = —30 to +70°C 400 mW Operating Temperature Topr —30 to +70 °c Storage Temperature Tstg -55 to +125 °c Allowable Operating Conditions/Ta = —30 to +70°C, Vgs = OV, Vpp = 3.0 to 5.5V min typ max unit Operating Supply Voltage Vpp Vpb 3.0 55 V Standby Supply Voltage Vst Vpp: RAM, resister hold (Note 3) 18 55 V “H'-Level Input Voltage Vj (1) Port of OD type, PBg to 3: 0.7VpD +135 =V Output Neh Tr OFF ViH{2) Port of PU type: Output Nch Tr OFF 0.7Vpp Vpp V Vin (3) SCK, SI, TNT of OD type: 0.8Vpp +135 V Output Neh Tr OFF Vin (4) SCK, SI, INT of PU type: 0.8Vpp Vpp V Output Nch Tr OFF Vin (5) RES 0.8Vpp Vpp V Vin (6) OSC1; External clock mode 0.8Vpp Vpp Vv min typ max unit “L"-Level Input Voltage Vir) PORT: Vpp = 4 to 5.5V, Vss 0.3Vpp V Output Neh Tr OFF ViL (2) PORT: Output Neh Tr OFF Vss 0.25Vpp V Vit (3) INT, SCK, SI: Vpp = 4 to 5.5V Vss 0.25Vpp ~V Output Neh Tr OFF Vit (4) INT, SCK, SI: Output Nch Tr OFF Vss 0.2Vpp V Vi_ (5) OSC1: Vpp = 4 to 5.5V,, Vss 0.25Vpp ~V External clock mode Vit (6) OSC1: External clock mode Vss 0.2Vpp ~V VIL (7) TEST: Vpp = 4 to 5.5V Vss 0.3Vpp V Vit (8) TEST Vss 0.25Vpp ~V ViL (9) RES: Vop = 4 to 5.5V Vss 0.25Vpp ~V ViL{10) RES Vss 0.2Vpp ~V Operating Frequency fop See Table 2. (Cycle Time) (Toye) (Vpp = 4.0 to 5.5V) (2.77) (20) (us) (6.0) {20) (us) Continued on next page. No. 2076-10/29

LC6520C ,6520H ,6522C ,6522H Continued from preceding page. External Clock Conditions (When the external clock or 2-pin RC OSC option is selected) min = typ —_ max __ unit Frequency fext OSC1: Fig. 1 See Table 2. Pulse Width [text OSC1: Vpp = 4 to 5.5V, Fig. 1 90 ns textL OSC1: Fig. 1 180 ns Rise/Fall Time textR, OSC1: Vpp = 4 to 5.5V, Fig. 7 30 ons [ie OSC1: Fig. 1 100 ns Oscillation Guaranteed Constants 2-Pin RC Oscillation Cext OSC1, OSC2: Vpp = 4 to 5.5V, Fig. 2 22015% pF Rext OSC1, OSC2: Vpp = 4 to 5.5V, Fig. 2 6.841% kQ Cext OSC1, OSC2: Fig. 2 27045% pF Rext OSC1, OSC2: Fig. 2 1541% kQ Ceramic Resonator Oscillation Fig. 3 Ses Table 1; Electrical Characteristics/Ta = —30 to +70°C, Vgg = OV, Vpp = 3.0 to 5.5V min typ max ‘unit “H"-Level Input Current hy 1) Port of open drain type, PBg to 3: 45.0 yA Output Nch Tr OFF, Including OFF leakage current of Nch Tr, Vin = +13.5V UH (2) OSC1: External clock mode, Vin = VDD +10 BA "L"-Level Input Current y. (1)_ Port of open drain type, PBg to 3: -1.0 BA Output Nch Tr OFF, Vin = Vsg 11L (2) Port with pull-up resistance: -13 0.35 mA Output Neh Tr OFF, Vin = Vss 11 (3) RES: Vin =Vsg -45 -10 uA te (4) OSC1: External clock mode, -1.0 BA VIN =Vss “H’-Level Output Voltage VOH (1) Port with pull-up resistance: Vpp-1.2 Vv Vpp = 4 to 5.5V, Io = —50 nA Vou (2) Port with pull-up resistance: Vpp-0.5 Vv loy = —10 HA “L"-Level Output Voltage VoL(1) Port: Vpp =4 to 5.5V, loL = 10 mA 15° V VOL (2) Port: IoL = 1 mA, When lot of 05 Vv each port is 1 mA or less. Hysteresis Voltage Viys RES, INT, SCK, SI, 0.1VpD Vv OSC1 of Schmitt type (Note 6) Current Dissipation Operation mode, Output Nch Tr OFF, Port = Vpp 2-Pin RC Oscillation Ippop (1) Vpp: Vpp = 4 to 5.5V, Fig. 2 2 5 mA fosc = 750 kHz typ Ippop (2) Vip: Fig. 2 foge = 350 kHz typ 15° 4.5 mA Ceramic Resonator Ippop (3) Vpp: Fig. 3 Vpp = 4 to 5.5V, 4MHz, 5 10 mA Oscillation 1/3 predivider Ippop (4) Vpp: Fig. 3 Vpp = 4 to 5.5V, 4MHz, 5 10 mA 1/4 predivider Ippop (5) Vpp: Fig. 3 400kHz 15 4 mA Ippop (6) Vpp: Vpp =4 to 5.5V, Fig. 3 800kKHz 2 5 mA External Clock Ippop (7) Vpp: 200 kHz to 667 kHz, 2 5 mA 1/1 predivider 600 kHz to 2000 kHz, 1/3 predivider 800 kHz to 2667 kHz, 1/4 predivider Ippop (8) Vpp: Vop = 4 to 5.5V, 3 10 mA 200 kHz to 1444 kHz, 1/1 predivider 600 kHz to 4330 kHz, 1/3 predivider 800 kHz to 4330 kHz, 1/4 predivider Standby Mode Ippst Vpp: Vop = §.5V (Cureut Nch Tr OFF, 0.05 10 BA Vp: Vpp = 3V_[Port= Vpp 0.025 5 pA Continued on next page. No, 2076-11/29

LC6520C ,6520H ,6522C ,6522H Continued from preceding page. Oscillation Characteristics min typ max unit Ceramic Resonator Oscillation Oscillation Frequency fcfosc OSC1, OSC2: Fig. 3 fo = 400 kHz 392 400 © 408_-kHz (Note 4) OSC1, OSC2: Vpp = 4 to 5.5V, 784 800 816 kHz Fig. 3 fo = 800 kHz OSC1, OSC2: Vpp = 4 to 5.5V, 2940 3000 3060 kHz Fig. 3 fo = 3 MHz, 1/3 predivider, 1/4 predivider OSC1, OSC2: Vpp = 4 to 5.5V, 3920 4000 4080 kHz Fig. 3 fo = 4 MHz, 1/3 predivider, 1/4 predivider Oscillation Stabilizing tcFs Fig. 4 fg = 400 kHz 10 ms Period Vpp = 4 to 5.5V, Fig. 4 10 ms fo = 4 MHz, 3 MHz, 800 kHz 2-Pin RC Oscillation Oscillation Frequency fmosc (1) OSC1, OSC2: Vpp = 4 to 5.5V, Fig. 2, 515 750 1156 kHz Cext = 220 pF25%, Rext = 6.8 k2E1% fmosc (2) OSC1, OSC2: Fig. 2, 222 350 609 kHz Cext = 270 pF#5%, Rext = 15 kQ£1% Pull-up Resistance 1/0 Port Pull-up Resistance Rpp Port of PU type: Vpp = 5V 14 ka External Reset Characteristics “H1"-Level Threshold Vt 0.5Vpp 0.8Vpp V “L’-Level Threshold Vel 0.2Vpp 0.5Vpp V Reset Time TRst See Fig. 5. Pin Capacitance cP f = 1 MHz, Other than pins to be 10 pF tested, Vin = Vsg Serial Clock Input Clock Cycle Time — texcy (1) SCK: Vpp = 4 to 5.5V, Fig. 6 3.0 us SCK 12.0 us Output Clock Cycle Time tcKcy (2) SCK (Teyc = 4 x System clock 64x Toye us period), Fig. 6 (inet Clock tcKL (1) SCK: Vpp = 4 to 5.5V, Fig. 6 1.0 us “'L’-Level Pulse Width SCK 4.0 us ‘Output Clock tcKL (2) SCK, Fig. 6 32x Toye us erent Pulse Width __ input Clock tcKH (1) SCK: Vpp = 4 to 5.5V, Fig. 6 1.0 us “'H’’-Level Pulse Width SCK 4.0 bs Output Clock tCKH (2) SCK: Fig. 6 32 x Tcyc us “H"-Level Pulse Width Serial Input Data Setup Time tICK SI: Specified for t of SCK, Fig. 6 05 us Data Hold Time tCKI Sl: Specified for t of SCK, Fig. 6 05 us Serial Output Output Delay Time tcKO SO: Vpp = 4 to 5.5V, 05 us Specified for | of SCK, Nch OD only: External 1 kohm, external 50 pF, Fig. 6 so 2.0 us Pulse Output Period tPCY PEO: Tcyc = 4 x System clock period, 64x Toye us Nch OD only: External 1 kohm, external 50 pF, Fig. 7 “H"-Level Pulse Width tPH PEO: 32 x Teyct10% us “L"-Level Pulse Width tPL PEO: 32 x TcycF10% us Note 1: When oscillated internally under the oscillating conditions in Fig. 3, up to the oscillation amplitude generated is allowable. Note 2: Average over the period of 100 msec. Note 3: Operating supply voltage Vpp must be held until the standby mode is entered after the execution of the HALT instruction, The PA3 (or PAO to 3) pin must be free from chattering during the HALT instruction execution cycle. Note 4: fCFOSC represents an oscillatable frequency. There is a tolerance of approximately 1% between the center frequency at the ceramic mode and the nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic resonator. Note 5: When mounting the QiP version on the board, do not dip it in solder. Note 6: The OSC1 becomes the Schmitt type when the OSC option is the 2-pin RC OSC or external clock OSC. No. 2076-12/29

LC6520C ,6520H ,6522C ,6522H os¢1 (osc2y OPEN External clock Fig, 1 External Clock Input Waveform osc __osc2 osct oso2 R Cox: Reet pall ¥ co i Resonator ¢ i Fig. 2 2-Pin RC Oscillation Circuit Fig, 3 Ceramic Resonator Oscillation Circuit Voo were ofee ee == == -- --- +--+ Lower limit of __ operating Vp AES Voo feeb ww ee ee enn res (=0.14) ose I Fig. 5 Reset Circuit ; ~ - Stabllized oscillation Oscillation unstabilizing period Note 7: When the rise time of the power supply is 0, the reset time becomes Fig. 4 Oscillation Stabilizing Period 10 ms to 100 ms at Cres = 0.1 HF. If the rise time of the power supply is tong, the value of CRES must be in- creased so that the reset time becomes 10 ms or greater. No, 2076-13/29

LC6520C ,6520H ,6522C ,6522H 4MHz (Murata) C1 | 33pr* 10% B00kHz (Murata) |_c1 | 220p¢* 10% CSA4.00MG c2 | 33pr#10% CSBB00D 220pF+10% CSB800K _ A fe | oa | 4MHz (Kyocera) |_¢1 | 33PF* 19% BOOkHz (Kyocera) TSOP F* 10% KeR4.oMS KBRBOOH 150pF* 10% fe foooe | [e | oa | 3MHz (Mureta) 33pF* 10% 400kHz (Murata) 4570p E+ 10% CSA3.00MG c2 | 33prF210% CSB400P 470PF+10% a | og | [ae | oa | 3MHz (Kyocera) G7pF£10% 400kHz (Kyocera) 330pF*10% KBR3.0MS 47pF=10% KBR400B 330pF+10% a | [e [oo | Table 1 Constants Guaranteed for Ceramic Resonator Oscillation tcxoy ‘SOR i 0.8V00 0.2. oo toe a ve ii it 12 sexo 50pF Fig. 6 Serial Input/Output Timing wor 0.7V00 The load conditions are the 0.25¥p0 same as in Fig. 6. Fig. 7 Pulse Output Timing at Port PEO No. 2076-14/29

LC6520C ,6520H ,6522C ,6522H Ceramic Resonator 400 kHz 1/1 (10 ps) 3 to 5.5V Unusable with 1/3, Option 1/4 predivider 1/1 (5 us) 4to5.5V 800 kHz 1/3 (15 us) 410 5.5V 1/4 (20 us) 4to5.5V 3MH 1/3 (4 us) 4 to 5.5V Unusable with 1/1 2 1/4 (5.33 us) 4 to 5.5V predivider 4 MHz 1/3 (3 ps) 4to 5.5V Unusable with 1/1 1/4 (4 us) 4to5.5V predivider 200 to 667 kHz 1/1 (20 to 6 ps) 3 to 5.5V External Clock Option | 600 to 2000 kHz 1/3 (20 to 6 bs) 3to5.5V or External Clock 800 to 2667 kHz 1/4 (20 to 6 ws) 3 to 5.5V Drive by RC OSC 200 to 1444 kHz 1/1 (20 to 2.77 us) 4to5.5V Option 600 to 4330 kHz 1/3 (20 to 2.77 us) 4to5.5V 800 to 4330 kHz 1/4 (20 to 3.70 us) 4 to 5.5V External Clock Drive | The external clock drive is impossible. When using the external clock drive, by Ceramic resonator , i, i OSC Option specify the external clock option or RC OSC option. RC OSC Option Used with 1/1 predivider, recommended constants (Vpp = 4 to 5.5V, Vpp = 3 to 5.5V). If used with other than recommended constants, the predivider option, frequency, Vpp range must be the same as for the external clock option. Table 2 Table of Oscillation, Predivider Option (All selectable combinations are shown. Do not use any other combinations than shown above.) RC Oscillation Characteristic of the LC6520C, 6522C Fig. 8 shows the RC oscillation characteristic of the LC6520C, 6522C. For the variation range of RC OSC frequency of the LC6520C, 6522C, the following are guaranteed at the external constants only shown below. 1) Vpp = 3.0V to 5.5V, Ta = -30°C to +70°C External constants Cext = 270 pF, Rext = 15 kohms 222 KHz. fmose S609 kHz 2) Vpp = 4.0V to 5.5V, Ta = —30°C to +70°C External constants Cext = 220 pF, Rext = 6.8 kohms 515 kHz S fmose S 1156 kHz If any other constants than specified above are used, the range of Rext = 4 kohms to 23 kohms, Cext = 150 pF to 400 pF must be observed. (See Fig. 8.) Note 8: The oscillation frequency at Vpp = 5.0V, Ta = 25°C must be in the range of 350 kHz to 750 kHz. Note 9: The oscillation frequency at Vpp = 4.0V to 5.5V, Ta = —30°C to+70°C and Vpp = 3.0V to5.5V, Ta = -30°C to +70°C must be within the operation clock frequency range. (See Table 2.) No, 2076-15/29

LC6520C ,6520H ,6522C ,6522H eee z fosc - Rext Vpp =5V g eer Ter25e QB |_| Lreferance onty without guarantee. _}| | Fate | | B sooo = <= ee PN EH SS [ t | ra

2 ON ||

¢ J] 7 TT TSN 8 rT JTL oN WN Fig. 8 RC Oscillation Frequency Data (Typ.) 100 NS 10 100 RC Oscillation, Rext —kQ Main Specifications of the LC6520H, 6522H Absolute Maximum Ratings/Ta = 25°C, Vgs = OV unit Maximum Supply Voltage Vpp max Vpp —0.3 to +7.0 Vv Output Voltage Vo oOsc2 Allowable up to voltage generated Vv Input Voltage vit) OSC1 (Note 1) 0.3 to Vppt0.3 Vv Vy (2) TEST, RES 0.3 to Vppt0.3 Vv V1 (3) PBo to3 -0.3 to +15 Vv Input/Output Voltage Vio (1) Port of OD type 0.3 to +15 Vv Vio (2) Port of PU type ~0.3 to Vppt0.3 Vv Peak Output Current lop Input/output port —2 to +20 mA Average Output Current loa Input/output port: Per pin over —2 to +20 mA the period of 100 msec, ZIOA (1) Total current of PAg to 3, PC to 3, —30 to +140 mA PDQ to 3, and PEg to g (Note 2) ZIOA (2) Total current of PF to 3, PGg to 3, —30 to +140 mA and Plg to 3, Pup to 3 (Note 2) Allowable Power Dissipation Py max (1) DIP package, Ta = —30 to +70°C 600 mw Pg max (2) QIP package, Ta = —30 to +70°C 400 mw Operating Frequency Topg —30 to +70 °c Storage Temperature Tstg 55 to +125 °c Allowable Operating Conditions/T, = —30 to +70°C, Vgs = OV, Vpp = 4.5 to 5.5V min typ max unit Operating Supply Voltage Vpp Vop 45 55 V Standby Supply Voltage Vst Vpp: RAM, resister hold (Note 3) 18 55 V “H-Level Input Voltage VjH (1) Port of OD type, PBg to 3: 0.7Vpp +135 VO, Output Neh Tr OFF Vii (2) Port of PU type: Output Nch Tr OFF 0.7Vpp Vop V Vin (3) SCK, SI, INT: OutputNch TrOFF = 0.8Vpp +135 V ViH (4) SCK, SI, INT: Output Nch Tr OFF 08Vpp Vop V Vin (5) RES 0.8VpD Vop V Vin (6) OSC1: External clock mode 0.8Vpp Vpp V “LLevel Input Voltage ViL (1) Port: Output Nch Tr OFF Vss 0.3Vpp V Vit (2). INT, SCK, SI: Output Neh Tr OFF Vss 0.28Vpp_«V Vit (3) OSC1: External clock mode Vss 0.25Vpp V Vit (4) TEST Vss 0.3Vpp ~V Vit (5) RES Vsg 0.25Vpp ~«V Operating Frequency fop See Table 2. (Cycle Time) (Toye) (0.92) (20) (us) External Clock Conditions (When the external clock option is selected) Frequency fext OSC1: Fig. 1 See Table 2. Pulse Width (ext OSC1: Fig. 1 90 ns texth Rise/Fall Time (rene OSC1: Fig. 1 30 ns textF Oscillation Guaranteed Constants : Ceramic Resonator Oscillation Fig. 2 See Table 1. No. 2076-16/29

: LC6520C ,6520H ,6522C ,6522H Electrical Characteristics/T, = —30 to +70°C, Vgg = OV, Vpp = 4.5 to 5.5V min typ. max_unit “H"-Level Input Current 11H. (1) Port of open drain type, 45.0 yA PBo to 3: Output Nch Tr OFF, Including Nch Tr OFF leakage current, VIN = 13.5V tH (2) OSC1: External clock mode, Vin = VoD 41.0 pA . “L'-Level Input Current 11. (1). Port of open drain type, PBg to 3: -1,0 HA Output Nch Tr OFF, Vin = Vss 11L(2) Port with pull-up resistance: -1.3 -0.35 mA Output Nch Tr OFF, VIN = Vss tr (3) RES: Vin =Vss ~45 -10 HA '1L (4) OSC1: External clock mode, -1.0 HA Vin = Vss “H"-Level Output Voltage VOH (1) Port with pull-up resistance: Vpp-1.2 Vv 1oH = —50 vA VOH (2) Port with pull-up resistance: Vpp-0.5 Vv loH =—10 nA “L"-Level Output Voltage VoL {1) Port: Io, = 10mA 15 OV VoL {2) Port: lo = 1 mA, When IOL of each 05 Vv port is 1 mA or less, Hysteresis Voltage Viys RES, INT, SCK, SI, 0.1Vpp Vv OSC1 of Schmitt type (Note 6) Current Dissipation Ceramic Resonator Ippop (1) Vpp: Fig. 2, 4MHz, Operating mode, 5 10 mA Oscillation Output Neh Tr OFF, Port=Vpp External Clock Ippop (2) Vpp: 200 kHz to 4330 kHz, 5 10 mA Operating mode, Output Nch Tr OFF, Port=Vpp Standby Mode Ippst Vpp: Vpp = 5.5V. (guint Neh Tr OFF, 0.05 10 WA Vpp: Vop =3V_ -\\Port= Vpp 0.025 5 pA Oscillation Characteristics Ceramic Resonator Oscillation Oscillation Frequency fcFosc OSC1, OSC2: Fig.2 fo =4 MHz 3920 4000 4080 kHz (Note 4) Oscillation Stabilizing tcrs Fig. 3 fo = 4 MHz 10 ms Period Pull-up Resistance 1/0 Port Pull-up Resistance Rpp Port of PU type: Vpp = 5V. 14 kQ External Reset Characteristics “H"-Level Threshold VtH 0.5VpD 08Vpp V “L"-Level Threshold VtL 0.25Vpp 05Vpp ~V Reset Time TRST : See Fig. 4. Pin Capacitance cP f = 1 MHz, Other than pins to be 10 pF tested, VIN = Vss. Serial Clock —_ Input Clock Cycle Time — texcy (1) SCK: Fig. 5 3.0 bs Output Clock Cycle Time tcKcy (2) SCK: (Tcyc = 4 x System clock 64x Tcyc us period), Fig. & Input Clock “L”-Level tcKL (1) SCK: Fig. 5 1.0 us Pulse Width Output Clock “L”-Level tcKL(2) SCK: Fig. 5 32x Tcyc us Pulse Width Continued on next page. No. 2076-17/29

LC6520C ,6520H ,6522C ,6522H Continued from preceding page. min typ max. unit Input Clock ‘*H’’-Level tCKH (1) SCK: Fig. 5 1.0 us Pulse Width __ Output Clock “H”-Level tcKH {2) SCK: Fig.5 32 x Toye us Pulse Width Serial Input Data Setup Time tICK Sl: Specified for t of SCK, Fig. 5 0.5 us Data Hold Time tCKI Sk: Specified for t of SCK, Fig. 5 0.5 us Serial Output Output Delay Time tcKo SO: Specified for | of SCK, 05 us Nch OD only: External 1 kohm, external 50 pF, Fig. 5 Pulse Output Period tpcy PEO: Tcyc = 4 x System clock period, 64x Toye us Nch OD only: External 1 kohm, external 50 pF, Fig. 6 "H"-Level Pulse Width tp PEO: 32xTcyc*10% us "L"-Level Pulse Width = tp PEO: 32x Toyc#l0% us Note 1: When oscillated internally under the oscillating conditions in Fig, 2, up to the oscillation amplitude generated is allowable. Note 2: Average over the period of 100 msec. Note 3: Operating supply voltage Vpp must be held until the standby mode is entered after the execution of the HALT instruction, The PA3 (or PAO to 3) pin must be free from chattering during the HALT instruction execution cycle. Note 4: fcFOSC represents an oscillatable frequency. There is a tolerance of approximately 1% between the center frequency at the ceramic mode and the nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic resonator. Note 5: When mounting the OIP version on the board, do not dip it in solder. Note 6: The OSC1 becomes the Schmitt type when the OSC option is the external clock OSC. osc! (osc) OPEN External clock ee Cees ~ 2 +--+) 0,8V00 eee oan ens + \\e--- 0.25Vv00 — aa woes Fig. 1 External Clock Input Waveform . Voo _e ee fee, Lower limit of operating Vpp osel ose2 i ee R Ceramic 1 + Resonator gz 4 i Stabilized oscillation Oscillation unstabilized period . WS _Fig. 2 Ceramic Resonator Oscillation Circuit . Fig. 3 Oscillation Stabilizing Preiod No. 2076-18/29

LC6520C ,6520H ,6522C ,6522H —_— ‘MHz (Murata) [_C1 | 330 F£ 10% sad oom = Voo ns 4MHz (Kyocera) 33PF+ 10% KBR4.0MS 33pF£10% Cres (=0.14) _ a Table 1 Constants Guaranteed for Ceramic Fig. 4 Reset Circuit Resonator Oscillation Note 7: When the rise time of the power supply is 0, the reset time becomes 10 ms to 100 ms at Cres = 0.1 uF. Jf the rise time of the power supply is long, the. value of CRES must be increased so that the reset time . - becomes 10 ms or greater. texey sek | bs 0.8V08 0.25V00 toa . a we (oxo S00F Fig.5 Serial Input/Output Timing wor 0.7Vo0 The load conditions are the 0.3V00 same as in Fig. 5. Fig. 6 Pulse Output Timing at Port PEO aa 7 a Predivider Option Circuit Configurati Frequenc: vi (Cycle Time) | vo | mmm | Ceramic Resonator OSC External Clock Option | 200 to4330 kHz 1/1 (20 to 0.92 4s) 4.5 to 5.5V | hey et ae | The external clock drive is impossible. When using the external clock drive, OSC Option specify the external clock option. Table 2 Table of Oscillation, Predivider Option (All selectable combinations are shown. Do not use any other combinations than shown above.) . . No. 2076-19/29

LC6520C ,6520H ,6522C ,6522H Notes for Standby Function Application The LC6520, LC6522 provide the standby function called HALT mode to minimize the current dissipation when the Program is in the wait state. The standby function is controlled by the HALT instruction, PA pin, RES pin, and serial transfer completion signal. A peripheral circuit and program must bo so designed as to provide precise control of the standby function. In most applications where the standby function is performed, voltage regulation, instantaneous break of power, and external noise are not negligible. When designing an application circuit and program, whether or not to take some measures must be considered according to the extent to which these factors are allowed. This section mainly describes power failure backup for which the standby function is mostly used. A sample application circuit where the standby function is performed precisely is shown below and notes for circuit design and program design are also given below, When using the standby function, the application circuit shown below must be used and the notes must be also fully observed. If any other method than shown in this section is applied, it is necessary to fully check the environmental conditions such as power failure and the actual operation of an application equipment. 1, HALT mode release conditions 1-1, Supplementary description of release by serial transfer completion signal On completion of serial transfer, the HALT mode is released and the execution of the program starts with an instruction immediately following the HALT instruction. This function can be used to execute the program only when serial transfer occurs, placing the program in the wait state when no serial transfer occurs. This function is effective in reducing the current dissipation or clock noise. — Notes — @ Release by the serial transfer completion signal is available only when the RC mode is used for system clock generation; and unavailable when the ceramic mode is used. © On completion of serial transfer, the HALT mode is released unconditionally. In an application, such as capacitor backup application, where the current dissipation must be kept as low as possible during backup and serial transfer by external clock is also used, the HALT mode is released when serial data is transferred ex- ternally during backup. 12, Summary of HALT release conditions The HALT mode setting, release conditions are shown in Table 1, Table 1 HALT mode setting, release conditions HALT mode setting conditions HALT mode release conditions HALT instruction 1 Reset (Low level is appled to RES.) Provided that PA3, (PAg to PAg or PAg is program- 2 Low level is applied to PA3, (PAg to PAg or PAZ, selectable) is at high level. is program-selectable.) 3 Serial transfer completion. Note) HALT mode release conditions (2), (3) are available only when the RC mode is used for system clock generation; and unavailable when the ceramic mode is used. 2, Proper cares in using standby function When using the standby function, an application circuit and program must be designed with the following in mind, (1) The supply voltage at the standby state must not be less than specified. (2) Input timing and conditions of each contro! signal (RES, port A, serial transfer} must be observed at the stand- by initiate/release state. (3) Release operation must not be overlapped at the time of execution of the HALT instruction. A sample application where the standby function is used for power failure backup is shown below as a concrete method to observe these notes. A sample application circuit, its operation, and notes for program design are given below, No. 2076-20/29

LC6520C ,6520H ,6522C ,6522H Sample application where the standby function is used for power failure backup Power failure backup is an application where power failure of the main power source is detected and the HALT instruction is executed to cause the standby state to be entered. The current dissipation is minimized and a backup Capacitor is used to retain the contents of the internal registers for a certain period of time. After power is restored, a reset occurs automatically and the execution of the program starts at address OOOH of the program counter {PC). Shown below are sample applications where the program selects or not between power-ON reset and reset after Power is restored, notes, measures for instantaneous break of AC power, and notes for serial transfer. 2-1, Sample application 1 where the standby function is used for power failure backup Shown below is a sample application where the program does not select between power-ON reset and reset after power is restored. 2-1-1, Sample application circuit — (1) Fig. 2-1 shows a sample application where the standby function is used for power failure backup, we im Unit (resistance: 9) tov ie [=] AC R1(50) power source i a (~1F) Yoo R2 00%) 7 Pxx (Note) R3G7k) (5008) Ra Es (7) (10%)9 RES as | C2(seIUF ) (e2k) (Note) Normal input NV TR Yss ports other than PAS RE (12ky Fig. 2-1. Sample application — (1) where the standby function is used for power failure backup 2-1-2. Operating waveform in sample application circuit — (1) The operating waveform in the sample application circuit in Fig. 2-1 is shown in Fig. 2-2. The mode is roughly divided as follows: a,.Power-ON reset, b, Instantaneous break of main power, C, Return from power failure backup, ve ve Vernon foe py nn AV Pxx _ 4 a ma eae PK iy 1/7 ‘ 7 Hy. Vi Px — Vie Pax r / a SPORT insennis {Raa(—ara s\\ Reme\\ Norma aH | eRe eae (a) Power-ON reset {b) Instantaneous Instantaneous break (iii) break (i), (ii) HALT instruction tra po or) , <5 " Vu RES ot We RS \\ je Vi. Pax a Te Ay HALT mode SS f (c)_ Return from power failure backup HALT instruction V+TRON: V+ value when TR is turned ON/OFF Fig, 2-2. Operating waveforms — (1) in sample application circuit No, 2076-21/29

LC6520C ,6520H ,6522C ,6522H 2-1-3, Operation of sample application circuit — (1) (a) At the time of power-ON reset After power rises, a reset occurs automatically and the execution of the program starts at address OOOH of the program counter (PC), — Note — This sample application circuit provides an indeterminate region where no reset occurs before the operating Vbp range is entered. (b) At the time of instantaneous break (i) When the Px x input voltage does not meet Vi_ (The Px x input level does not get lower than input threshold level Vj_) and the RES input voltage only meets ViL: A reset occurs in the normal mode, providing the same operation as power-ON reset. (ii) When both of the Pxx input voltage and RES input voltage do not meet Vj: The program continues running in the normal mode. (iii) When both of the Pxx input voltage and RES input voltage meet ViL: When two pollings do not regard the Px x input voltage as “L”’ level, the HALT mode is not entered and a reset occurs, When two pollings regard the Px x input voltage as ’L’’ level, the HALT mode is entered and after power is restored a reset occurs, releasing the standby mode. (c) At the time of return from power failure backup After power is restored, a reset occurs, releasing the standby mode. 2-1-4, Notes for design of sample application circuit — (1) © Vtrise time and Co Make the time constant (C2, R) of the reset circuit 10 times as long as the V+rise time. (R: ON-chip resistor, 500 kohm typ.) Make the V+trise time shorter (up to 20 ms). @ RyandCy Make the Ry value as small as possible. Make the C1 value as large as possible according to the backup time calculated, (Fix the Ry value so that the C1 charging current does not exceed the power source capacity.) © Rzand R3 Make the "H’’-level input voltage applied to the Pxx pin equal to Vpp. © R4 Fix the time constant of Cz and Cq so that C2 can discharge during the period of time from when V+ gets lower than V+TROM (TR OFF) at the time of instantaneous break until the Pxx input voltage gets lower than Vj (because release by reset is not available after the HALT mode is entered by instantaneous break), ®@ Rg and Re Make V+ (Vee = 0.6V is obtained by Rg and Rg) when the reset circuit works (Tr ON) more than (operat- ing VDD min + VF of diode D4), Observing this note, make V+ as low as possible to provide a reset early enough after power-ON. ®@ Backup time The normal operation continues with a relatively high current dissipation from when power failure is detect- ed by the Px x until the HALT instruction is executed. Fix the C1 value so that the standby supply voltage is held during backup time of set + above-mentioned time. 2-15. Notes for software design ® Design the program so that port Ag to Ag cannot be used for standby release and port Ag is brought to “H”” level at the standby mode. @ Input a standby request to a normal input port other than the PAg and check by polling this input port twice. (Example) BPI AAA ; Ist polling RCTL 3 ; Interrupt inhibit BP1 AAA 7 2nd polling HALT ; Standby AAA: : No. 2076-22/29

LC6520C ,6520H ,6522C ,6522H re 2.2, Sample application 2 where the standby function is used for power failure backup Shown below is a sample application where the program selects between power-ON reset and reset after power is restored. 2-2-1, Sample application circuit — (2) (No instantaneous break in power source) Fig, 2-3 shows a sample application where the standby function is used for power failure backup. ye OF Unit (resistance: 2) re e 4 power source “* (50) TR2 Yoo Yo + Pxx (Note) ene eats wird RS (100) (roo (500k) Re (typ) (10%) eS Hy ¢2 RS (uF) Vss (ek) K 71 Re i Ging (Note) Normal input ports other than PAg Fig, 2-3 Sample application — (2) where the standby function is used for power failure backup 2-2-2. Operating waveform in sample application circuit — (2) The operating waveform in the sample application circuit in Fig. 2-3 is shown in Fig. 2-4. The mode is roughtly divided as follows: a, Power-ON reset, b. Return from power failure backup. ve yoo ~*~ TP vernon ioniieeiienel y - oh 7 fe i) y Ie Vi om hee Indeterminate X Reset \\\\X___ Normal mode

1 Power-ON reset

Pxx = "L' is detected, ve en tee | alakelceeietemenaneieneteietetatel T) VoD \\. V*rrow = \\Le ew —r Vou REE ‘ 7 \\ svn Pex Vie. Pxx Be ‘ 7 i 17 — — _-—. HALT mode Normal mode K\\)--- --- = = tk ==~--~--- {7 Reset: Normal mode SS failure back HALT instruction Return from power failure mp sat” edotected V+TRON: V+ value when TA1 is turned ON/OFF. Fig. 2-4, Operating waveform — (2) in sample application circuit No. 2076-23/29

LC6520C ,6520H ,6522C ,6522H 2-2-3. Operation of sample application circuit — (2) (a) At the time of power-ON reset The operation and notes are the same as for sample application circuit — (1), except that after reset release Px x = “L"’ is program-detected to decide program start after initial reset. (b) Standby initiation _ When one polling regards the Px x input voltage as “"L”’ level, the HALT mode is entered. (c) At the time of return from power failure backup After power is restored, a reset occurs, releasing the standby mode. After standby release Pxx =H" is program-detected, deciding program start after power is restored. ~— Note — If power is restored after Vpp during power failure backup gets lower than Vj} on the Pxx,PxX = “L"" may be program-detected, deciding program start after initial reset. 2.2-4. Notes for design of sample application circuit — (2) @ RoandR3 Fix the R2 value so that R2 >> R71 is yielded and fix the Rg value so that Ig of TR2 is limited. © R4 : There is no severe restriction on the Rq value, but fix it so that Cz can discharge quickly. Other notes are the same as for sample application circuit — (1). 2-25. Notes for software design © Design the program so that port Ag to Ag cannot be used for standby release and port A3 is brought to “H"’ level. © Input a standby request to a normal input port other than the PAg and check by polling this input port once. (Example) BPI AAA : Polling HALT } Standby AAA: : 2-3, Sample application 3 where the standby function is used for power failure backup 2-3-1, Sample application circuit — (3) (There is an instantaneous break in power source.) Fig. 2-5. shows a sample application where the standby function is used for power failure backup. ve Unit (resistance: 2) 100V Lee] o AC power source Yop Pxx (Note) C1 gp RB WY Re (SENSE } (m1 FT 1100k: 00K) our (12k) Yoo {rms (5008) Re (12k) RS (1) (10) res 1262 (1 F) RS Vss (82k) &) mr RE (Note) Normal input ports other than PAg (12k) Fig. 2-5 Sample application — (3) where the standby function is used for power failure backup No, 2076-24/29

LC6520C ,6520H ,6522C ,6522H 2.3.2. Operating waveform in sample application circuit — (3) 7 The operating waveform in the sample application circuit in fig. 2-5 is shown in Fig. 2-6. The mode is roughly divided as follows: a, Power-ON reset, b, Instantaneous break of main power, C, Return from power failure backup. ve ~ole | daiaiah | teeta ate sieeeeeaeneianeen tee Vrrrion Se St “yl = — mie \\ \\ _ if Vin FES 7 VI Ate Voi Px I | ‘ y vtraaon Hf H Y iL Poot vi Pax |Z vernon ff |7 | 7 Pm _ ves Vu Pax IT V/ Nv. | im Inaeterminave | Reamer oa Roser YK Nerina mode Xp - (“Reset [JX Neral moe — et yD (1) Power-ON reset (2) Instantaneous pyle sayy (2) Instant. ary PxX="L" is detected, break (i), (i) gaered. anaous break Pxx = "H" is detected. HALT instruction (Pxx = "L" is detected.) wey peccce eee e nee ee ‘1 Xv q Vow RES phe — \\ —> iim Po \\ iva Vie Px { mua WOE Pa tly Ve REE Kg H nornarmoeY- wna ALT meee... eset YJ Normat made ———— | {3) Return from power . HALT instruction failure backup PxxX = "H" is detected, (Pxx ="L" is detected.) V+TRION: V+value when TRI is turned ON/OFF. : V+TR3ON: V+ value when TR3 is turned ON/OFF. Fig, 2-6. Operating waveform in sample application circuit — (3) 2-3-3, Operation of sample application circuit — (3) (a) At the time of power-ON reset The operation and notes are the same as for sample application circuit — (2) (b) At the time of instantaneous break (i) | When the Px x input voltage does not meet Vj, (the Pxx input level does not get tower than input threshold level Vj) and the RES input voltage only meets VIL: A reset occurs in the normal mode. After reset release Pxx = “H’’ is program-detected, deciding program start after instantaneous break. (ii) When both of the Px x Input voltage and RES input voltage do not meet VL: The program continues running in the normal mode. (iii) When both of the Px input voltage and RES input voltage meet VjL: When two pollings do not regard the Px x input voltage as “L”’ level, the HALT mode is not entered and a reset occurs, When two pollings regard the Px x input voltage as “L’’ level, the HALT mode is entered and after power is restored, a reset occurs, releasing the standby mode. After standby release Pxx = “H” is Program-detected, deciding program start after instantaneous break. (c) At the time of return from power failure backup The operation and notes are the same as for sample application circuit — (2) No, 2076-25/29

LC6520C ,6520H ,6522C ,6522H 2.3.4, Notes for design of sample application circuit — (3) e Rg Bias resistance of TR2 © R7and Rg Fix the R7 and R8 values so that TR3 is turned ON/OFF at approximately 1.5V of V+. Other notes are the same as for sample application circuit — (1) 2-3.5. Notes for software design Same as for sample application circuit — {1} 2-4, Notes (1) for providing seria! transfer Notes for providing power failure backup and serial transfer This application assigns top priority to power failure backup, When power failure backup is provided, serial transfer may not be provided normally. (1) When the internal clock is used for the serial clock: Execute the serial transfer start instruction immediately before executing the HALT instruction. If this is done during serial transfer, the power failure backup mode is entered without normal transfer. (2) When the external clock is used for the serial clock: When power failure is detected, it is most prioritized that the HALT mode is entered, providing power failure backup. !t is necessary to design an application system where no release signal by serial transfer completion is inputted to the HALT instruction executing cycle and no release signal is inputted during backup. 2.5. Notes (2) for providing serial transfer Notes for providing HALT and serial transfer for program standby without power failure backup This apptication assigns top priority to serial transfer. The following notes for system design must be observed. (1) When the internal clock is used for the serial clock: Transfer starts when it is ready on both sides. When transfer is not ready on the other side, the HALT instruction is executed to reduce the current dissipation. When transfer is ready, the HALT release signal (RES, PA) causes return from the standby mode, starting seria! transfer. (2) When the external clock is used for the serial clock: Synchronization must be provided between microcomputers to prevent the HALT instruction and HALT release signal (RSIOEND) from overlapping. When transfer is ready, the serial transfer start instruction is executed and the program is placed in the wait state. The other side adjusts thime so that no overlap occurs between the HALT instruction and transfer completion and starts serial transfer. On completion of transfer, the HALT mode is released and the program is executed with an instruction immediately following the HALT instruction, No, 2076-26/29

LC6520C ,6520H ,6522C ,6522H C6520, LC6522 INSTRUCTION SET Symbo! Description AC: Accumulator (OP): Memory addressed by DP (1,0 F:Contants AC Accumulator bit t P(DP_) —_: Input/output port addressed by DP). ‘L sTranster and direction CE Carry tag C "Program counter + Addition CTL: Controt reginer STACK: Stack register = Subtraction OP :Data pointer ™ Timer 2 :AND e eister TMF: Time (internal interrupt request flag vo :oR EXT: External interrupt request flag At, Ha, La: Working register Exclusive OR Fn Fag bit n ze Zero tag © ™ :Memory 1 A hk Pano [Ga ]eee ke ro ofe oc afifi face [wateommnaneret eT flac Jowrcr [rva ofoo et fp fermo__[Tmereonemanamis § [sce @ foo perms cree ee f [ome [eonbienea ae [vv efro nr fr facnith [Teaemmiaeamaiaeiw ar | Elise _[ncenen ac [ooo of rol |rlacnuc ti [Teateonmericmnmesst fare | | § [occ Torcenen ac foo oe fn) [rt faceuc=1lteateminssvarconen-1 [ere 5 [ha Rorate AC leit 5 ACOMICFH AGasi= | The AC contents are shifted left through B [PAL [tmougn ce gee " [ecm cen vacs) | meee mrt 4 [TAE[Tronster ac to € [0000 EtAc) The AGcontents are rartered tothe, |" [| feng AC win Ffoooa | oy p | RO [pabeareneens recom o [J FF [inv —Yiverenes woo oT +1 oft [wri GnGAI= [Tm worlconemaeineenmned [iF eT | |B foew—foscrmencw foro re [ra 1 fr wien =u or) -1 [rm MOM cnare we cements [ze cr |

5 A single Bit of the M(DP) specified with

ee SMBbit | Set M gata bit 00001]1 0 B:Bo MOP. Bi Bo) <1 818 is wet. a ‘A single bit of the MIDP) specified with Ha Reset M data bit 10 BiBo MiDP.ByBol-O |g Bpinreset, a Ginary adgition of the AG contents and Add M to AC o1rio]o000 AC (AC) + (M(DP}) | the MIDP) contents is performed and ZF OCF the result stored in the AC. = Binary addition of the AC, CF content ADC Add Mio AC wrnCF OO 1010000 AC (AC) + (M4 OPS) and the M(DP) contents is performed and | 7F CF +icF) the results red in the AC. Decimal adjust AC i contents fos [omnes [iva efrerofiffensacio [wrmmenesconn |e |_| "The AC contents and the MTOPT content gz fext — [exctusve or Mtoacl 111 Ac (AC) v (MiDP)) | tre exclave OR ond te ret sored) ZF 5 inthe A

5 The AC conan ad the TDP conten

g AND And M to AC AC AC} A(MiDP}) agg AND ‘and the result is stored inthe | ZF § ‘The AC contents and the MOP] contents i Or M10 AC 0101 Ac =taciy (moe) | YEON! and he et trad nthe “The AC contents and he MIDPT contents B [ew [compare aC with (aber) + (AC) +4 Wanou nude amare [2 oF 2 setirest, zg (aoris>iaci | o To | 3 [CSTE | i imort<racr {1 | 0] © [cr data [compare AC win [001 .0]1 1.00 [2[2|istaito +caci+1 | The AC contents and the immediate [7¢ cr < immediate data 0100 figtalito data gla! q!o ere compared and the ZF and CF are set/reset, Trigtite>iacy [oT 0] Hyigtita Staci [1 Tt) [ynitpcw@ery 1 | o Gur onva| Comeare OFr wth 10.01 041 1.6.0 ]2|2 [ror viatzty to | TheOPL contentsand the immediate 7” immediate data 0107 fatairte data 1glp!4 19 ae compare, Toad AC with The immediate data Talgh lp is Toaded in [estore ne toe [STS TOO Of [me iac) | rent com ve rah mI [io fiowe 8 tom ove ofa oo [ri [ac = OW or) | taemOM esa isn | = ———"TThe AC contents end the MID The ZF os setirewt, e Exchange AC with M ‘0 M2MiMo AC) = (MiDP}) contents are exchanged and then the erage s then modily OPH DP iOPad w DPy contents are modified with the | ZF fuer 10>, 5 with immediate data OM 2M Mo _| eodients of (OP) VOMDM Mo some & ik Exchange AC with M[1 0 1 010000 |? {2 faci = (mori) “The AC contents end the M{OP) contents Lato £ are exchanged, a oreconen = Tie AC contaniy ond the MID tae eho Elm [escnonge ac wan mii vty Ty yo [1 [2 fas towoe) [RAG Sis ita en me [zr | oon § then increment DP OPL—10P uy +t Be, contents are: heremented $1 a woaere st xO Exchange AC with M 2 [tach (mors) Pe |e Maen then decrement OP: oP, (DP) -1 DPy. contents are decremented —1. erica RTBL | Read cable cata trom oot) ‘AC. E-ROM TE Poe ee coe eee program ROM 1PCh.£. AC) | withthe E and AC content ae londed In The AC and £ No. 2076-27/29

LC6520C ,6520H ,6522C ,6522H h EE Deseroion E | coz data] toad DP with zero ang]? 0 0 0 |iatz ti to OPK =O “The OP; and DP are loaded with O ard 3g OP wih immediate OPr mia tg tito |theimmedite dats tyta! tg respectively A data respectively [UHI ara | Load OPH wah 0100 DPA ia12I lo | The OP, is lowded with the Immediate i immediate data data glghy1o- 4 [imo [wrenen on [To Te [Asn [ mo ommmmenmr [|_| § [co Jorcenew-an Pro fr [rf forr=tons=1 [ear emamemmarerend—t fer [| : Torte aC io A [ PTY Oa [ifr foreman [eatenanaeneantoretmnebh] | & Transter OPLto AC [1110 |1 001 [1 |) [acec0PL) Fhe OP, contenisare wersferradtothe AQ 7F | < (|xat Exchange AC wih ie to The AC conten ard the contents of £ | xao [working regster at 111 1 0 FOG!0 0 (AC) S1A0) ‘working register At are exchangs S| xa 1110 [0 sf00 (ac) SKA) At ie enon are of Ag A Az. Aa B | xa2 11101 of00 (AC) 5 (a2) secording £0 110° 2 | xa3 1110 ft 10 0 (AC) 143) & [xra Exchange OPH with 2 —_ ‘The DP), contents and the contents oF 5 183 = working register Ha are exchanged, Fe XHO |workng register He [1 111 [17630 0 (OPH) (HO Wes epead sitter of Hor ht Ft XH ritt|riiioo (OPH) StH) according toa $Elxte | excrange DX wan 3 The DP; contents and the contents of 2 eBt cking Yegister La are exchanged. FE] xro working regsier ta ofdto o [1 |r froP.ssctoy Teh onigned either of LO or Lt according xu fifo o | |r [ropa sien) tos. ‘4 —— — § [Pra F00] Reser tag ox 63626: Bo Fa =O “The fag pected with BBB Bp hrewet| 7p Teena, § Fr fet Fi fia Fi wr

2 Tre 9 wines

2 Signet

= Gee tyhty IMP aaar| Jump sn the curent [0 1 1 0 [1 PoPere POmPCHI Ree) [A lume to the edaress specified Wis bann ow bank Ps PePsPa|PsP2P Po bePapoprees| mim the Pou for POL) oa sree ‘2 ; immediate dat 4 Soret come PaParePs Po | protean PuoParerrPePsraPaPa SF PEA [Jump in urea = ‘A Jump to the acdress specified with IPE: Jump nthe surrent PCr~0 T1E.AC) | the'contents of the PC whose low-order Eg page modified by 8 bits are replaced by the E and AC F and AC contents occurs, § | 62° saa [C01 subroutine on the [1 01 7 [Pa Pa Pio STACK ==(PCI41 _ [Asubroutine in page 0 of bank 0 is called. g reo page PCi~6,PC1~9 -0

2 PCs~2--PaP2P1 Po

B [CAL adar [Catt subroutine in the [1 0 1 O11 PoPsPe STACK={PCI+2 | A subroutine in bank O is calle. 3 zero bank P7 PePsPa|P3P2 P1 Po PCito + OPOPoPEP? ? PPsPaPaP2P1Po 5 lat [rom romamere [otro [oot e || [renistacn | Amustonenoneemn | _[ | fT Return trom interrupt 0070 PC (STACK) ‘A return from an interrupt service routine | 2F CF routine cr ZF=<CSF.zsF | ours BAt addr [Branch on AC bu [O11 1 [00 tito PCI<o= B7 PePaPa | ite See Et of te AC west wiih owen w6A0 7 | papaps Pa POP Pe | the immediate data t3to is, # branct wa movie PrPePsPe|PapaP) Po WAC oP? | tot aro spate’ with the immedi omeameatt data PPePePaP PoP Po within the same age occurs. | paar Branch on wo AC bi ee Ta single bit of the AC specified with Tinomave wBRAD ‘Nat addi] Branch ac bu [001 1 [0 Otite PCr ~0~ Pr Pose [Te et ity Rarer to Repel iP Pees Pa|P9P2P1 Po PaP2P1Po | tne address specified with the immediate etwnaveott M act=0 data PrP GPPaP PoP Po within the same age occur, BMt add! [ Branch on M bit 011110 1tyto[2 [2] PCr~cm PrPePsPa Wo angle bit of the MOP weed wih Mneoncia BHD te . P/PaPsPalPaP2 Pt bg | the immediate deta tytq is 1, a brane! Gia emoreato PoPa|PaP2Pi Po PaP2PsPO line address epecilied with the Immediate esaunat| it (MIDP.t 1 tA}=1 | data PoP EPP gPaPZP Po within the same page occu. BNMI addi] Branch on no Mb [001110 tito PC7~0% Pr PoPsPa | tas ‘of the MI(OP) wpecified wil ‘raanie® BNMO the Immadiate data tytg Is 0, a branch t obwg core P7 PePs Pa] Ps P2 Pr Po P3P2P1 Po | ene addres soscfiad withthe immedat® omecce Mt (MIOP.t ito) =O | dete PyPgPgPghaP2P Po within the same age occur. BPr adgr [Branch on Pon bh |O.1 1 111 Otito{2 [2 | PCr~o—PrPePsre | #8 Smale bi of por PIDP.) specified Meamanic BPO 10 Py Po Py Pa] P3P2P 1 Po PaP2PsPo | with in, immediate daca ito i 1. @ rs e Branch to the address specitid with the woe 1 (PIDPL tit od J=1 | immediate daa PoPePePaPgP2P Po within the same page occurs, ENPL ede Bren on ve Pon ba]O O11 [1 Otrto|2|2| PCr~o-Prershs [Un tule BR ol pon FOP] weciog Pa Pe Ps Pal Pa Pz Ps Po| PaP2P1Po | branch to the adden speclid with the W(PCOPL.1 it oh} =O. | enmediate date P;P—PsP4PaP2? {Po within the same peas occurs. i| Branch on torn == Py lit the THF is 1, a brench to thal BTM agai] Branch on timer otiifi1oo PCT ~0— PT PSPS Pe Ee ee ae mnadiate| IME P7 PePsPa|P3P2 P10 PaP2P1 Po [dace PyPgPeP4PgPzP Po within the same WTME=1 page oceura, The TMF is rest | then TME <0 No, 2076-28/20

LC6520C ,6520H ,6522C ,6522H ie ge Deserpton Hi 1D; 0695 04 ]Os 02 0; Do | ® no tuner ees The TMF Te 0,6 branch to thd tar BNTMadai] Branch on no wmer [O01 1 [1 1.0.0 [2 ]2[PCrm~om PrPePsre [hatte TME, ik Oe Branch te the ru IP) Pg Ps Pa |P3P2P1 Po PaP2P) Po |data P7PePP4Pa?2P 1Pp within the same 7PaePaPsP2P Fo) A TMF=0 page occurs, The TMF is reset. then TMF <0 | Brad [Branch on mewn Jory i {ry ov PcraomPrPoPohs [LMR EXTE RY a Bane © | exre P7P6PsPa|P9P2 Py Po P9P2P1Po limmedate data PpPePePaP PoP P EXIF = 1 ‘within the same page oceurs. The EXTE unen EXTF =O is reset. 2 = TF h 0, a branch 10 BNI agar [Brana on no snierupr]O O11 [1 1 0 1 [2 [2 [PCr-a--PrPePors [It the EXTE 0, a branch eXTF : Pr P6Ps Pa |PaP2P1 Po P3P2P1Po |immediate data PyPgPsPaPaP2P1Po, ul EXTF=0 wrtin the se page ours. The EXT theo EXTF 0 | isroset 8 [ec dar [Branch on CF Ot iv] 111 fefa[rcr-o~Precrsre [H me cE BT g cat

2 P)PePsPa[PaP2P1 Po PaP2P1Po | immediate ‘dato P7PePePQPaP2P1P0

: : wor} within the sre poe Seu. | BNC agar | Branch on no CF 0011 ]1 111 [2]2[PCr-omPrPersre [If the Ce Sled Byeeh g 7 PePsPe|PsP2P1 Po P2P2P1Po |\\mmadiote data P7PgPePaPaP2P1Po é CF =0 within the same page occurs T the 2F i 12 branch 1 82 addr | Branch on 2F O11 1 [1110 [22 [Pcr~o~PrPersre [imate Teg Orme Ps PePsPalPsP2 Pi Po PaP2P1 Po |immediate data PpPgPsPaPaP2P1Pq a 2F=1 within the same page occurs. @NZ agar] Branch on no ZF 0911 |1 110 [2 {2 [Peroni Porsra [ma Ze G8 brane P7PoP5Ps|PaP2 Pi Po P3P2P1Po Jimmediate date P7PgPsP4PqP2P Po, W 2F=0 within the same page Occurs. " ' Nayar rn 7 ]it the fag bof the 16 lags speciied TTT Ty Branch on Hag bx [1 1 0.1 [ngnamrno]2 [2 [PCr ~o—P7 PoP ams [UME Mag DA Gl the T8 Com spe wepane PyPePsPa|P3P2Ps Po. _P3P2P1PO Ta branch to the address specified with the the wee of Monet mmediate data PyPgPaP qh PP Po within the same page occas Teach oan 7 payne a -, [Tf the fag bh of the TE Tags specified Teron 3 BNFa adai] Branch on no Nag 001 |nanamial2 ]2 [PCr om PPC Pe Tee en Tee age. Feerpronl br IPs P5P5P4|P2P2P1 Po PaP2P1Po 1} branch to the address specified with the Smevdunotn Fa immediate data PoP ePeP PP 2P 1Po within the same page occurs pl [eww Sooo [Te of [eae = ese] fenton emmaweioainnens| z= [| § Jor ouna Ac wo pon [a1 1 0100.0 1 [1 | [PoP =1Ac) Tre AC conterv are outputted vo por POP)

2 A single Bi in por POP sbecifed wi

7 bn 7 FiDP. ByBo)=1 ingle Bit in por PIOP ] weed wi wasianpegon & [spa ox [Set 0 90.00/01 B:60]1 [2 ]PrDP, 8:B0 Areas oun B,Bbieae TEEN

3 See

S [ree we [Reser port vit 0.0.1 0 [0 1 6:80]! 2 [Pr DF: B18) —O — [Asinglebin in por PIDP,) specified with | z¢ Jere ms marion 3 ‘the immediate data 8 18 i reset. [ress oe et cont register “oo l2 12 = The bits of the contol register specified Scr bu] Set control vegater [OO 1 O]i 1002 [2 [er crv Witihe inmedite duis ByBy8 0 0 butS} 10.0.0 [828281 B0 @3828°60 | Set : veginer spestied RTL bul Reser control cegate {0.01 0]1 1 00]2]2 [ct icTLiA The is ofthe conve egier goad | 7 bist 10.0 1 /B2876160 BaBrETEs |e theimmeare dara 8620180 a ar = The € ond AC contents are loaded in the jo operation i ,operaivon [No operation ie performed, bot ¥ machine NOP [No operatio ao00]o0000 rei pe No oraaton 59 “1 If the CLA instruction is used consecutively in such a manner as CLA, CLA, -———, . the first CLA instruction only is effective and the following CLA instructions are changed to the NOP instructions, This is also true of the LI instruction. IE No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power contro! systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss, Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @® Not impose any responsibilty for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally, Mi Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of . third parties. No. 2076-29/29