LC65204A

Sanyo Semicon Device

4-bit SingleChip Microcomputer for Control Applications

Manufacturer: Sanyo Semicon Device

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ij (A/D Converter, FLT drivers, PWM Output, SANYO and On-chip 4Kbyte ROM) 4-bit Single Chip Microcomputer L for Control Applications The LC65204A is a 52-pin CMOS 4-bit single chip microcomputer. It consists of a high-speed core CPU with the minimum cycle time = 0.92 microsecond, 8-bit AD converter with 8 input channels, 4Kbyte ROM and a 1Kbit RAM (256 x 4 bits). The LC65204A has a total of 41 input/output (1/0) port pins; 29 for high withstand outputs (Drivers for fluorescent display tubes and LEDs), and 12 for input/output (common with interrupt inputs and serial . input.) In addition, this single-chip microcomputer has a two-channel timer. This timer circuit block can be used as a general-purpose timer, watchdog timer, time base timer, PWM type DA converter, melody tone generator and the like within application products. It is designed based on two types of oscillation circuits. This allows various standby operation modes. As a result, the LC65204A microcomputer can be embedded into many kinds of home appliances as, for example, display control and timer control in audio visual products. There is another microcomputer with almost all the LC65204A functions but oscillation circuit design and ambient operating temperature range. Its chip name is LC65404A, This single chip device has no subclock function and its operating temperature range is from minus 30 °C (-30) to plus 85 °C (+85). For detailed information, refer to its catalog. Features: - Seventy-seven instructions - On-chip storage capacity; 4Kbyte ROM and IKbit (256 x 4 bits) RAM - Minimum instruction cycle time: 0,92us (4.33MHz at Vpop = 4.5V or greater) 1.84us (2.17MHz at VoD = 4.0V or greater) 6lus (32.768KHz at VDD = 2.7V or greater) - Reduced power dissipation mode through system clock selection by software + (Main) system clock = 4,19MHz : 0.95us, 1.9us and 30.6us + (Sub) system clock = 32.768KHz : 61us ~ Operating temperature: Ta = -30°C to +70°C ~ Working register/Flag function + (16 flags + 8 working registers ) x 4 banks - Stacks : 8 levels - I/O ports : 41 (Total) + High-voltage withstand output ports : 21 + High-voltage withstand input/output ports : 8 + Medium-voltage withstand input/output ports : 3 « Input/output ports : 9 - AD converter (sequential comparison type) + B-bit Accuracy x 8 channels - Timer : 2 channels . + Timer 1 (interval timer) : Also used as the PWM DAC and applicable to a divider at melody tone generation. + Time base timer for clock generation : 14-level divider on-chipped - Internal wake-up function Wake-up function: Restart from a standby operation mode by using the time base timer overflow. The wake-up function together with the standby operation mode would enable a clock operation at extremely low power dissipation during a battery backed-up mode. - PWM DAC output : Also used as timer 1. + 6-bit PWM DAC + 8-bit PWM DAC or 14-bit PWM DAC SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 82093JN KAWA/NOGOJN,JK KAWA/8079TA KAWA No, 3117-1/28

Serial input/output interface (LSB first) + 8-bit input/output - AC zero cross detection circuit + The AC zero cross detection circuit is allowed to internally connected to the PF3/INTO pin through option data specification. - Interrupt function: 5 Interrupt sources and 4 vector addresses + External interrupt sources: 2 + Timer interrupt sources: 2 + Serial input/output interrupt source: 1 - On-chip oscillation stabilization period wait function: Effective at the reset. - Oscillation circuits: 2 types + Main clock: 4.19MHz Crystal oscillation or 4,0MHz Ceramic oscillation + Sub clock: 32.768KHz Crystal oscillation - Standby function: two modes; HALT mode and HOLD mode - Supply voltage: 2.7V to 6.0V - Package: DIP-52S - Evaluation Tools: LC65999 (evaluation chip) + EVA800/850-TB6S1XX/2XX/3XX/4XX LC65PG20X/40X (piggyback) System Block Diagram AVE g Ay" © Alo Ea; Cpr x > PKo~s PA2/A02 ~ PAI/AD3/INTT Cofoonr [> Plows PB0/AD4 /ORTS | voronee | PBI/ADS /DACT (0 PORT B PB2/AD6 /SOR hy V0 BUS a ‘STAND BY CONTROLLER ITEAVAG TasER 4096% 8 { j Pco fraarr ‘ 8 TIME BASE stack} 1— Kn REGISTER WATCH DOG PDO c Ginter °°) Safemnefy| US : P03 ‘SYSTEM BUS KOSKY je SYSTEM CLOCK PFQ/SI bee eee SHY 170 Pont F KY oS: ius UE ee ac: H PF 3 /INTO S: FOS ‘ONTROLLERY OSC! : 8 BIT SERIAL ey {i 4.19MHz OSC 0 0SC2 ox) PA3/AD/INTT 0 pea Gg OG Of 8 —orest ——o RES oo Em] om =i Ye eS © | ee. pad PMO~3 PNO~3. POD~3 PRO t y ° No, 3117-2/28

The development support tools for the LC65204A are as follows: (1) User's Manual [LC©65204A/404A User's Manual] (2) Development Tool Manual [EVA800/850-L C651XX/2XX/3XX/4XX Development Tool Manual] (3) Development Tools 3-1. Program development tools i. MS-DOS Host Computer System and Cross Assembler (note 1) ii, Cross Assembler --- MS-DOS-based Cross Assembler : LC65S.EXE 3-2. Program evaluation tools i, Evaluation Chip: LC65999 ii. Piggyback Microcomputer : LC65PG20X/40X iii, Emulator : EVA-800 main unit and EVA chip board, or EVA-850 malin unit and EVA chip board (note 2) Outline of the Development Support System <LC65S. EXE z Ss SB — J 7 (SS Emulator: EPROM EVA-800 or EVA-850 (2764, 27128 or their equivalent) —- cy Model/Function 1 eno setting switches ax Lessee // Sa ae — TAS oe Ong oS » << S EVA chip board: SS

5 EVA800/850-TB651XX/2XX/3XX/4XX

SS Piggyback Microcomputer: %) LC65PG20x/40x bin 2 7p Conversion board (T8528) Application product board (Note 1) MS-DOS: A trademark of Microsoft Corporation. (Note 2) The EVA-800 and EVA-850 are general names given to emulators. They are qualified with suffixes (A, B, ...) because the emulators are updated very often. So use the fatest version of the emulators by checking the suffixes carefully prior to program debug. No, 3117-3/28

Pao/ad0 [J 1 s2C] vp Pal/adl []2 51() Pro pazvaoz [] 3 so] P03 Pas/ap3/INTI CL) 4 49C] poz paosan4/daco CL] 5 48] Pov Pet/aps/DaAcT [6 47[] Poo Pp2/ap6/son [7 460) Pua Pp3/ao7/starT [] 8 450) pn2 avt []9 44(] ent av- Chto 430) pno Vss (]11 420] pm3 ose! [J12 410) pm2 osez []13 LC65204A ao) pm Voo []14 39) PMo Res [415 38[] PL3 x1 Che 37) PL2 x2 (7 36C) Pu Test [18 35) PLo Provsi [J19 34L) PK3 pFivso []20 30) pk2 pr2/S0K [23 320) ext PF3/INTO [_] 22 310] pxo eco [) 23 30] pos Por [)24 23[] poz poz []25 28[) Pol Po3 (26 27() Poo Package Dimensions : 3128 (unit: mm) 52 a 1 6 | i 0.25 a PVCU RHNWN ANGLE cu 1.78 0.48 1.05 SANYO : DIP52S No, 3117-4/28

Pin No.Of + a Output . Reset Unused Pin Name [Pins |!” Functional Description Driver Option Status | Handling [vss [ 1 [=| TEST LSI test pin, This pin should be con- Always con nected to the Vss pin during operation nected to the and has an internal pull-down resistor. Vss pin, RES System reset input. tor. [ave | 1 [—] Reference voltage input pin for A/D Always con- conversion nected to the Os Trgur scl a System main clock generation, fexters Bin Spam and connect thecextetnel Seek OSC2 | [| Generator to fRe"88b} pin. Feed-back | fesistor_is internally provided, ; XI Oscillation circuit component pins for Xt: connected system sud clock generation, If external to the VDD clock input is used, leave the X2 pin pin. ‘open and connect ‘the external clock x2: left XD generator to the X1 pin. If not used, OPEN the X2 pin open and connect the X1 pin . to the Vop pin, Feed-back resistor and limiting tesistor_ internally provided. down resistor the Vo pin. PADto3 1/0 |Input/output port pins PAO to PAS Normal-volt- | Each port pin | Output Should be set - Port function age withstand| can be set to | transistor | to the open 4-vit data input (IP instruction) Medium-level | output type | OFF (H- | drain output 4-bit data output (OP instruction) current type | (1) or (2): level out- | type and then J-bit input decide operation (BP/BNP (1) Open put) connected to instruction) Drain the VSS pin. I-bit output set_and reset opera- (oD) tions (SPB and RPB instructions) output ~ Low-level threshold input (2) Puil-up ~ Ail these four port pins can be used resistor for two or more purposes: output PAO/ADO: Also used as AD converter input pin ADO PAI/ADI: Also used as AD converter input pin ADI PA2/AD2: Also used as AD converter input pin AD2 PA3/ADS/INTT: Also used as AD converter input pin AD3 and as external interrupt signal input pin TNTT PB0to3 4 1/0 | input/output port pins PBO to PB3 Same as PAO | Same es PAO |SameasPA0| Same as PAO = These port pins have the same function] to PA3 to PA3 to PAS to PA3, as port pins PAO to PA3. + Low-level threshold Input = All these four port pins can be used for two or_more purposes: PBO/AD4/DACO : Also used as AD converter input pin AD4 and 6-bit PWM output pin DATO PB1/AD5/DACT: Also used as AD converter input pin ADS and 8-/14-bit PWM output pin ACI PB2/AD6/SOR: Also used as AD converter input pin AD6 and square waveform signal output pin SOR. PBI/AD7/START: Also used as AD converter input pin A07 and standby contro! Input pin START To be continued on the next page. No, 3117-5/28

Continued from the preceding page. Pin No,Of A aon Output . Reset | Unused Pin i VO Functional Di Name | Pins ‘al Description Driver Option | status | Handling PCO to3 1/O | Input/output port pins PCO to PC3 Vpp-45 The output |The output |Set the - Same as port pins PAO to PAS In High-voltage type of each Ttevel at | pin(s) to the function. withstond [PO Pl 30 | the reset | open drain = High-level threshold input Medium cur- | either (1) or | can be set | output type + The output level of these four port| rent type (2) by option | to 'H' or | by option pins can be set to 'H! or 'L' by data. "L' by | data and then option date at the same time. (1 Qpen Drain! option data,| connect it - FLT segment drive output (2) Pulldown (or them) to Fesistor output the Vss pin Output level through the specification resistance of eee tne In addition, four port be sure to pins can be set the port simultaneously output level Set, to TH or at the reset at the reset by tol option data. PDOto3 1/0 | !Mput/output port pins PDO to POS ‘Same as port | Same as port |Same as port| Same as port - Same as port pins PAO to PA3 in| pins PCO to | pins PCO to |pins PCO to| pins PCO to _ function and characteristic. PCa PCa Pc3 PC3 PFOto3 1/O |Input/output port pins PFO to PF3 PFO to PF2 (1) Output Same as port] Set the - Same as port pins PAO to PA3 in| Open Drain type pins PAO to} pin{s) to the function. (OD) output option: |PA3 open drain = Schmitt input type: With- Same as output type - All these four port pins can be used | stand voltage port pins by option for two purposes: +15V PAO to date and then PFO/St: Pull-up out- PAa. connect it Also used as 8-bit serial input pin] put type: | (2) The AC {or them) to Si. Normat-volt- zero the Vss pin. PFI/SO: age withstand cross Also used as 8-bit serial output pin | pF3 detection SO,__ Normal-volt- circuit PF2/SCK : age withstand can be Also used as 6-bit serial clock pin | Medium cur- internally 5CK cent type added to PF3/INTO: the INTO Also used as external interrupt pin by request input INTO. The AC zero ‘option cross detection circuit can be data. internally added to this pin by option data (AC zero cross interrupt function available). PK0to3 Output port pins PKO to PK3 Same as port | The output | output Set the = Port functions pins PCO to | {PP Of each | transistor | pin(s) to the 4-bit data output {OP Instruction) Pc3 Be et POP OFF ('L'| open drain I-bit set and reset operation either (1) or | level out- | output type (SPB and RPB Instructions) (2). put) by option 1-bit decide operation (1) Open date end then (BP and BNP Instructions) Drain (OD)) connect it - FLT segment drive output output {or them) to (2) Pull-down the VOD pin resistor output ‘Output port pins Pi Pi Vpo-45V Same as port |Same as port| Same as port PLOto3 oO eeine nae eet pies PRO te PKS in |Hlgh-voltage | pins PKO to [pins PKO tol pine PKO to function. withstand PK3 PK3 PK3 = FLT digit drive output page current, PMO tod ‘Output port pins PMO to PM3, Same as port | Same as port |Same as port| Same as port = Same as port pins PLO to PL3 in| pins PLO to | pins PKO to |pins PKO tol pins PKO to functlon_and characteristic PL3 PK3 PK3 PKS PNOto3 Output port pins PNO to PN3. ‘Same as port | Same as port [Same as port| Same as port = Same as port pins PLO to PL3 in| pins PLO to | pins PKO to |pins PKO to| pins PKO to function and characteristic PLS Pa PK3 PK3 POOto3 ‘Output port pins POO to PO3. Same as port | Same as port [Same as port! Same as port = Same as port pins PLO to PL3 in| pins PLO to | pins PKO to [pins PKO to] pins PKO to tunction and characteristic PL3 PK3 PKS PK3 Output port pin PPO Same as port | Same as port |Same as port] Same as port = Same as port pins PLO to PL3 except} pins PLO to | pins PKO to |pins PKO to] pins PKO to for 1-bit configuration. PL3 PK3 PKa PKS No, 3117-6/28

1) Oscillation circuit options The main clock oscillation circuit and the sub clock oscillation circuit can be selected from the following optional circuits: Option name Optional oscillation circuit Main clock oscillation circuit Two-pin CF oscillation circuit Two-pin X'tal (crystal) oscillation circuit External clock input Sub clock oscillation circuit Two-pin X'tal oscillation circuit 2) Output level option This option is provided to set the output level of input/output ports C and D to either 'H’ or 'L' at the reset. Conditions 1. 'H' level output at the reset Simultaneous 4-bit setting (input/output ports C and D) 2. 'L' level output at the reset | Simultaneous 4-bit setting (input/output ports C and D) 3. Watchdog reset option The watchdog reset option is used to select the watchdog reset function. Note that the watchdog reset function utilizes the time base timer. 1, Watchdog reset function select An additional program routine is required in order for the time base interrupt request flag to be reset at a certain interval. This prevents the watchdog reset circuit from being activated in cases but a program upset. 2. Watchdog reset function non-select [—— 4) AC zero cross detection input circuit option The AC zero cross detection input circuit option is used to permit the INTO pin to internally have an AC zero cross detection circuit or Schmitt input circuit. PF3/INTO [circuit ob bo [AC zero cross eetection circuit Option name tree Te Te No, 3117-7/28

5) Normal-voltage withstand/Medium-voltage withstand port output type option This user option is used to allow the output circuit type of each normal-voltage withstand and medium- voltage input/output port pin to be set to either the open drain output or the pull-up resistor output (bit-by-bit setting only). Option name Circuit type Applied ports Open Drain (OD) Ports A, B and F output IE Pull-up resistor Ports A, B and F output o > 6) High-voltage withstand port output type option This user option is used to allow the output circuit type of each high-voltage input/output and high- voltage output port pin to either the open drain output or the pull-down resistor output (bit-by-bit setting only). Open Drain (OD) Ports C and D output I} ae Ports K, L, M, N, O and P oe Pull-down resistor Ports C and D output IE nos Ty Ports K, L, M, N, O and P RO No. 3117-8/28

Major LC65204A Characteristics Applied Pins mi . P; L Ul Symbol VoolV} BREE=™ [veo mo [veo | | a iow vex [vail [ SCH [at saontiatn |__| Uo te voreoe oan | RES. OSC1 and XI: — vile) TEST,RES,OSC1 — [OSC1 and x1: at 0.3toVo0 +0.3 xl input wer [ave oo 7 ce rr Er ws) [| Weo=#6tvo0+0 3 Output Voltage | Voll) OSC2,x2 At self-oscillation |__| Up to the voltage produced _| v Ports K, L, M, N, O = f “0 Feats ae forever input/output viol) Port pins F2 to FO | At open drain —0.3to+15 Voltage output output Vou _[e eae [i Voo—BeaVoor3 Viola) Ports A and B —0.3t0Vo0+0.3 port pin F3 a ea =2o+10 [or(2) [endpor’ pa po” | | ioe [rors wee | || Tt Average Out [Pons A, 8 and F | A q Toate) [f= 80000 | tt ee Eioa(@ [Pen Foo a = Bro [Biowia” [Pons c, 0 a | a issipation Hrempereture (Tope [| PT =wot | lfemperstwre [Tse] TT = 8610+ 125 2, Allowable Operating Range at Ta = -30°C to +70°C, Vss = OV Applied Pins Pxameter | Symte' | and Remarks Vootv [win [Tye T wex | Sil Vote veel) Tevecd | fy Supply Voltage /| (including a Toye < 674s standby mode) | Vopl2) | Voo 1.84uss 6.0 Toyo < 624s | oy Voo(3) | Voo 29.4us< 6.0 Toye <67us Voold) | Voo igtion © stop 27 32kHz OSC oscil- ation © scuve Memory backed-up Full standby ae Voltage mode) To be continued on the next page. No, 3117-9/28

Electrical Characteristics at Ta = -30 © to +70 C, Vss = OV i Parameter | Symbol | APplied Pins ! ; Input ‘H'-tevel | In4(1) OD type port pins | Output Neh (N 2.7t06.0 +5.0 Current F2 to FO (transistor) ‘OFF. including Neh Tr. OFF leakage current). Vine+13.5V | OD t; ts Aand | Output Neh (N : . He) Brats OB type ert | channel) Tre 2706.0 +10 pin F3 (including | (transistor) OFF multi-functional” | {Including Neh Tr. port pins INTO, OFF leakage uA INTT and START) current). Vin=Vpp (Note 1) [mor [RES |Vin=voo [2 me6.0[ || [ime [OScr.xt _[Vin=voo [2 706.0 | + vee | | ” “ DP) Vin © Voo Input ‘L'-tevet I) OD type ports A,B | Output NchTr. OFF. | 2.7t06.0 Current and F (including Vin = Vss multi-functional port pins INTO, uA INTT and START) (Note 1) he (2) PU type ports Output Noh Tr. OFF. | 2.7t06.0 A, Band F Vin = Vss nctiona pins INTO, mA and START) (Note 1) uta) [osei. x1 2706.0[ =f | WS} 0 type ports Cana | Guteue ven? 2.7t06.0 uh 1 {transistor ‘OFF including Pch Tr, OFF leakage current), Vout = Vpp - 40v —— Output ‘Hitevel | VoH(1) | PU type ports A,B | loH= 504A, 4.5t06.0 | Voo—1.2 Voltage and Voxl2) lon = 104A 3.0108.0 |voo—0.5 I | an Ports L, M, Nand “5tob.0 2. “e [Sra eA | aie aa | | Ports L, M, Nand =— 1 — Vou) lon=—1.0mA | .0t06.0 |Voo—1.0 | loHs of other Vv ports <-ImA Vonté) lon bma | 4.5106.0 [Voon1.8 L Von(6) | Ports C, D and K | IoH=—1.0MA 3.0t06.0 |Voo—1.0 JoHs of other H ports <-ImA Voltage Vo(2) | Ports A, B and F | Iqu=1.0mA 3.0t06.0 1oLs of other Vv ports < tmA To be continued on the next page. No, 3117-11/28

Continued from the preceding page. Electrical Characteristics at Ta = -30°C to +70 °C, Vss = OV ied Pi Parameter | Symbol | Applied Pins and Remarks vootv) | Min | Typ | Max | unit Output 'L'-tevet [Output Pch (P channel) current produced by and PD type port’ | Vout=3.0V utl-down Fesistors) __|pin Po Vp=—36V OD type ts K, L, [Output Poh (P channel)| Qutput OFF Leakage] loff(t) | Hund Oy andOO |r. (transistor) OFF | 9-0%06-0 30] uA type port pin PO | Vout=Voo Output Ph (P channel) = Toffl2) | O0;type ports KE. [Output Pon r cRanAeO/ 3. 0106.0] —a0 type port pin PO_| Vout=Voo—40V E Output Nch (N channel)| iIN= [rao Ranmor Ru RES wo of fm] = [Output Pch (P channel) Pull-down Resistor oR and Go” [Tr Iteansistor) OFF 48 108 200 and PO typeport’ | Vout=3.0V kQ pin PO Vp=—36V Hysteresis Voltage | Vuvs Dine INTO TRC 3.0to6.0 0.1Vop RES and START v (Note 1) Input Clock | Texcy(1) | SCK See Figure 7. 4.0t06.0 Cycle Qutput Clock | Tcxev(2) | SCK See Figure 7. 4.0to6.0 |2.0x vere Teye Input Clock = | Tcku(1) | SCK See Figure 7. 4.0t06.0 ‘Ui-tevel Pulse Width (Note §) 8 | output ctock | Tcxi(2) | SCK See Figure 7. 4.0t06.0) Tove 5 | 'L'- level = | Pulse Width 3 = Input Ciock Tekk(1) | SCK See Figure 7. 4.0t06.0 0.3 ‘H!'-level Pulse Width (Note 5) us Qutput Clock | TcKH(2) | SCK See Figure 7. 4.0106.0 Teye 'H'-level Pulse Width Tick With reference to the Data Setup c Ss! rising edge of the SCK} 4.0t06-0 signal. See Fig. 7. Time D With reference to_the 3 Qutput Delay | TcKo so falling edge of the SCK 4.0t06.0 g signal. ° External resistance: 1 = kohm, External capaci 4 tance: SOpF. See Fig. 3 2 To be continued on the next page. No, 3117-12/28

Continued from the preceding page. Electrical Characteristics at Ta = -30°C to +70 °C, Vss = OV Applied Pins i Parameter | Symbol | 33 Remarks woot) | Min [Typ [Max] Unit Input Fain Apply to the case |(1) At open drain 1000 Frequency where the AC zero output He g cross detection (2) At self-bias ON g circuit has been | (3) See Fig.8. 5 the PFS/NTOpin dy [THfa,{a)__Coupt a 2 u Opin by } (1),(2), - § | input Voltese | Vzww the user option | (1x23) | Covel 2) op 5 data. WF 6 1),2),(3) 60H +1 2 | Detection — | vza CeO goat 00) av 3 input § input Current | tz 0.00 4.5t06.0 +40

3 Vin=Voo_

3 lez 0,0,

3 Vin=Vss

& | Threshola Vt AcM 0,%@ 0.3Voo 0.7V00 ° Voltage N [istever Input | Vik ACL 0,@,® VT*AcM| Vv Q | Threshold 0.2 < | voltage Comparison | Vcecon | ADDtCAD? AV+=Voo +1 £2) og g Accuracy AV-=Vss © [Threshota | VtHcon AV- AV+ 5 | voltage s 5 = + ne jo AV Avt} v £8 | Reference | ay+ AV+ AV- Voo 2 Input AV 5.0 Be [voter sio% [| Vss| [ave] $£ [conversion | Toc Cpmoarator speed WW 96 be Time At 12 x Toye. (Teve= (Teve= 5s 0.92us) Bus) 6O BS ac Comparator speed a 92 ~ . = 83 At 23 x Tove. (Tove= (Teyo= oe 0.92us) 4us) [Reston | fi dC |Aceuesy | | FAV += V0 ne es ees @ | Zero Scale Ezs AV-=Vss +4 B | Error LSB Q | Full Scate iz, +1 € Conversion Tcao AO speed 1/1, 24 208 5 | Time At 26 x TCYG (Tere= (Tevc= g 0.92us) Bus)| 6 AD speed 1/2. 47 204 < at $1 x Toye. 5.0 | (Tevc= (Teve= 8 | Input & | Reference +, AV- += 6 300 & [Reference | iar AV+, AV AV#=Voo } HA 5 | Range AV-=Vss § | Analog Input ADOtoAD?7 AV- Av+ “Analog Port Port pins ADO to | Including output 1 Q | input ‘Current £7 fultn the ae Orr Teakage cur the input/output | Temes uh multi-functional Vain=Voo t te types ENS es) a To be continued on the next page. No, 3117-13/28

Continued from the preceding page. Electrical Characteristics at Ta = -30 to +70 C, Vss = OV Applied Pins Parameter Symbot ‘ " and Remarks Vootv) |_Min [Tye [ Max_| unit Dissipated Current | IDpor(t) | Vop 4.19MH2 x 1/12 4.5t06.0 3 in Normal Operation! High-speed opera- Mode (Note 4) tlon mode (TCYC = 0,95 us). And at sub clock oscil- lation Tooor(2) | Voo 4.19MHz x 172: 4.5106.0 2 High-speed opera- tlon mode (TCYC = 1,9 microseconds). And at 32kH2 sub clock oscillation mA Ipoor(3)_ | Voo 4.19MHz2 x 1/32: 3.0 0.3 Low- speed opera- tion mode (Toc = 30.5 microseconds), And at 32kHz sub clock oscillation 'ppor{4)_ | Voo ‘32kHz: Low-speed 2.7 ‘operation mode MTeye=61 us). 4.19MHz main . clock = stop Dissipated Current | lopst(1) | Vop | 4.19MHz main clock 120 in Standby Opera- = stop. 32kHz sub tion Mode (Note 4) clock oscillation (HALT mode) Inost(2)_ | Voo 2.7 |‘) 4 HA Dissipated current | lppst(3) | Voo Full standby mode in Full standby (HOLD mode) operation mode (Note 4) loost(4) | Voo Full standby mode (HOLD mode) Oscillation] foscx osct See Fig. 1. 3.0to6.0 & |_SlFreauency osce (Note 2) Mie = |g = | BE [Oscitlati (Note 3) 8 58 Seoul | | hes |

3 Period

3 Oscillation | fosccr See Fig. 1. 4.08 ie §|Frequency (Note 2) MHz 8223 jos se eeitlation [tices See Fig. 3. |< 515 8] Stabilizing EE PO} Period ms S| g [Frequency (Note 3) 2 1s ke Fs 5 |6 3 | = JOscillation See Fig. 4. § 5] & |stevitizing Sz] & [Period (Note 3) For oscillation constants, refer to Tables 1 and 2. {Note 4) The ‘dissipated current' does not include the current flowing into the 1/O port transistors, pull- up/pull-down resistors. (Note 5) When the internal clock is used, although according to the specifications TCKL(2) and TCKH(2)(=TCYC) are output from the SCK pin with the minimum clock width, there are cases where their clock widths become shorter than TCYC due to the value of the pull-up resistor. However, it is necessary to select a value for the pull-up resistor so that even at the minimum, these clock widths exceed the 0.3 us stipulated for TCKL(1) and TCKH(1). No, 3117-14/28

Table 1. Guaranteed constants for Table 2. Guaranteed constants for

(Note) If power stabilizing time is zero, the reset time will be Bee 10ms to 100ms with the Cres = RES O.1uF. If the power stabilizing period Cres(=0.1 uF) is rather long, the Cres value should be set properly so that the reset time period can be longer than the main clock oscillation stabilizing period. Fig. 6, Reset Circuit Von 1kQ test point ia 50pF Serial output load tency ; | 0.80 Voo (input) x 0.2000 (input) X] voo-tv (output) 0.5V (output) text : . { Y 0.80 Voo L\\ 0.20Voo teKo J Voo-1¥ so (| 0.5V Fig. 7 Serial clock timing No. 3117-16/28

+ PF3/INTO Ac tout — FT [> ete sbnaratin eu ™ =} —> ACZ interrt c oY b ‘ Option <AC zero cross detection> Van AC input Van Vza Rising edge detection and output The falling point does not correspond exactly to the AC zero-crossing point. <AC zero cross timing> Rising edge detection and output ef Synchronization pulse generation circuit Synchronization delay = Otol + Tey Fig. 8 AC zero cross detection No, 3117-17/28

LC65204A Instruction Set (by Function) Convention AC: ACcumulator PC: Program Counter Act + ACcumulator bit t STACK : STACK register CF: Carry Flag DAt bea, cTL + ConTroL register ble : Working register MSTEN : MaSTerinterrupt ENable fiag 2F + Zero Flag DP: : Data Pointer (1 + Indicates the content. E 1 E register +: Transfer operation and its direction brn: Flag bit n + Aadition M : Memory 7 + Subtraction M (DP): Memory address specified by OP ~ 2 And P (OP) : input/output port specified by ODPL v + Or GP (OP) : Pseudo port specified by DP ” : Exclusive Or Moamonic Operations operating Deseription By gle Town ac ft oofocooliifac~o [ree acto zr fe pee ewe ce ofoc es |ififermofemecree fer Tt afsre [secre foo ort [fers ewer Pr TT §[ewa [comotemen ac [vt to fe ory [i fi facetmty | iwerts ov ac ow ze linc [increment ac fo oo o fv to fi [i [ac macs +1 [weemens acer far cr [TT : Rorave AC lett ‘ACO =ICFHAGRo i 7 G[tae [tonter aco e foooolootr [if [entac [remnacwee, TT Elen [erernae a wine foo oo [ro 1 ffi fsa [ exchonos the contents of AG onde, [| g [iw Pincremens mw foo oft tt oft [t futon caiorntt [wcrements wor) ty. zr er [| oem Joecremene Mm foo roy tii [i[miori~Caiori—1 [decrements wor) oy. [ze cr [| 5, (OP) bit Wied by BIB. i Resets the MIDP) bit pecitioa TWOP) in inwry nd ets = Tate AO ond MOP) with GF In Dinar Decimal agiust AC y -ogically excluslve-Ore AC end MIOP), : Exclusive of M (AC Ao (aol (M(OP)) | god wat fa Tales ectave wm In rs 1 Logicetly Ands AC and M{OP) and sete é Toojesliy Ors AG end MIOP) end ete : Compare AC with M GMTOPII-+(a0)+1 femte GF ard BF corny to te Fy fevstt. H [-conparon coat] CF | 2F] (lor) Siac | Oo To} [oop =racy [+ [1 | oator <iac) [1 [oJ 1 date ompare with 1 TyTaTiTq FIACI +4 | Compares AC with Immediste date | ZF CF ene Tmesnie ane [Os 00 SUT ACES | anata o rote CF ard BF tectraing tow romate [Comparison vesuit [ CF [ 2F | [att te>iaci{_o [0 _) [Taig ty ig Stacy TT Tar ttocway 1 To) Compe DP win [O01 0 TOPAI¥ 131211 10 | Compares OFL with Immediate Gate CLE 0918 inmediate dare o1or Ulaltloe Load AC with ~ ‘Lond Immadiole data Ialailo Into AC, [esos [isda [+ se ofsiette[s[ [acmstaane [tetinnemse te panei sefay fev | [s_ |store ac rom [oo 0 0 foo» os [1 | mior)~tacd Store AC to MOF), [ [teers ac trom moo ro foo ot |r ft faor tutors [toes wor) ino Ac. [eT

3 Exchange AC with M (a0)==04(0P)) MiBiy, "then Nopicaly esctualve-Ora eg aoc

z then modity. OP DPW (OPA {Derglona immediate dts Ona ana crate 2 wih immediate date O MaMiMe | flealy fntgces OPH with Une logical saga re one $ Exchange AC with M 0000 Exchanges the contents of AC end ee acter | 3 eens wor). rege conet Exchange AC wihM (ac) =(M(0P)) Exchangoe the contents of AC and 3 then increment OPL OA tO) + MOP) end then Ineromants FL, by te Enchonge AC wiih (ao)=0a(0P)) Exchanges the contents of AC and thar aman oey oP,~(0P.)—1 MOP) a then decrements OFL by 1 Read table dats Irom! AC.E-ROM Taplaces the PG You-ordor 8 bits wlth Evand AG, and than lovds the contents rogram ROM (PCH.E.ACI | of the ROM address specified by the naw PG. contents ito’ AC ond 2. No, 3117-18/28

i § Operating Description

3 JOr04050z {03 02 04 0» || &

Laxd OP win Boa we Deno Tone igo inmate ate ign OP, with immediate OPLmiatztito Ig Into OP} and OPL, respectively. ene vespacvty UH ania [cond OP with Toe tmmaaate ote 19 Ino smmediale date DP He [ino Tinerementome [vt ro [tt voit fon worrtr | meronents ory content byw [ze [| FHoe0 [overemenon fr ro firs [r[r}on =tonr—1 | ovcrenons onc conent oy fer |__| [rat [reenter acto om [Pry T foe tf [efor mtach | Yowton acento wor | fd pg SR a OD OS [Tresiee onL content wo ac dae par |eaweAcemors [oor ofo-o 1 [|i [uazienn [Burm waren zee PT 5 xchany wa Onn ‘Exchanges the contents of AC end & S Enchange AC wih Or = specitied working register In re- 3 working cegater bar |1 1 10 FO GTO 0 4AC) 53(bAO) Gister bank b (already selected). i 1110 fo 1!00 (AC) 5 (bA1) Note that bite t1 and to era ured to 2 1110f1 of00 {Ac} (bA2) ‘spoclty working repiatere BAO, DAT, g 111 ofi tio o FAC} 5 (bA3) DAZ end DAS. i Exaunge OP wih ‘ Tenis Seainp rages teeae é working tegaier bHa 11810 0 (oer) =(bHO) Rate eee bendy ates 2 tinfo o (OP (0H) working rogitare BHO and Hie H)ets,_[Excuanoe BF son a. tpectlga woking reqner In roe & XxLO working regater bla, of0t0 0 (OP. =(bLO) gister bank b (elready selected). e{ xt ohyjo 0 [t|y froma sik | ReSgiae 8? FS Sot Register RBF = 1110 of SB Sete the bank vaive given by the $8 g Bank Address. Instruction Ia ‘the ‘register Bank Vmedee Set B96s0i80 se to g ecliy the "Hoo. 2 83 Bz Bs B bFn-0 Resets » specified flag In register Flege ace H 982 Bs Bo . Bert's Caeeay Saclay Ne tet spd ins Rinse S90 EaaGot@s Webs ts Seer F remy Set ie Be, i ina i Bettis, 3 iad Te, Tut wal Dome ww the wm JO TO] PaPoral? [2 | PE — POW we —lieiee ewan. ne fo Oe sR reer road > PgPaPalPaPaPs (ivertes Poi) | secitog by Ft! Tor Inverted faethe 1PaPsPa|PoPaPiPo tvs Pon) | scinedansataPaPoboraneara aoa PuPsPaPiPo eur ier TEA [pump w the currant Tacs ear ae 8 ia FE TREE ae tate sevncanes's SEEPS Pree fe i tan Sena. Bl czP ada [Cait subroutine en tne [P3?2P1 Po ‘STAOK=(PO)+1 {alla « subroutine to pape 0 of bank reo pope Poin, POiwe= 0 i POsie2*-PaP2 Pt Po £ Call tubroutine vn the 1 PuPePe STAGK=(PO)42 | Calla 0 msbroutine in bank O. two bank arse eo) |” | Peiue00Pi9PsPsP> | PaPsPaPaP2PiPo E [x [Ren tom amouwefo v1 0 foo ro [i [remistace | Raggy © aan Toure Wan FRET [ eyar Return {rom wtesupt PC {STACK} Returns to main routine from an in | 2F CF ee el aoa” ann i an Polo rea Branch on AC bit 00 tilo PCrmo — Pr PaPs Pa | padre Propreny oranch to & see] tied re enon si Saeabae Papsetos | aeites Se OE beat Ete Lae een et PoE Redie aut Ben BB po Poeaciod Sn spe ca ed ete sooeily XC"Site BWAI addi Branch on no AC bu JOO 1 1/0 Otito PCrwo~ PrP EP EPa | Makes proorem branch to # epocified fe rere preepsre|popam Po Papipite LNs Eyes w ACL=O resses pid snother fests ahs ata | ieitaraqh ra'uced to taal BMt addi | Branch on M bil O1TT1O ttite PCr00— Pr PaPsPa | Makes orogram branch Be f, pel 4 [Fre mnemonic wii ee orieies | RRSOECE Ms | ETE se (mor.tytad=1 | lePunad torepectty ade hie fst peiohie as eae Brancy on no Mbn [0011/0 1tito PCI wom PrPePs Pa | mace pjonam branch to f wpecliiad brs marron, gt = PrPaPsPal Pa Pri Po mor ren fi me Le AES ble, srab 1 (mor.t 1t1)=0 | bined totvaselty 'adareisel” fi ROA Y align gl 6 ads BP1 ada | Branch on Port bit 1 Otito PCr P7P4PsPe enn pape pete tt baoel: [ie mramonie_ =u Psereiro pupapie | abe Meee mnt gel baeersea wP(OPceneiet —_ | tnaosatecee Tons ino fase otis COP (OR, trtold— 1 | Krrnekyfaeale"tnd utes acy BNPr ad0"| Branch on no Port bt |0.01 1 1t Otrto POr0*-PrPaPsPa Baars Toe pane pate te [ime mremonse ws Pr Po Ps Pal Po a Pi Po PaP:PiPe irs Hones Pathe al rT aero wetoncivons, | Beale Meee ears COP(OP,t1t0))—0 | ERrasatercaltito ved to telly No. 3117-19/28

070g 0304 03020) Do! Badd [Branch on OF OoTtfiite Pormo=PrPePsPe | BaheuPee Re tin nee PRE ae PrPeraealPsrarire PipIPIPs fees 1 ore’ Beesertey Maes Sat 1 ‘BNO addr | Branch onno OF oottliiit POrwo-PyP PsP | MEER PIER Brae et : yore Bessy po By Wa oc Slez asa [Branch on ZF Oriiiitto Porwo-PyPePsPq | Maken prpocem branch to.» ppegitleg i ae Bree rie th Gfpnzecw [Branch on no 2F oottlrive PCreo—P)PePsPy | Makes Proogm eae rea 5 waee ebanesh ah eee Bare ENE TER I aT PrPaPaPal PaPaP Pa Diotetes | frames sf Ren eta eae tan oes aids Grae chet date eee SRT ee Sant EE ot Bas Abel arti Pos GAZ addr] Branch on vo tag ox [1 0 0 1[mgnanind 2[2| Porme—PrPePaPe | RUMHIRE mite por Nt Tre nsenenis PrPsPsPal PaP EP LPG PxPEPiPD eters ay SRE ae " OFrmo Baath eleoanieyios es Sevale oI Ei oda atl laid Input port to | or Inpute date to AC tras 1 port | ZF § Quipur AC 10 port PCOPL) or (AC) | Outoute date to the port PIDPL) oF : ‘GP(OP) paeudo poet GPLOP) from AC. i Too of 01 Bred 1] 2] Promcesy 1 | Hany PRE aT at am eA — Fi wosoreey | WAL Ran are OLE Leet Saha ae ana g Sas oSe, i Elpee or [Rese pov oe o7 b6d 7] 2] PORLen—0 | Reise meme mcrian ee [P| keseig cr opie oreo) | RePh sedate’ ob aL ES See sera esate nol et Spall SCTL bit } Set control register ootrojr1100 CTL, €3B2B1 Bo —1 | Sets o echt ies, Hat the, ‘contro! #2 vs 10.0 8/8,808,04 | | a eps OG ie Se wore ane Pa eae ROTC ts Reon’ cova) wesw POO VO} 1 oo] afa| CH Grebe 0 | Rew merece we aman [oF | ¥2 rs 190 1/598:8.84 | | Hae ES es Sane MSTEN~0 B3dso By "Waed To apecity the Ca CY TI W two oF ore LT or GLA Tnaostons ave exeeuted conInooey, Gay ha Hrs iatuclon wl be executed normally. However, the Instructions following the first will be handled @s the NOP Instruc- tone ‘2; BH0#e160 = oo008 to 10008 No, 3117-20/28

On the LC65204A user mask option code specification Overview The user mask option data for the LC65204A should be stored to an EPROM as well as program code and then sent to Sanyo. With the Sanyo cross assembler for the LC65204A, the user is allowed to specify option codes in the conversation mode and the user option data can be set in an EPROM properly with ease. If the Sanyo cross assembler is not used, the option code should be specified in the following manner (this corresponds to the format of the cross assembler): EPROM address map 0000H Program code area (4Kbytes) OFFFH 1000H | [oT 1003H [ 1004H [| 1005H [Od es | 1008H xy . }909H (WG Option code area 1008H N 100CH [OU . 100DH [ 100EH | TOOFH fo 1010H [ 1011H [oT N indicate the areas that 1FFFH \\ RX ss should be filled with "00", No. 3117-21/28

Contents of User option codes 2 20 voooh [TT] fof TT) + Main clock oscillation option

00 Two-pin CF oscillation

Q1 Two-pin X'tal oscillation

10 No assigned (unselectable)

11 External clock

+ Sub clock oscillation option 00 Two-pin X'ta! oscillation

01 Unused

" } Not assigned(unselectable) + Port C output level at the initial reset 0 ‘L' level output 1 'H! level output + Port D output level at the initial reset 0 'L' level output 1 'H! level output + Watchdog timer reset function

0 Not selected

1 Selected . + AC zero cross input function

0 INTO input mode

1 AC zero cross input mode

voorH [o]ofofo[o[o]o]o} oo These bits should always be set to '0'. a 20 voozH [PAs | Paz | Pat | PAO | » Port A output type

00 Nch open drain output

01 Pull-up MOS output

1) } No assigned (unselectable) er 20 1003H [P83 | P62 | PBI | PAO | + Port B output type . " } Not assigned (unselectable) To be continued on the next page. No, 3117-22/28

Continued from the preceding page. 2 20 . 100aH + Port C output type

00 Pch open drain output

01 Not assigned (unselectable)

10 Pull-down resistor output

11 Not assigned (unselectable)

voosn [Pos] Poe FOr | PbO] + Port D output type ‘oosH [ofofofofofo]a]o} — ore These bits should always be set to ‘0’, 2 20 voor [PFS] PFe[ PA | FO] + Port F output type 1° } Not assigned (unselectable) (Note) Be sure to set the output type of the PF3 port pin to OD if the AC zero cross input mode has been selected with the AC zero cross 1oosH 2 2 input option. 5, elolelef[ofofo]o} 100BH These bits should always be set to ‘0’. 2? 20 vocn [PRET PRET PRT EO] + Port K output type

09 Pech open drain output

To be continued on the next page. No, 3117-23/28

Continued from the preceding page. 27 20 10004 » Port L output type

00 Pech open drain output

Ot Not assigned (unselectable) + Port M output type 00 ch open drain output + Port N output type toroH [Po3| Poe | PO | POO | + Port O output type rors [of of ofofofo] po} a + Port P output type These bits should 00 Pch open drain output always be set to '0'. 01 Not assigned (unselectable) 11 “Not assigned (unselectable) No. 3117-24/28

Programming Considerations + The user application programs for the LC65204A should be developed with the following considerations in mind. a System clock | The LC65204A allows the user to select the desired system clock + The main clock oscillation is always mode source from the following four by software, required at the system start-up. (1) Main clock 1/1 mode (Teyc = 0.95us) + If your application uses the sub clock, (2) Main clock 1/2 mode {Teyc = 1.90us) the clock should be selected. (3) Main clock 1/32 mode (Tcyc = 30,.6us) (4) Sub clock mode (Tcyc = 6tus) (Note) Main clock = 4,19MHz and Sub clock = 32,768kKHz System clock | The desired system clock mode can be selected by writing data to + When the current system clock mode needs switching the clock mode flag (CMF: 2 bits) of the system clock control to be changed, the user should confirm fegister as shown below: that the main clock oscillation has become stabilized or that the MCSTP flag has been set to '0' in the external clock [ 0 [Main clock 1/32 mode (at the reset) | input_mode, § [1_[Main clock 1/1 mode id + The current system clock mode will be 3 [2 |Main clock 1/2 mode switched to the desired mode in 64 cycles 5 L_3_[Sub clock mode (64/#MOSC, Max.) after the CMF flag is a set properly. If the user wants the 3 L.C65204A to enter a standby mode after 3 the system clock switching, the above switching time perlod should be kept in § mind, That Is, the user should execute ra the HALT instruction after the switching é time elapses. Main clock The main clock oscillation can be controlled (stop and start) by + Be sure not to set the MCSTP to 'I' if contro! writing data to the MCSTP flag of the system clock contro! ‘one of the main clock mode has been used (oscillation Fegister as shown below: as the system clock, stop/start) « If the MCSTP is set to "I, it should be confirmed that the sub clock is already [0 Start (at the reset) | specitied and the switching time above [OT [stop mentioned Is over, + If one of the main clock modes is started from the main clock 'stop' mode, it should be confirmed that the MCSTP is set to '0' and the main clock oscillation stabilizing time period (tMxS or TMCFS) is over. HALT mode | <Start> + If the HALT mode needs to be released start/release | The HALT mode will be started if the HALT instruction is executed based on the PB3/START pin level ('H!) of with the SLPF flag of the standby control register set to ‘0’. the interrupt release signal, the WG2 or Note that the instruction will be processed as the NOP instruc- WG3 flag must be set prior to the execu- tion If one of the following conditions is satisfied. tion of the HALT instruction, <Release> (1) Reset (2) The PB3/START pin is set to 'H' with the WG2 = 1. & (3) The Interrupt release signal becomes active with the WG3 © 1. 3 (4) Time base overtiow Fi Z| HOLD mode | start» + Execute one NOP Instruction before issu- | start/release | The HOLD mode will be started if the HALT instruction is executed ing the HALT instruction to place the 4 with the SLPF = 1, microcomputer In the HOLD mode. + If the HOLD mode needs to be released based on the PES/START pin level, it | --- ----- nn ene ee nen eee eee ane ----| should be confirmed that the WGI flag is <Release> set and the active oscillation clock (1) Reset (either main clock x 1/128 or sub clock) (2) The PB3/START pin Is set to 'H’ with the WGI = 1, Is used as the time base source clock prior to the execution of the HALT in- struction, No. 3117-25/28

a Watchdog reset. The watchdog reset function uses the time base timer to allow + The routine must be included in the user {only in case when| program upset and watchdog reset. application program in order to reset the the optional TBF flag within a certain fixed time watchdog function (maximum time base timer overflow cycle). has been selected) In this case, be sure not to overlap the time base interrupt request signal timing with the TBF flag reset timing, + The active oscillation clock should be used as the time base clock source. + If the time base interrupt request flag (TBF) is set to 'I' prior to the HALT mode activation, the HALT mode will be released due to the time base overflow signal and at the same time the watchdog reset signal becomes active, In order to Prevent the watchdog reset at the HALT mode release, (1) reset the TBF im- mediately before executing the HALT instruction or (2) set the time base interrupt enable flag (TBEN) and the HALT release enable flag (WG3: release due to the interrupt) before executing the HALT instruction. Interrupt + Five flags are provided to contro! the five interrupt sources + No flag is reset after interrupt process- Enable fiag ‘on one-to-one basis. To enable a certain interrupt request, its ing terminates. In resetting a certain (control corresponding interrupt enable flag must be set. (For this flag, Issue the RCTL instruction to that register: purpose, the SCTLO to SCTL? instructions can be used. Note that flag. 5 bits) multiple flag bits cannot be accessed at the same time.) += All the flags are reset at the HOLD mode + All the interrupt enable flags are reset at the system start. Set the desired flag after the reset. HOLD mode is released, Interrupt + Five Interrupt request flags are provided to the five interrupt + No flag is reset after interrupt process- request sources on an one-to-one basis. These flags are assigned to a ing terminates. Every time when a certain §| tlag pseudo port. To reset the flag bits, data is loaded to the AC interrupt processing is performed, be o (ACcumulator) by the "BANK + IP! instructions and then output sure to reset the flag that corresponds § to the port by the "BANK + OP! instructions. Note that any bit to the interrupt source, Note that if the 2 cannot be set. The data bit that corresponds to the flag bit to Interrupt request flag needs to be reset, 2 be reset should be set to ‘0' and the remaining data bits it should be confirmed that the master o ‘should be set to 'I', This data should be first set in the AC interrupt enable flag, and at the same € and then cutput to the interrupt request register by the ‘SANK time the individual interrupt enable flag + OP" instructions. that corresponds to that interrupt source + At the reset, all the flags except for the timer 1 interrupt are both reset or either one is reset. request flag (TMIF) are set to all ‘0’. + All the flags are reset at the HOLD mode + The SIOF is reset the moment when the seria! data transfer is start-up. started, + Be sure not to issue the 'BANK + SPB/RPB’ instructions to the interrupt request register. No. 3117-26/28

Considerations on Program Evaluation + The application programs for the LC65204A should be evaluated on the evaluation chip (LC65999 or LC65PG20X/40X) with the following considerations in mind, - Consideration Production chip EVA chip RAM capacity | RAM capacity of The desired RAM capacity can | Set the RC and RC2 pins properly in 256 x 4 bits be selected by using the RC | accordance with the production chip RAM and RC2 pins. capacity. @| Stack levels | 8 levels The desired stack level can| Set the STC pin properly in accordance £ be set by the STC pin, with the production chip setting. § output type of | Pch high-voltage withstand | The circuit type of ports C | Set the C/FLSEL pin properly in ac- % |ports C and D] input/output and D can be set to the Pch | cordance with the production chip é high-voltage withstand | circuit type. input/output or the Nch medium-voltage withstand input/output by the C/FLSEL pin, Oscillation Connect the desired oscil- | If the EVA chip board is used | [EVA chip board] Set the jumper switch circuit lator with pins OSC1, OSC2, | for program evaluation, the | properly in accordance with the pro- X1 and X2. desired oscillator can be | duction chip option setting, [simula- selected by using the jump | tion chip] Connect the same oscillation switch on the board. The | as that of the production chip to pins simulation chip has the same | OSC1, OSC2, X1 and x2. optional selection as the production chip. Output level | 4-bit simultaneous select. | Port C can set to the 'H' or | Set the CHL and DHL pins properly in of ports C ang | The output level of all the | 'L' by the CHL pin while port | accordance with the production chip © at the reset] four bits of the port C or D | O by the DHL pin, option setting. can be set to the 'H! or 'L' at the same time. Watchdog reset | The watchdog reset function | The watchdog function can be | Set the WDC pin properly in accordance function based on the time base timer | activated or inactivated by | with the production chip option sett- » can be selected. using the WDC pin. ing. S —— %| AC zerocross | The AC zero cross detection | The AC zero cross detection | Set the ACZ/INTO pin properly in § | detection circuit can be internally | circuit can be internally | accordance with the production chip =| circuit added to the PF3/INTO pin, | activated by the ACZ/INTO| option setting, 3 pin, B| Port output | The output type of each port | No pull-up resistor output | [EVA chip board] Connect the 10kohm of ©} type: PU and | pin can be set to the PU or | can be selected, All the port | external resistor to the target port. oD OD (on a single-bit manipu- | pins are set to the Nch OD | (Simulation chip] Connect a resistor to lation basis). output type. the target port of the user application board. PU resistor | This resistor is used with | Since this is a resistor} On the production chip, only the the port pin that enters the | externally added, the im- | leakage current flows into the Pch Tr. high impedance state (Hi-Z | pedance level remains un- | at the 'L' output. However, the current OFF) a the 'L'-level output. | changed at the 'L' level] flow continues through the pull-up output. resistor on the EVA chip, Please remember. Port output | The output type of each port | No pull-down resistor can be | [EVA chip board] Connect the 100kohm of type: PDand | pin can be set to the OD or | selected. All the port pins | external resistor to the target port. oD PD (on a single-bit manipu- | are set to the Pch OD output | [Simulation chip] Connect the external lation basis). type. resistor to the target port of the user application board. Note that the user application board should have its own load power supply. No. 3117-27/28

qf. — == 35) Consideration Main clock | [Crystal oscillation] and| (Crystal oscillation] and | [Crystal oscillation] and [Ceramic oscillation [Ceramic oscillation) If the | [Ceramic oscillation] The EVA | oscillation} External constants should constant: guaranteed constant listed in| chip differs from the pro- | be fine-adjusted according to the this catalog is used, the| duction chip in oscillation | evaluation environment. standard oscillation fre- | circuit design and character- quency is produced. istics. In addition, the ec oscillation may be unstable 2 due to wire capacitance. | Sub clock (Crystal oscillation] If the | (Crystal oscillation] The EVA | [Crystal oscillation] External | oscillation —_| guaranteed constant listed in| chip differs from the pro- | constants should be fine-adjusted ac- constant this catalog is used, the | duction chip in oscillation | cording to the evaluation environment. standard oscillation fre- | circuit design and character- quency is produced. istics. In addition, the (19) oscillation may be unstable due to wire capacitance. Oscillation | The oscillation frequency | The EVA chip differs from the | The detailed evaluation should be per- frequencies of | characteristics are shown in} production chip in circuit | formed on the ES and CS. main clock and | this catalog. design and characteristics, sub clock Operation The current characteristics | The EVA chip differs from the | The standby current cannot be evaluated current and | are shown in this catalog. | production chip in circuit | in detail. However, the standby func- Standby cur- design and characteristics. | tion can be confirmed in the manner as 8 | rent shown in the manual. Be sure to check . 3 the standby function in that way. The 5 characteristics should be evaluated in g detail on the EC and CS. & | Operating The operating power supply |The power supply voltage | The EVA chip should operate in the 3 | power supply | voltage range is shown in| range is limited to the the | operating power supply voltage range of 8 | voltage this catalog. range for the EPROM andother | VDD=5V 45%. The operating voltage

8 LSis, range of the EPROM and other

Ff LSts shoutd not be exceeded, This means that the functions in the entire oper- ating range of the production chip cannot be evaluated, Operating The operating ambient | Guaranteed temperature range:| The operating temperature range of the ambient temperature is shown in this | 10 °C to 40°C EVA chip and the simulation chip should temperature | catalog. be from 10°C to 40 C. ROM capacity | The LC65204A has the 4Kbyte | Up to 8Kbytes of ROM canbe | It should be confirmed that the ap- ROM, This means that the JMP | externally added to the chip. | plication program size is less than 4K 5 and BANK + JMP instructions | The SB+ JMP, BANK + JMP and| bytes, Pa allow program to jump to the | JMP instructions allow pro- 2 entire ROM area, Note that | gram to jump to the: entire a the SB + JMP instructions | ROM area, cannot be used. HI No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. @ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO,, LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such olaim or litigation on SANYO ELECTRIC CO, LTD,, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- . eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties, No. 3117-28/28

Product Information

LC65204A specifications and overview.

Summary

4-bit SingleChip Microcomputer for Control Applications

Description

4-bit SingleChip Microcomputer for Control Applications

Source title LC65204A Datasheet(PDF) - Sanyo Semicon Device

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