LC6513A

LC6512A SANYO | Alldatasheet

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© Low power dissipation CMOS single-chip microcomputer ¢ Instruction set with 79 instructions common to the LC6502C, 6502B, 6502D/LC6505C, 6505B, 6505D © 2-source, 2-level interrupt function (external interrupt/internal timer interrupt) © B-level stack ¢ 4-bit prescaler-contained 8-bit programmable timer ¢ FLT driver-contained output ports and low-threshold input ports (1) Digits driving output ports: 10 pins (2) Segments driving output ports: 8 pins (3) Normal voltage input ports: 8 pins (4 pins: Low-threshold input port) (4) Normal voltage input/output ports: 8-pins e ROM, RAM (1) LC6512A ROM: 2048 bytes, RAM: 128 x 4 bits (2) LC6513A ROM: 1024 bytes, RAM: 64 x 4 bits © Cycle time 1.33us min. 400kHz, 800kHz, 1MHz, 3MHz ceremic resonator OSC * Power-down by 2 standby modes (1) HALT mode: Power dissipation saving by program standby during normal operation (2) HOLD mode: Power supply backup during power failure {3) The standby function is the same as for the LC6514B and its using method is different from that of the LC6502D, 6505D, etc. © Differences among LC6512D, 6513D, and LC6512A, 6513A_ . The LC6512D, 6513D and LC6512A, 6513A are different in the OSC circuit only and are the same in the basic features, The differences are shown below. |_tem | __keesizavesisa[keasia, e515 OSC circuit | 1-stage inverter 5-stage inverter fi configuration OSC mode | Ceramic resonator OSC Ceramic resonator OSC, CR OSC, application of external clock a waveform Operating Ceramic resonator OSC: 500kHz, 800kHz, Ceramic resonator OSC: 400kHz, 800kHz, 1MHz frequency 1MHz, 3MHz CR OSC: 400kHz typ, 800kHz typ External clock: 222kHz to 1290kHz Technical Data The LC6512A, 6513A are members of our LC6500 series of CMOS microcomputers. For their internal functions, refer to the LC6500 SERIES USER’S MANUAL. Those which differ from the description in the USER’S MANUAL are described in this catalog. Carefully study features and Appendix 4 Standby Function in this catalog before using the LC6512A, 6513A. SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 7129Y1/7227KV5317)||/N256KI, TS No.2367-1/23

LC6512A, 6513A ee Package Dimensions 30258-D42sIC (unit: mm) 2 _ 2 = Sa ; 3 SANYO: DIP42s Package Dimensions 30524-048AIC (unit: mm) 20.0 4.0 ONS [aA OANUR A SS hahha =" —= UI pe E ee = = =| = paz lay Pat STITT TA feo El FB veo cesy) NOON OUUER Pai a NT Ls PB2 G) (3) HOLD PB3 Ee} Pi " Pco @ PIO Pin Assignment Por 5 PH3 Po2 G] [34] PH2 Pc3 [33] PHi Poo Ti] PHO POI fy] P63 ., PO2 PG2 Pin Name P03 [i [23] PG) OSC1, OSC2 : Ceramic resonator for OSC PEO £5) 2) PGO on PEI Ge] [2] PF3 INT i Interrupt Pe2 fa] Pr2 : Pes G (2) PF1 RES : Reset Fe Beco HOLD : Hold Test Gi 3) osc2 PAO-3 —_: Input port A0-3 (ovr vss Bi Hoses PBO—3 + Input port BO-3 DIp42s PCO-3 : Input/output common port co-3 PDO-3 : Input/output common port DO-3 PEO-—3 : Output port (High-voltage port) E0—-3 io PFO-3 : Output port (High-voltage port) FO-3 BESI2o oF 8Ee PGO-3 : Output port (High-voltage port) GO—3 PHO-3 —— : Output port (High-voltage port) HO-3 pas 1 PREM BRNOB : . Pco 42 3 Pio P10,1 : Output port (High-voltage port) 10, 1 por 43 34E pus TEST : Test Po2 44 3b paa P03 45 32 PH NC 6 3 PHO PDO 7 30 NC por 48 29+ Po3 poz 49 28} PG2 (Note) Nothing must be connected to NC Pp3 7710 27 PGI Pins internally or externally. bes tp aL pee 13.1415 16 17 18 19 20 21 22 23 24 When mounting the QIP version on the Jor BeesNora board, do not dip it in solder. BERG S22 aReEe Qip4as ee No. 2367-2/23

LC6512A, 6513A System Block Diagram PAO~3 =i | [ec —y [FT] wR] | Ppo~3 [_) aT LI = PCO~3 on om 4 poo~s (= 0 {= {i PEO~3 oni on | | . — 7 oat PFO~3 mo Perr Tt Pa0~3 mics LEswr system clock ~3 d tm Fe—o OSC1 Plo, 1 ae Note *: High-voltage port ) ) 4 4 $ $ FOLD NT RES TEST Vss Voo RAM __ : Data memory STS : Status register F 1 Flag ROM _ : Program memory WR : Working register PC : Program counter AC : Accumulator INT : Interrupt controt ALU — : Arithmetic and logic unit IR : Instruction register DP : Data pointer I.DEC : Instruction decoder E +E register CF, CSF : Carry flag, carry save flag CTL —: Control register ZF, ZSF : Zero flag, zero save flag osc : Oscillation circuit EXTF .: External interrupt request flag ™ : Timer TMF : Internal interrupt request flag Pin Description HOLD Input HOLD mode request input pin (The LC6502, 6505 differ in function.) Capable of being used as a general-purpose single-bit input port unless the standby mode is used. PAQ.3 Input port Ag to Ag (Normal voltage, low-threshoid input) Capable of 4-bit input and single-bit decision for branch Use also for HALT mode release request input {Continued on next page) No. 2367-3/23

LC6512A, 6513A (Continued from preceding page.) PBo.3 Input Input port Bg to Bg (Normal voltage) Capable of 4-bit input and single-bit decision for branch PCo.3 input/Output | Input/output common port Cg to C3 (Normal voltage) Capable of 4-bit input and single-bit decision for branch during input Capable of 4-bit output and single-bit set/reset during output PDo.3 Input/Output | Input/output common port Dg to Dg (Normal voltage) Capable of 4-bit input and single-bit decision for branch during input Capable of 4-bit output and single-bit set/reset during output Output port Eg to Eg (Digit driver output) Capable of 4-bit output and single-bit set/reset Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch Output Output port Fo to F3 (Digit driver output) Capable of 4-bit output and single-bit set/reset Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch PGo.3 Output Output port Go to G3 (Segment driver output) Capable of 4-bit output and single-bit set/reset Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch PHo.3. Output Output port Hg to H3 (Segment driver output) Capable of 4-bit output and single-bit set/reset Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch Output Output port Ig, 14 (Digit driver output) Capable of 2-bit output and single-bit set/reset Capable of 2-bit input of output latch contents and single-bit decision of output latch for branch osct | Input _| A ceramic resonator is corinected to this pin and pin OSC2 in the internal clock mode. Osc2 | outpur | Pin for externally connecting a resonance circuit for the internal clock mode Vop Power supply pin Normally connected to +5V Ives | - | Connected to OV power supply TEST LSI test pin Normally connected to Vssiov) Absolute Maximum Ratings/Ta = 25°C, Vsg = OV unit Maximum Supply Voltage Vpp -0.3 to +7.0 Vv Input Voltage VIN Input pins other than OSC1 0.3 to Vpp+0.3(Note1} Vv Output Voltage VouT(1) Ports C, D OSC 2 ~0.3 to Vpp+0.3 Vv VouT(2) Ports E, F,G,H, | Vpp—45 to Vpp+0.3 Vv Peak Output Current fo) Ports C, D: Each pin —2.0 to +2.0 mA . lo(2) Ports E, F, }: Each pin —15 to 0 mA 10(3) Ports G, H: Each pin —10 to0 mA loa) All pins of Ports C tol —90 to +16 mA Allowable Power Dissipation Pgmax(1) Ta=—30 to +70 C(Flat package) 350 mW Pgmax(2) Ta=—30 to +70°C (DIP) 600 mw Operating Temperature Topr —30 to +70 °c Storage Temperature Tstg —55 to +125 °c (Note 1) For pin OSC1, up to oscillation amplitude generated when internally oscillated under the recommended oscillation conditions in Fig. 2 is allowable. [Note] When mounting the QiP package version on the board, do not dip it in solder. No. 2367-4/23

LC6512A, 6513A Allowable Operating Conditions/T, = —30 to +70°C, Vpp = 5V£10%, Vss = OV min typ max unit Operating Supply Voltage Vpb(1) 4.5 5.0 5.5 Vv Power-down Supply Voltage Vpp(2) HOLD mode: HOLD = V1L(3) 18 55 v “H"-Level Input Voltage VIH(1) Port A 1.9 Vop Vv VIH{2) Ports B, C,D 0.7VpD Vpb Vv Vini3) TNT, RES, HOLDandOSci ~—0.8Vpp Vpp Vv “L’-Level Input Voltage ViL(1) Ports B, C, D Vss 0.3VpD Vv VIL(2) INT, RES, OSC1 Vss 0.2VoD Vv ViL(g} HOLD, TEST: Vpp=1.8 to 5:5V—Vsg 0.2Vpp v ViL(4) PortA Vss 0.5 v External Capacitance for Ceramic C1 See Fig. 2. Resonator OSC c2 See Fig. 2. Allowable Delay in Key Scan tDH See Figs. 3-3, 3-4 in Appendix 3. (N-2) Xteye us Circuit tDL (N-2) Xteye us (Note) teyc: Cycle time at microcomputer running mode Standby Timing tVDDF Vpp=1.8 to 5.5V, See Fig. 1. i) us tVDDR _- Vpp=1.8 to 5.5V, See Fig. 1. 0 us HALT instruction + XO [Note } Voo (1) Standby No chattering shall be applied to the HOLD” Ving) Ne code fae pin and PAg to 3 pins during the HALT instruction execution cycle. oot) Vis) == = f----- OV ~~ --- 2-2-2 22 ee boo ‘voor Fig. 1 Standby mode timing No. 2367-5/23

LC6512A, 6513A Electrical Characteristics/Ta = —30 to +70°C, Vpp = 5.0V#10%, Vsg = 0V min typ max unit “H"-Level Input Current WH Each input pin: ViN=VDD 1.0 HA “L'-Level Input Current lie Each input pin: Vin=Vss -1.0 HA “H"-Level Output Voltage VOH(1) Ports C, D: IQH=-1mA Vpp-2.0 Vv VOH(2) Ports C, D: IoH=—100uA Vpp-0.5 Vv VOH(3) Ports E,F,: IQH=-10MA = Vpp-1.8 v - VOH(4) Ports E, F, 1: IQH=-2mA Vpp-1.0 Vv VOH(5) Ports E, F, 1: IQH=—1mA Vpp-0.5 v (Each port IOH=Less than —1mA) VoH(6) — Ports G, H: IgH=—-2mMA Vpp-1.0 Vv VoH(7) Ports G, H: IoH=—1mA Vpp-0.5 Vv (Each port IoH=Less than —1mA) VOH(8) OSC2: IoH=—-1002A Vpp-0.5 Vv “L'-Level Output Voltage VoL(t) Ports C, D: IgL=1mA 04 v VoLi(2) OSC2: Io. =1002A 0.4 Vv Output OFF Leak Current loFF(1) Ports C, D: VouT=Vpp, HOLD mode 1.0 uA 'OFF(2) Ports C, D: VouT=Vss, -1.0 BA . HOLD mode ioFF(3) Ports E, F, G, H, |: VouT=Vpp 30 BA lOFF(4) Ports E, F,G, H, I: 30 LA VouT=Vpp-40V Clock OSC Frequency for fcFosc OSC circuit in Fig. 2: 392 Note2 408 kHz Ceramic Resonator OSC Recommended conditions for 784 Note2 816 kHz ceramic resonator OSC 980 Note 2 1020 kHz

2940 Note 2 3060 kHz

Current Dissipation Ippi1) Ceramic resonator OSC; f=400, 800, 1000kHz 1.0 2.0 mA Operating mode f=3MHz 27 4.0 mA Recommended conditions for ceramic resonator OSC, output pin open, input pin ViN=Vss Ipp(2) HALT mode: Vpp=5V10%, 10 vA Test circuit in Fig. 3 Ipp(3)__- HOLD mode: Vpp=1.8 to 5.6V, 10 BA Test circuit in Fig. 4 Input Capacitance CIN Each input pin: Measure at f=1MHz. 5 pF Pins not being measured: Vg Output Capacitance CouT Ports E, F, G, H, 1: Measure at f=1MHz 10 pF Pins not being measured: Vsg Input/Output Capacitance Cio Ports C, D: Measure at f=1MHz, 10 pF Pins not being measured: Vg Hysteresis Voltage Vu INT, RES, HOLD 0.1Vpp v No. 2367-6/23

LC6512A, 6513A [Center frequency | Coramic resonator [C1 (pF) | C2 (pF) _| CF: Ceramic resonator osct osca : CSA3.00MG (Murata) | ___S5HT0% | ‘Note 3) GSAS.00NG (rat) . ‘yoceral KBR3.0MS (Kyocera) CSB1000K, D (Murata) | imme | ‘CSB1000K, D (Murata) KBR 1000H(Kyocera) KBR1000H (Kyocera) 180+10% 0 CSB800K, D (Murata) (CSBB00K, D (Murata) 180210% “so 2 KBRGOOH (Ky osera) B00kHz * as Tt CSB400P (Murata) KBR800H (Kyocera) KBR400B (Ky osera) a 330210% KBR400B (Kyocera) 330#10% Fig. 2 Recommended OSC circuit, constants for ceramic resonator OSC Note 2) There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the nominal value presented by the ceramic resonator supplier, For details, refer to the specification for the ceramic resonator. The min., max. values of OSC frequency represent the oscitlatable frequency range. Note 3) When using the piggyback microcomputer, evaluation chip for evaluation, connect a feedback resistor (approxi- mately 1Mohm). I a ‘OSG2 OSCT OS02 SCT PEO Free Pet per BEN f—jrar Pe? paz PE2| vues Pas PES Pas PES! PFO PRO PFO peo PFI pe PF [esr Be? paz PF2| [eer PE ke pes PF3| vucyet pas 89° Release Release poo PG0— | Release P09 Pa jpc2 Pa? PC! pa3 pos Poa f—lece Bo] Poo PHO| t—jecs Bur Por PHY t—lp00 iis poz PH2| [P21 ena Pos PH3| [-——]P02 PI Pi [— fn ae Pit +— ir fu [—FEOUD rest [Harp Test]

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input/output common ports C, D: Output inhibit HALT instruction is executed to provide HALT mode, Fig. 3 I pp(a) test circuit Fig. 4 Ipp({3) test circuit [> Operation start Voo | 48V ----~ RES v Z—-==" Vows): (OBVOD=A4V at Voo= SV) TVoo, ' Z— Vii2y=(0.2V00=0.9V at Voo=4.5V) ov {| 080 Voo tof R TVD: Power supply rise time constant Lces12a) FES| TRES: RES pin rise time constant 6513A| 7° Fix C, R so that TVDDSTRES, tOSC2 10msec. is obtained, Vs tOSC: OSC stabilized time ss Fig. 5 Initial reset timing No, 2367-7/23

LC6512A, 6513A Appendix 1. Support System . For application development of the LC6512A, 6513A, the support system for the LC6512A, 6513A is used. 1-1, Software support The support system provides source editor, cross assembler. For cross assembler on CP/M, the ““LC6502.COM”, “LC6505.COM" are used, and on MS-DOS, the "LC6512.COM”, "LC6513,COM” are used, 1-2. Hardware support (1) Evaluation-chip . Evaluation chip LC6597 is used. Level converters, drivers are connected to high-voltage ports (PEg to 3, PFo to 3, PGo to 3, PHg to 3, Plo, 1) externally. {A dedicated adaptor is available.) Evaluation chip LC6597 Boon s K2) General-purpose input poo~3 Ka i PD0~3 jeneral-purpose input/output External memory for program PEO~3 eprom [5 Boone = [> FLT driver output or | PHO~3 RAM Ko] oPio,1 Fig. 1-1 Basic evaluation system using evaluation chip (2) Simulation chip Piggyback LC65PG12/13 and adaptor (EVA-97-12D/13D) for the LC6512A, 6513A are used jointly. Lo6sPG12/13 EZ EVA97-120/130 ——_— a A driver shown in Fig, 1-3 is contained. ne —<— cin Conversion board TB42S v To user's application equipment Fig. 1-2 How to use piggyback No, 2367-8/23

LC6512A, 6513A (3) Evaluation kit The EVA-410 and EVA-TB2 are used. For connecting with user’s application equipment, adaptor (EVA-97-12D/13D) is used. (4) Adaptor (EVA-97-12D/13D) This is used when evaluating the LC6512A, 6513A with the aid of the evaluation chip and piggyback. This contains drivers for FLT. (See Figs. 1-3, 1-4.) 42-pin tC socket Bo * Evaluation kit ae Ss > river ‘Vp input S © Power supply for adaptor- . contained driver (LB1294) Nig} Conversion board T8425 -Vpp for FLT is applied, No external driver is required for User's pplication board mass-produced microcomputers, 4% (42-pin IC pin) Fig. 1-3 Adaptor (EVA-97-12D/13D) for LC6512A, 6513A CN3 CN2 NFP-50A-0112 cNi Conversion board Connector for (Yamaichi Electric-made) Surface 42-pin socket 42-pin IC pin cable connection 4 (Yamaichi Electric-made) Pah fet [lah | eer Toa a gC Ce it pan Ts Hee: : 7} ferore} + n ' ' ' i) Pt TT? pon vot 5.6K ' : ° < a] a es 1 oe react — 25 | sod poy m4 era is ee ° 1 ee eo | 1 oe of — ont ier oft ee ree a ' , rt “pe © T t OD ’ ' H : ‘ 1 ‘ 9 : 1 <a e 1 of 7 a 1 oz ret met o2 | ie out a eC oe ‘ H t ' ' en a) ple ont per 2 ee aT HH cis | (ex reat pe} en | roy | 7 rt ‘ tg! ' ears re es oR!

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{ S200 $38 ee Uae ' ' ’ ’ 1 oy 1a | 02 1 IC1~3 (I6pin) rok pot eo 22) ' LB1294 10 pin : NC \\ oat oat | 1 2 1 (C4 (14pin) tooo enn ceed LA6339 Fig. 1-4 EVA-97-120/13D. No, 2367-9/23

LC6512A, 6513A Appendix 2. Internal Architecture of LC6512A, 6513A The LC6512A, 6513A are identical with the LC6502C, 6505C in the internal architecture and instruction set except that output ports are of high-voltage type and port A is of low-threshold input type and the standby function is the same as for the LC65148. For details, refer to ‘‘LC6500 SERIES USER’S MANUAL”; and for the standby function, refer to Appendix 4 “Standby Function”, 2-1. PC For the LC6512A, 6513A, this is organized with a 11-bit, 10-bit binary counter, respectively, which specifies the ROM address of an instruction to be executed next. The high-order 3(2) bits specify a page and the low-order 8 bits specify an address in the page. The page is updated automatically. ( ) is for the LC6513A. 2-2. ROM This is used to store user programs. For the LC6512A, 6513A, this is organized with 2048 x 8 bits, 1024 x 8 bits, respectively. By using the ROM table read instruction, the whole area can be accessed and the display pattern can be programmed. 2-3. Stack This is used to save the contents of the PC at the subroutine call or interrupt mode. This allows subroutine nesting up to 8 levels. 2-4. DP This is a register organized with 4-bit DPL and 3-bit, 2-bit DPH for the LC6512A, 6513A, respectively. When accessing the data RAM, the DPL, DPH specify a column address, row address, respectively. When accessing input/ output ports, the DPL specifies port A to port |. The DPL also specifies internal pseudo port O. 25. RAM This is a static RAM used to store data. For the LC6512A, 65134, this is organized with 128 x 4 bits, 64 x 4 bits, respectively. Row address 7H(3H) is allocated for 16 flags and 8 working registers which can be manipulated without being addressed by the DP. ( ) is for the LC6513A. 2-6. AC, E The AC is a 4-bit register which stores data to be processed by instructions. The E register is an auxiliary register to be back up the AC and is used as a temporary register or general-purpose register at the instruction execution mode. 2-7. ALU This is a circuit which performs arithmetic and logic operations specified by individual instructions. This outputs not only data of operation results but also the status of carry (C), zero (Z). 2-8. Status register This is a 4-bit register which stores the status of carry, zero and the external interrupt, timer interrupt request. The contents of the status register can be tested by the branch instructions. 2-9. Timer This consists of a 4-bit fixed prescaler and a 8-bit programmable timer. This counts the system clock and requests a timer interrupt when an overflow occurs. 2-10. Control register This is a 4-bit register, 2-bits of which control input/output of input/output common ports C, D and 2-bits of which enable/disable external interrupt, internal timer interrupt. 2-11, Input/output ports There are 9 ports/34 pins from port A to |. Each port is addressed by the DPL. Ports A, B are of normal-voltage input type, ports C, D are of normal-vottage input/output common type, and ports E, F, G, H, | contain FLT drivers. Port A is of low-threshold input type. No. 2367-10/23

LC6512A, 6513A (1) Ports Ag to 3, Bg to 3 DSB-—~-Input inhibit at HOLD mode Ports A,B >—hO— Internal bus Functions 4-bit input (IP instruction) © Single-bit test (BP, BNP instructions) © Port A: Low-threshold input * Port B: Normal-threshold input (2) Ports Cg to 3, Dg to 3 DSB-— Input, output inhibit at HOLD mode Output: High impedance Ports C, DO Te Internal bus SetBRt (= | Co BSS-—--Output control (Control register) Functions 1. Input mode (Output inhibit) © 4-bit input (IP instruction) Single-bit test (BP, BNP instructions) 2. Output mode ¢ 4-bit output (OP instruction) Single-bit set, reset (SPB, RPB instructions) (3) Ports Eg to 3, Fg to 3, Gg to 3, Hg to 3, Ig to 1 (High-voltage ports) DSB=Output inhibit et HOLD mode (Output transistor OFF) Yoo P 5 i ae Intemal bus Ports E tot Functions —_—e 4-bit (2-bit for port I) output (OP instruction) © 4-bit (2-bit for port |) input of output latch contents (IP instruction) © Single-bit set, reset (SPB, RPB instructions) Set: The output represents a 1, ----- Output transistor ON Reset: The output represents a O. ----- Output transistor OF F © Single-bit test of output latch contents (BP, BNP instructions) © Ports E,F,I: FLT digits drive © Ports G, H: FLT segments drive No. 2367-11/23

LC6512A, 6513A 2-12. External interrupt The trailing edge of the signal on the INT pin is detected and the interrupt request flag in the status register is set. The occurrence of an interrupt is controlled by the enable/disable flag in the control register. 2-13, Reset The system is initialized by setting the RES pin to “’L” level. The contents to be initialized are as follows: « PC Address 000H ¢ Control register 0000 Interrupt disable, Ports C, D: Output inhibit e Status register Timer, external interrupt flag > Reset Output port Output latch (04) > Output transistor OF F Appendix 3. Proper Cares in Using LSI 3-1, Low-threshold input port Ag to 3 provides the input characteristic shown in Fig. 3-1. Voo : Vos [iit] } Low-level input Fig. 3-1 3.2. FLT driver output Ports Eg to 3, Fo to 3, tg to 1 (10 pins) are for high-current digits driver output; and ports Gg to 3, Ho to 3 (8 pins) are for intermediate-current segments driver outputs, Of course, digits driver outputs can be used as segments driver outputs, Fig. 3-2 shows a sample application. Key scan Ports E, F, 1 Digits . Az -Vop Sagments L.C6512A, 6513A Fig, 3-2 FLT display application No. 2367-12/23

LC6512A, 6513A ' Digit drive signal-used key scan When key-scanning with the FLT digit drive signal in Fig. 3-3 and inputting the return signal to port A, the following must be observed. {a) Estimate voltage drop (Von) in the output transistor using the current flowing in an FLT used and the V-I characteristic of the output port of the LC6512A, 6513A. {b) Estimate voltage drop (Vgw) in the switch circuit. (c) Check to see that Von + Vsw meets the VjH/Vi_ requirement of the input port in Fig. 3-1. tox, ton (External circuit delay time) s Switch circuit Voo stnputz Yow Non Port | s >) Current Output transistor | Output port FLT Fig. 3-3 Sample key scan application For the key scan application in Fig. 3-3, make the program considering the delay in the external circuit and the input delay shown below. N . N X-9P KTP coz OK wom YX oP YI Koz wow) X_ 1 Input port waveform This Any other instruction Any other instruction may be used. instruction may be used. This instruction must be used. must be used, Veet) Vi) ov . *\\. Output port Voo-40v Ss. waveform 4 LJ as ie @x® © tH @ Fig. 3-4 When the IP instruction is used to input the return signal as shown above, the input delay must be considered and two instructions are placed between the IP instruction and the crossing of input port waveform and Vj|(4), VIH(1), respectively. Some instructions must be placed additionally according to the length of delay (tpL, tpH) in the external circuit after the digit drive signal is delivered with the execution of the OP instruction (point a and point c). N; Number of instruction cycles existing between instruction (OP, SPB, RPB) used to output data to output port and instruction (IP, BP, BNP} used to input data from input port. (Number of instruction cycles to be programmed according to the length of toL, toy) tDL, tDH: Delay in external circuit from output port to input port. No, 2367-13/23

LC6512A, 6513A Appendix 4, Standby Function Two standby modes — HALT mode and HOLD mode — are available to minimize the power dissipation when the Program is in the wait state or a power failure is backed up. Both modes are set with the execution of the HALT instruction, All the operations including the system clock generator are stopped at the standby mode. (For other models 1.C6502/05 of the LC6500 series, the HOLD mode is hardware-set with the HOLD pin = “L". Be careful of the difference in the mode setting method.) The HALT mode and HOLD mode are used properly depending on the purposes. They are different in the mode setting conditions, !/O port state during standby operation, mode releasing method. The HALT mode is entered by executing the HALT instruction when the HOLD pin is at “H’ level. The HALT mode is used to save the power dissipation when the program is in the wait state. The HOLD mode is entered by executing the HALT instruction when the HOLD pin is at “L"’ level. At the HOLD mode all 1/O ports are disabled and there is no power dissipation in the interfaces with external circuits, permitting capacitor or battery-used power supply backup during power failure. 4-1, HALT mode setting The HALT mode is entered by executing the HALT instruction when the HOLD pin is at “‘H” level and all pins for port Ag to Ag are at ‘’L” level. When even one of pins for port Ag to Ag is at “H” level, the HALT instruction is disregarded and becomes equal to the NOP instruction, The HALT mode causes individual blocks to be placed in the following states. (1) | Operation is stopped ¢ All the operations including the system clock generator are stopped. (2) | 1/0 port © The state immediately before setting the HALT mode is held. (3) | Blocks to be cleared/reset request at the HALT mode is disregarded. (4) | Blocks to be held e For the registers, data RAM, port output latch, PC (except those in (3), the contents immediately before setting the HALT mode are held. 4-2, HOLD mode setting The HOLD mode is entered by executing the HALT instruction when the HOLD pin is at “L” level. In this case, the contents of port Ag to Ag remain unaffected. The state in the HOLD mode is the same as that in the HALT mode, except the state of 1/O port. The HOLD mode permits the undermentioned power-down mode to be entered. 1/0 port e Input ports A, B: Input inhibit e Input/output port C,D: Input inhibit, output high impedance Output ports E to I: Output Pch transistor OFF e INT, RES pins: Input inhibit For the output latch of the output port, the contents immediately before setting the HOLD mode are held. No, 2367-14/23

LC6512A, 6513A 4-3. HOLD power-down mode setting The HOLD mode permits the supply voltage to be lowered and also the power dissipation to be reduced after mode setting. The HOLD mode can be used in the capacitor or battery-used backup operation during power failure. Main power AY $$$ AYU supply \\ @ Voo @ iN Oc ° (INT) HALT tone iaieh tele Sees ea ® Power-down Instruction HOLD mode Fig. 4-1 HOLD mode and power-down ® A failure of the main power supply is detected and a standby request is made. This is hardware-controlled by the external circuit. @ The HOLD pin is software-polled or the same signal is applied to the INT pin to test the standby request by interrupt. Then, the HALT instruction is executed and the HOLD mode is entered. (Note) After the HOLD mode is entered, power-down can be attained by lowering Vpp. After Vpp returns to the prescribed voltage, the HOLD pin is set to “H" level and the normal operation returns, (Note) The HOLD pin input signal is transferred to pseudo input port PO 0 (DPL = OEH, 2° bit). Therefore, when polling the HOLD pin, the BPO or BNPO instruction is used at DPL = OEH. (The IP instruction cannot be used.) When the BPO.instruction is used for testing, a branch occurs when the input voltage is at high level in the same manner as for normal input ports. 4-4. HALT mode release Release by reset . When “'L” level is applied to the RES pin, the HALT mode is released and the system reset state is entered. When the RES pin is set to ““H’’ level again, the normal operation starts. Since the ceremic resonator mode is used for system clock generation, the release by reset must be performed. — Notes — © Since the ceramic resonator mode is used for system clock generation, “‘L” level must be applied to the RES pin for 5 to 10 msec {oscillation stabilizing time). Mode change from HALT mode to HOLD Mode The HALT mode is entered with the execution of the HALT instruction when the HOLD pin is at “H‘level. The HALT mode is changed to the HOLD mode automatically by setting the HOLD pin to “L” level. HOLD 7 F=" Value just before HALT in retained | t prohibited, Output High Impedance vo ne ari iees Mode Functioning | HALT mode HOLD mode Fig. 4-2 Mode change from HALT mode to HOLD mode No, 2367-15/23

LC6512A, 6513A 4-5. HOLD mode release Release by reset The HOLD mode is released by setting the HOLD pin to “H” level while applying “L” level to the RES pin. When the RES pin is set to H” level again, the normal operation starts. The contents of the memories remain unaffected except the PC, I/O ports, registers which are initialized by the reset operation. Since the ceramic resonator mode is used, the reset state must be held until oscillation is fully stabilized (10 msec after oscillation start) after the HOLD mode is released. FOLO a : ; RES ‘ {Note} 1 1 fi System clock iC h {Seare sentr moa <A 1 1 "Unstable : | Oscillation ‘ —— HOLD mode Jo— Reset —~|— Operation start after initial __ (10msec or more) "eset Fig. 4-3 HOLD mode release by reset Note: With ‘’L” level applied to the HOLD pin as shown above, the CPU is not reset even when the RES pin is set to “L” level. This is because the HOLD pin is given priority lest the CPU is reset unnecessarily when the capacitor or battery-used backup mode causes the CPU peripherals to operate unstably and the RES pin is set to ‘L” level. Be careful of the level of the HOLD pin and RES pin also at the initial reset mode when power is applied. When the HOLD pin is at ‘’L"’ level, no reset occurs. 4-6. Proper cares in using standby function When using the HOLD mode, an application circuit and program must be designed with the following in mind. (1) The supply voltage at the standby state must not be less than specified. (2) Input timing of each control signal (HOLD, RES, port A, INT, etc.) at the standby initiate/release state. (3) Release operation must not be overlapped at the time of execution of the HALT instruction. 4-7. Sample application where the standby function is used for power failure backup. Power failure backup is an application where power failure of the main power source is detected by the HOLD pin, etc. to cause the HOLD mode to be entered so that the current dissipation is minimized and a backup capacitor is used to retain the contents of the internal registers even during power failure. 4-7-1, Sample application circuit (ceramic resonator OSC) Fig. 4-4 shows a ceramic resonator OSC-applied circuit where the standby function is used for power failure backup. 100V 3 = tor = DI Rt 50 Power om Supply ~1F D4 3 Voo R6 RES 10k @ mn C3 © aia Lees12a/130 ® qe Ra re (0) t ose: R2 D3 BOK SRS Q) & ° 220K 12k R3 osc1 ba 220k FB 7, 0.01 Unit (resistance: ©, capacitance: F) Fig. 4-4 Sample Application Circuit No. 2367-16/23

LC6512A, 6513A 4-7-2. Operating waveform The operating waveform in the sample application circuit in Fig. 4-4 is shown below. The mode is roughly divided as follows: vt popeseress eer pe possesses egnzsiesss: FOOD i arn an ee or we h/ | Ann | a CsCl (Reset Normal mode oo ee @ Initial application of power —@) Instantaneous break-(2) @) Instantaneous break-(3) eee: —. _ ypoattetbereses: FOB Sa ; = vol HALT instruction 4.1 5 mode | Normal mode Reset _\\ Normal mode eos Laie @ Return from backup voltage 4-7-3, Operation of sample application circuit @ At the time of initia! application of power A reset occurs and the execution of the program starts at address OOOH of the program counter (PC). ® At the time of instantaneous break (1) At the time of very short instantaneous break The execution of the program continues. : (2) At the time of instantaneous break being a little longer than (1) (When the RES input voltage meets ViL and the HOLD input voltage does not meet Viti A reset occurs during the execution of the program and the execution of the program starts at address OOOH of the program counter (PC). Since the HOLD request signa! is not applied to the HOLD pin, the HOLD mode is not entered. (3) At the time of long instantaneous break (When both of the RES input voltage and HOLD input voltage meet Vj\\). The HOLD request signal is applied to the HOLD pin and the HOLD mode is entered. When V+ rises after instantaneous break, a reset occurs to release the HOLD mode and the execution of the program starts at address OOOH of the program counter (PC). @ At the time of return from backup voltage A reset occurs and the execution of the program starts at address OOOH of the program counter (PC). No. 2367-17/23

LC6512A, 6513A 4-7-4, Notes for circuit design @ How to fix C3, R6, C2, R2 Fix closed Joop (A} discharge time constants C3, R6 and HOLD pin charge time constants C2, R2 so that closed loop (A) fully discharges before the HOLD input voltage gets lower than Vj, at the time of instantaneous break and the RES input voltage is sure to get lower than VyL_ (a reset occurs) when V+ rises after instantaneous break where the HOLD input voltage gets lower than VL. @ How to fix C3, R7 Fix RES pin charge time constants C3, R7 so that when power is applied initially or the HOLD mode is releas- ed the ceramic resonator OSC oscillates normally and the RES input voltage exceeds Vj and the program starts running. @® How to fix R4, RS __ Fix Tr bias constants R4, R5 so that when V+ rises after instantaneous break the RES input voltage gets lower than Vj (brought to “‘L” level) before the HOLD input voltage exceeds Vj} (brought to “H” level). @ How to fix C2, R3 Fix HOLD pin charge time constants C2, R3 so that when the HOLD mode is released from the backup mode the HOLD input voltage does not exceed VQH {not brought to H”’ level) until the RES input voltage gets lower than VjL (brought to ‘’L’’ level). Fix C3, R7_ and C2, R3 so that the time interval from the moment the HOLD input voltage exceeds Vj} until the moment the RES input voltage exceeds Vj} is longer than the ceremic resonator OSC stabilizing time. © when the load is heavy or the polling interval is long Since C1 discharges largely, increase the capacity of C1 or separate (B) detection from V+ and use a power supply or signal that rises faster than V+. 4-7-5. Notes for software design When the HOLD request signal is detected, the HALT instruction is executed immediately. A concrete example is shown below. (1) An interrupt is inhibited before polling the HOLD request pin (HOLD pin). (2) Polling of the HOLD pin and the HALT instruction are programmed consecutively. [Concrete example ] RCTL 3 ;EXTEN, TMEN <0 (External, timer interrupt inhibit) BPO AAA ;Polling of the HOLD pin (If ““H” level, a branch occurs to AAA.) HALT iThe HOLD mode is entered. H AAA: II No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. WW Anyone purchasing any products described or contained herein for an above-mentioned use shall ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO, LTD,, its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD,, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Mi Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property. rights or other rights of third parties. No, 2367-18/23

LC6512A, 6513A Appendix LC6500 Series Instruction Set (by Function) Symbols Mesning M: Memory ©),[ 1: Contents AC: Accumulator MIOP): Memory addressed by DP - Transfer and direction ACt: Accumulator bit t P(OPL): Input/output port addressed by ODPL ** Addition CF: Carry flog PC: Program counter = Subtraction CTL Control register STACK: Stack register A AND DP: Data pointer TM: — Timer v oR E: E register TMF: — Timer (internal) interrupt request flag Exclusive OR EXTF: External interrupt request flag At, Ha, La: Working register Fn: Flag bit n ZF: Zero flag Mnemonic g tag 107060504 |D3020; Oo] ® attected Vac [ow ef Pv volocoif flere [mecrween Ted piste [se ef foo ori ferm [reeren | ef | slows |conotenen xe [rv efre wy [ri ae =m Raia fe {line [nconen Ac Joo o ofr ref p facsaciti | twacenwavenenmnase [ar ee |

3 Rotate AC Jett ACUMICF)AGa+ i= | The AC contents are shifted tafe through

3] RAL through, CF eooojooo1 ff fase; CFCs theck é {a [rarest ooo ofoor fh fences ee “frat [escraroe Ae win € foo oft 1 Ov [i fr facie FE F [iw [increment M [oy [11 0 [1 [t | moe <GADAIFT | rwMoranemenncermery far er |_| E [oem [orcremenr foo ofr ra a [i fh [worm tooe=1 wet | _ & ging oi of the MOP) speci The AC contants and ihe WIP) contents AC =1aci + (MC0P)) | 7 F, MIDPI contents are binary: g contents and ine WADA) convenes Fle [esciewe or rome] 111 foro + [1s [ac riaciw cmon | iemstestsetstan P85 |e 3 tnt ae : The AC contents and ihe MIOP) contents A contents anc MiDP) contents Blon for mie ac [20] aceinciv (morn) | EMSRS TASES Baca | ze : mpar we “The AC contents and the MIDP) contencs 5{cM Compare AC with M v fy] GarDPr}+ (ac) +1 Meaesoed te OF ER Sa ze cr i [_Comparisonresutt [CF [ZF | Mippiy>tacy [oT oT] | | (wippit=iacy [rT | | tmiopy<iacr | 1 fo | | Ch data mpare AC wi 1 1 The tents immediate data FOE eco eater lot oo PPP O FATTY | Tig ai tomiwredanswogtanste |7F S [“Conparson rent CF] 2F ] [aiztte>iaci] oT oO] Hytgtiig Sac Fy 1) talgivigciaci]| 1 10] | Compare DR with [0010|1 100 OPUVIa!a Tilo | The OPL contents ong immadiate cae | {s__ [store AC to M @000|001 0411 |miDPi—iac, TraACconienusarescoreaiomemior. | | | ‘Exchange AC win M O MMiMo AC) (MiOPI) The AC contents god the MIOP) contents rouat accord 2 then modity OPK DPw=(0Pql ¥ Me exchanged. Then. tne Deut contents | 7p tothe resutt of ‘ae Es immediate data | = OM2MiMo___| vaMiannig. "(mF sontent of (OPH! payee é Exchange AC with M ° (AC) (MiDPY The AC contents and the MIOP) contents reset acepe3i : 9 900 (ach = (M0PIT meonchonged Pa iene Beene 3 ‘imocot kare. Exchange AC with M. {ACI 5 (MIOP))} The AC contents and the IOP) contents isa aro ane then Sorter reset accord xO Exchange AC with M. vera ty [2 [aces (ror) Tee AC contents 20d the MiDP) sontenss The Ze ge then dorement OP Oresipeurm1 | SeaaSura, Trem rove fons jz | sey RTBL [Read table aia tor AC E=ROM The comtents of ROM scarenad by he PC megan now ali ‘renga Eire | || Ke and, No. 2367-19/23

JOr Dg Ds De |D3 02 Dy Do |* | tected £| LOZ data] Load DP wien Zero ang] Ista to DPx 0 The OPH ond DP. ae loaded with 0 and : OP with immeciate Dec miata tito | tmmediateldate tatatito respectively 2 data respectively 5 Lead DP with fata tito The. OPH loeand with Immediate deta 2 immediate data $1210. | Cee NN foe [orcienerr on. [vv eh [ey fon =iony=1 | tetrteemnenanneene [ze [| {i Treante ato RP To fe form een TT] ta Prate omen [oof of facmionar [Renee far [| B[xar__ [exchange AC wih wt Tne AC contents end the contents ol

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G XAO working regster Ar |t 1 1 0 FO"GEO 0 fr |r [racy 1A0) Toeatied OY 110 ore oxchorge le] XA! +110 fo tio ofr ]s fac siany BE) xaz 1110 f1 o:0 0 fr }r [cacy s¢az a XA3 y 41 0 f1 1:0 0 2» |(ACH S(A3) A Exenange OPs with rm Te, Fa a UPS i woreng vegsier na ft 117 |x f8%0 0 [1 ]2 |copm x10: SEE gS Si H 1113 [tito o (DP SiH) zp [Xta | Excnange OP: with 2 The OFL contents and she contents of | xL0 |worang ragsier te [1 1 1 1 Jofdt0 0 (DP. S110) SOER opger 40 oF LY species by 9 IB} xu 1412 Jolljoo (DP S(L1) 2 83 828; Bo 1 log apeciiod by 83828 180 tt tare tea 8387 81 B Fn 0 ' fag soacitind by 69828 160 is reso. onan A Brae & BPR

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FH yo the 4 bits, e including 3 : Hie oes: : agen reas gon Beet IMP sadr| Jump on the current [0 1 1 0 |1 PoPePe PC=PCWiRIseET) | ALIA, BeAD, Mere soeeiTed by sme bank Pr PePsPa|PaP2PiPo PiePoBovBabsy ReagaeeetT am moms on FTG PaPaP2P1 Po JPA [Jump mo the current TO10 PCr~o M1EAC) | A jump fp an powers aeciiog oy she g ang AC Scout 5 C2ZP addr} Cali subroutine in the P3P2P1 Po STACK =(PC)+1 ‘A subroutine in page 0 of bank 0 is called, & zero page PCIn5.PC1 ~0 HO z PCs~2=-P3P2P1 Po B| CAL adar [Cali subroutine in the |1 0 1 © |1 PuoPyPa STACK IPC) +2 ‘A subtoutine in bank O's calag, a 20 bank P2 PePsPa|P9P Pr Po Porto —OPoPEPOP? i PePsPuP3P2P1Po [et [inontonamonn [ooo oT el lec ista00 | amentonrnmammoam P| RT! | Return trom wnterupt PC ~ISTACK) return from an inerupt servicing routine CF ZF =CSF.ZSF routine occurs BA addi | Branch on AC bu 0111/0 0tito PCr-0— P7 PePaPa | if a single bit of the AC specitieg by im- wove: PPPs Pal PapzPi Po P3.P2PiPo | sderane soeitied by: ininedate: ante P according? . woacist SS tidRin ne etlent pope dears evolu ot Bran on no AC bn [O01 10 Otito PCr ~0— PrPoPaPa | it single bit of he AC soeiiog by im Moumonie is mediate data 110 is 0 8 branch to an BNAD ic P7 Po PsPalPyP2P1 Po PaP2PiPo | aderen acetic’ Wy Smoreticte dove 27 to BNA3 accor Wact=0 BOrwttnie an euro Be secure Ingo tw soke BMt addr | Branch on M bit Ort |ottite PC? ~O- PYPEPSPa | ifs single bit of the MIDP) specifieg by Wasmonic is Intaedste data itis 1 bearer oe 96 pratt P PoPsPalpaP2Pi Po P3P2P1 Po | adores sonst ‘by immediate outa 719 Seconing's A OMOP.ty to)=1 | Pownthin the current pape occurs thevalue at H Prepare] Bo Pa Ps Po papapie | inpesnie one 0 m0. a aren ie ge Ree. E A (MOP.t 19) )=O | toPBwithin the curfent page oceurs Ingo teva 8] BP adar|Brancr on Por bt [O11 111 Ost PC? ~0— PI PERSP4 | I 9 single bit of port PIDPL) secitieg by Moemonic.is Ps Ps Pal PaPaPiPo Papa mo | iaueteie ea Ma nguancn eB orore aes. (IOP tat oh J=1 | oF within the current page oceurt teevotusot BNPr add] Branch on no Pon bi Ton — Ua single bit of por PLOPL) spect by remonie " sa] Barer on no Pen ou [9 9 14 |! Otto PCr or PIP EPSPS | U eedaie ane 10 nO. b branch to oh BNEOts SNP3 »? Pg Ps Pa! Py Pz Pr Po P3P2Pi Po sas, ‘specified by immediate data P7 according to (POP tat }=o. | POs INN curent pope ects tevelueore BTM addr] Branch on timer Orrrir108090 PCr ~o- PrPePsPa | If the IME is). @ branch 2B ocarass MF Pr PePsPalPsPa Pi Po PaP2PiPo | ‘eihmine dren page occurs. The TMP TMF=1 rest then TME 0 No. 2367-20/23

LC6512A, 6513A Moemonie 3 Description tog 1D Dg 0s Ds [D302 Dy Dp |® | © affected BNTMaddd] Branch on roume JOO11]1 100 PCr~o= P7PEPEPS | It the TME is 0. 9 branch to an adores | TMF P2 PePsPa |P3P2P1 Po PaP2P1Po | rete he durrent nope occuss gn Ww TMF=0 eset then TME =O Bi dar [Branch on imtewupt [O11 [1 104 PCr~o—P7P6P5Pa | I the EXTF is 1.0 branch to an adores | EXTF PrPorsPe|paP2PiPo PaPEPiPo | Mining Curent pepe oeeury The EXTER =1 EXTR is reset then EXTF -O BNI addr | Branch on no interupi]OO1 1 {1 1 OF PC )=0- P7PEPSPa | Ih the EXTF i 0. » bronch 10 on aadress PrPoPsPePaP2PiPo PaP2PiPo | Sihn'tne curren sage stews) “The 1 eXTF=0 EXTE irreset. then EXTF =O BC addr | Branch on CF orvifraed PCr~o=P7PEPSPa | 11 the CF is 3.» branch to a address 7 Pe Ps Pa |PaP2P) Po. PaP2P1 Po | sowciied by, immediate det» P7 to PO “rst BNC adar | Branch on no CF oortfrist PCr~o- Pr PePsPa | 1 ihe CF is 0. » wanch 10 an adoro Pr PePsPa|PaP2P) Po PaP2Pi Po | speciied by immediate cats P7 to FO MCF =0 oriifrii0 PCr~0~PIPEPSPa | it the ZF is 1. 9 branch to on adress P7PePsPa|P3P2P1 Po Pap2PiPo | peciiad oy, rnmediate date Pr to PO ar) BNZ adar| Branch on no ZF oortliito PCI~O-PYPEPSPa | 1 ie ZF is 0. « branch to an ecara JP) Peps Pa |P2P2P1 Po PaPaPsPo | Mthinihe tuceat sage oosen, 7° wt 2F=0 BFn addr| Branch on Hag bt 1 1 0 7 [agngnino PC7~0—P7POPS Pa | ia fog bi of the 16 fags species by woemorie Immediate dete nananinois 4-8 bea FO 9 BF PrPePsPe|P3P2P1 Po P1P2P1Po | ss anaddress soecied oy immediate coi seceding (0 : aw oRnet B10 Bo wnthin the current page occurs thevaluootn, 9 ada] Bran "i 1 1 [ranzmve =m 7a |» fag bit of the 16 flog specitieg by Moamonie BNF a addr] Branen on no f199 00 1 Jnanzarno PCr 0+ PrPePsPe | \\rtadate cata ngngeinors Oa wank BUFO to BNF br IP: PePsPa|P3P2P1 Po PaP2PiPo | san address soncthes by immedate dota {Bisccording

4 Fa=0 80 Bo within the current page oscars 16 thavatueot

Sloe Jose ate nor foto foo ot [i]t prom imc Raa So wT 3] sPe ou [Ser oon ba 1 Br PLOP: B1Bo}—1 | immedice dara 8180 apocitied one bit in oenenig 3 b or 0000/01 B:Bo (OP. B1B0) irraiane dre 8180 00 SPB oie i to the lve ol S[mPB on [Reser port ow 0? B80 PI OP. B1B0) —O | Immediate date B Bpspeciied one Bit in When hia 3 por (DELI is veset wruction £ Ergin Eontentsare - Sesvoved SCTL but] Ser control vegste [0010/1100 CTL AACTLV Tmmediore data 836281 Bo specified bits butt S} 1 0 0 0 |B3828180 B3B2B1 Bo | the controtrepister ae se || RCTL O11 | Reset controt register [0.01 0] 1 0 o[2 [2 [cremictLyA Immediate date 83826180 specified bits | ZF bats) 10.0 1 |83828160 BeBSET Es | nite comvolreginier ere reset WITM [wore timer TM=1E) (AC) The € and AC contents ore loded in the | TMF uvabany Winer the thet reset HALT ‘All operations stop. [ror fre ervor ees eeepc frearazarenimen | #1 If the LI instruction or CLA instruction is used consecutively in such a manner as LI, LI, LI, —=-, or CLA, CLA, CLA, ~~, the first LI instruction or CLA instruction only is effective and the following LI instructions or CLA instructions are changed to the NOP instructions, No, 2367-21/23

LC6512A, 6513A LC6500 Series Instruction Map i s 2 o ° ala & rs) a)z 9 a 2 mA ala a a | ; Se BB (ES is) Z/N N o\\e “IE * a ‘ ae U] < z x a 8o|2 = ela Q ° Be] 2 5 S| os 55/2 cE) > | Be oS 2a a 4 ag 2 5 gs < 2 2/2 Be o}e 9 al< < sia L| | a ° im i S/e& c eye Ss = 2d ge alo oe <z|= w= Foaesd ola Fe) =| N [of . & alal/ele a a 2 nla ~ Zz </e Bl als a a a ay n a a ” Fd y x a oll < < fs} & x E c & °) jel. = < 2 Zz < a a oO Py iS) s aie = aq oa a i) < ole fs) a a * a s/3 -| Zz < < is) Eee ayAq is, ayAq puz No. 2367-22/23

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