LC65102A SANYO | Alldatasheet
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LC65102A, LC65104A SANYO fi 4-bit Single-chip Microprocessors OVERVIEW The LC65102A and LC65104A are 4-bit, single-chip microprocessors that incorporate 2 Kbyte ROM and 128 x 4-bit RAM, and 4 Kbyte ROM and 256 x 4-bit RAM, respectively, making them ideal for timer controllers, audiovisual equipment and domestic appliances. The LC65102A and LC65104A comprise one 2-bit and five 4-bit bidirectional I/O ports, a three-wire serial interface, an eight-channel, 8-bit A/D converter and a 14-bit D/A converter that can be configured as separate 6-bit and 8-bit modules or as a single 14-bit module. An on-chip oscillator can be directly connected to either an external crystal or ceramic resonator, or alternatively, an external oscillator can be used, The mask options for the LC65102A and LC65104A comprise a 14-bit general-purpose timer, used to generate pulsewidth modulated output or tone output, a 14-bit clock or overrun watchdog timer, and an AC zero-crossing detector or Schmitt trigger input circuit. Two power-saving standby modes are also provided. The LC65102A and LC65104A operate over a 2.7 to 6.0 V supply range and are available in 30-pin SDIPs. A 30-pin SMFP is currently under development.
FEATURES
+ 77 instructions * On-chip 2 Kbyte ROM and 128 x 4-bit RAM (LC65102A) and 4 Kbyte ROM and 256 x 4-bit RAM (LC65104A) instruction cycle times * — Software-selectable system clock * Four banks of eight working registers and 16 flags + Eight-level stack * 22 bidirectional I/O lines, including 12 multiplexed lines * — 8-bit precision, eight-channel tracking A/D converter + 8-bit interval timer for PWM D/A converter and music generator * 14-bit timer for calendar/clock function * Separate 6-bit and 8-bit or single 14-bit D/A converter configurations * — Serial I/O interface + AC zero-crossing detector mask option * Two external interrupts, two timer interrupts and one serial I/O interrupt * Wait function allows oscillator to stabilize after reset * On-chip oscillator supports 4.19 MHz crystal, 400 kHz or 4.0 MHz ceramic resonators + 1065999 evaluation chip, EVA800/850 emulator, TB65XXX adapter board and LC65PG10X piggy- back connector evaluation tools available + HALT/HOLD standby functions * 2.7 to 6.0 V supply operating range + 30-pin SDIP and 30-pin SMFP (under development) SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N1193JN B8-0195/8161JN No.3653-1/24
. LC65102A, LC65104A — SSS PIN ASSIGNMENT PeoaDsiDACe [1 | [30} PAsADS/NTT | PavaDsiDACi [2 | [29] Paging paonosson [5] [ee] Pasaos pavaonstanr [eo] AGIADO ave [5] [26] Pes av- [6] [2s] Peo vss uossioaar [24] P° osci [e} LC65102A faa] Poe osce [9] [ze] Por voo [21] P00 Fes [11] [20] Pca rest [ia] fis} Poe ros [13] [ra] Pcs pruso [14] Pco Pr2SCK [15] [16] PF3aNTo PACKAGE DIMENSIONS Unit: mm 3061-DIP30S 30 16 ) 88 10.16 1 18 -—2—_ 0.25 Cd adm THAAD aA i ae one thos | here 3073A-MFP30S 20 16 ar ir it ve de TT SSS No. 3653—2/24
LC65102A, LC65104A EE BLOCK DIAGRAM roA00 Pa Pa2ane KO PAVADIANT! | <2 an 1SDACI peonuarart | = Tanna iia aa eo poo l ree [Fra rea } ig bares ae we Oy) LIS i. oF kas f eB ; : . = eptsein Koy] Se 1 est <a rest ES brannto a v00 | IE as PrOINTY Note Values in parentheses indicate LC65102A RAM and ROM capacities PIN DESCRIPTION | 2 | PBI/ADS/DAGT |4-bit_VO port B multiplexed with A/D converter lines AD4 to AD7, D/A lines DACO and DAC1, square wave pulse output SQR and standby control line START. ; 3 | PB2/ADG/SCR Normally HIGH [es |» |” converter reference voltage input ee External crystal or ceramic resonator connection or external clock input a System reset input, Normally HIGH No, 3653--3/24
1C65102A, LC65104A eee a ; ow | PFA/SO 4-bit 0 port_F multiplexed with serial input and output lines SI and SO, serial PF2SGK _|clock output SCK and interrupt request input INTO. Normally HIGH es 4-bit /O port C a ee ee ete nme [| PaO Jasit vo port A multiplexed with A/D converter input lines ADO to AD and [2 | Pampa —|iterupt put INT, Normaly HIGH SPECIFICATIONS Absolute Maximum Ratings Supply voltage range 3 to 7.0 TEST, RES and OSC4 input voltage range 0.3 to Voo + 03 AV * input voltage range 0.3 to Voo + 03 AV "input voltage range 0.3 10 Vop + 03 Ports A, B and F3 input/output voltage range 0.3 to Voo + 0.3 Ports C, D and E, and FO to F2 input/output to 189 voltage range (open-drain output) Vice 0.3 to 151 v Ports C, D and £, and FO to F2 input/output a 03 lvoltage range (totem-pole output) Vios 0.3 to Voo + v Ports A, B, E and F average output current per pin range anges MME oti cre pe ee eee range Ports A, B, E and F average current per port 24 to 120 | ma | range Ports C and D average current per port range 20 to 100 [ma | No, 3653—d/24
LC65102A, LC65104A ee SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSeeeeeseSsssFSSSSFSSsseseSeee oo Recommended Operating Conditions Vss = 0 V, T, = 25 deg. C a Supply voltage range 27 to 6.0
Electrical Characteristics
Von = 2.7 to 6.0 V, Vss = 0 V, T, = -40 to 85 deg. C unless noted otherwise Port € and FO to F2 HIGH-level . 135 v input voltage (open-drain output) Vint n-channel tWansistor OFF | 0,80Voo ; | Port E and FO to F2 HIGH-level ' 5 v, v input voltage (totem-pole output) Vine n-channel transistor OFF | 0.80Vpo | - | oo Ports A and B HIGH-level input 7 Vu Vv voltage Ving n-channel transistor OFF 19 | - | oo n-channel transistor OFF, Ports © and D HIGH-evet input Via Von = 45 to 6.0 V 0.70Vo0 P= [ws | ov | voltage (open-drain output) n-channel transistor OFF | 0.75voo | - | 135 | v_ | n-channel transistor OFF, Ports C and D HIGH-level input Vong Voo = 4.5 to 6.0 V | oma | = | ve | ov | voltage (totem-pole output) nrohannel transistor OFF | 075Vo0 | - | Vo | Vv | lOSC1, START, PF/INTO and n-channel transistor OFF, INT1 HIGH-level input voltage. Vins extemal oscillator input. | 0.80Vop Voo v See note 1. See figure 16. RES HIGH-level input voltage Vinv n-channel transistor OFF, Port E and FO to F2 LOW-level Var Voo = 4.5 to 6.0 V fw | = | 0.20Vo0 input voltage mehannel transistor OFF | Ves | - ‘| 0.45V00 n-channel transistor OFF, v. Vv Ports A and B LOW-level input Vu2 Von = 45 to 60 V bad voltage SSE No. 3653—5/24
LC65102A, LC65104A ee ‘n-channel transistor OFF, 90V, Vv Ports © and D LOW-level input Vig (Yoo = 45 to 60V Vss | - | 9.30Vo0 voltage n-channel transistor OFF | Vss_ | - ‘| 025Voo START LOW-level input voltage Vie n-channel transistor OFF, extemal oscillator input. V 0.20V; v —— a . Iss .20Vo00 losct, RES, PF3/INTO and INT! See figure 16. Yoo = LOW-level input voltage. See Vus 8 {0 6 note 1 n-channel transistor OFF, external oscillator input. | Vs 0.15Vpo v See figure 16. TEST LOW-level input voltage Vas Ports A, B, C, D, E and F a HIGH-level ‘output voltage Vor P= SOMALI Noo — 1.2 v (totem-pole output) 00 = Ports A, B, C, D, E and F HIGH-level output voltage Vore lox = -10 pA Vo - 0.5 v (totem-pole output) lo = 5 mA, v Vout = P-[-[s | Ports A, B, E and F HIGH-evel Noo = 45 to 60 V output voltage \\ lo. = 1.0 mA, tox of v O12 other ports below 1 mA jou = 15 mA, Vous io = ; pe f- fe] | Ports G and D LOW-level output Voo = 45 to 6.0 V voltage lo 20 lo. = 2.0 mA, Io, of v Vous other ports below 1 mA Port F, INTO, INTI, RES and START hysteresis voltage. Vays 0.1Vop v See note 1. n-channel output peas. and 6 ane to Fa transistor OFF (includes HA ~ Hopen-drain output) ‘output transistor leakage i current), Vj = 135 V Ports A and B, and F3 n-channel output HIGH-level input current ‘transistor OFF (includes pA (open-drain output). output transistor leakage See notes 1 and 5 current), Vi = Voo Ports A, B, 0, D, E and F LOW-level input current | n-channel output -1.0 nA (open-drain output). a transistor OFF, Vi = Vss ‘ See notes 1 and 5 Ports A, B, C, D, E and F LOW-level input current he n-channel output 1.0 {(totem-pole output) ied transistor OFF, Vi = Vss See notes 1 and 5. ee No, 3653—~6/24
LC65102A, LC65104A eee fose = 4 MHz, | divide ratio = 1/1, ooge tee = 0.95 ys, Von = 4.5 to 6.0 V fose = 4 MH2, divide ratio = 1/2, 2 mA eye = 1.9 ps, Von = 4.0 to 6.0 V fose = 4 MHz, Operating current consumption. divide ratio = 1/32, mA See note 4 Ino tee = 905 ps, 93 Voo = 27 V fore = 400 kHz, | divide ratio = 1/1, o0Ps tye = 10 ps, Von = 4.0 to 6.0 V fose = 400 kHz, divide ratio = 1/1, 0 lopops tye = 10 ps, 50 pA Voo = 27V HALT mode, lost 4.19 MHz clock, o7 Voo = 6.0 V HALT mode, lopste 4.19 MHz clock, pA Voo = 2.7 V HALT mode, Standby current consumption. lonsrs 400 kHz clock, See note 4. Yoo = 6.0 V HALT mode, 400 kHz clock, pA Von = 27 V HOLD mode, HOLD mode, Ports A, B, C, D, E and F n-channel output lp-channel MOS output transistor transistor OFF, ka resistance Von = 5 V, Vi = Vss Notes 1. This value applies when the AC zero-crossing detector option is not selected. 2. Includes n-channel output transistor leakage current (transistor OFF) 3. Current dissipation values apply to microprocessor circuitry. They do not include currents associated with I/O port transistors. 4. These values do not include I/O port transistor currents. 5. Includes INTO, INTI and START eee No. 3653—7/24
LC65102A, LC65104A ——— SSSSssSssssssssSsSSSs Serlal Interface Vop = 4 to 6 V, Vss = 0 V, Ts = —40 to 85 deg. C rot cack 660 seins [wen | foe TT | puat ook (SH pres [toe [ove twve te zoe | = [|| SI data setup time Referenced to SCK rT - | - | «| tising edge. [02 Referenced to SCK falling edge. 1 ko, S SO propagation delay 50 pF extemal load. Las See figure 19 Note The pullup resistor values should be set so that tex: and tcqn are greater than 0.3 ps. AC zero-crossing detector Input Voo = 4.5 to 6.0 V, Vss = 0 V, T, = -40 to 85 deg. C A a fmxwew | wee Pe | Lowi iit ret [haw |e [= Tf | LOW-level input threshold Vt x Acm — iment wee PO ey Te Note Open-drain output with self-bias ON. See figures 21 and 22. No, 3653—8/24
LC65102A, LC65104A Self-exciting oscillator Von = 2.7 to 6.0 V, Vss = 0 V, T. = -40 to 85 deg. C unless noted otherwise See figure 14. Ceramic resonator frequency fosccr See note 1 392 408 sto oo me |e iow sf oe | - | ® |» | [too fi fair i P- | - fe | Extemal oscillator pulsewidth See figure 16 a See figure 16. External oscillator fall time [ns | Notes 1, The frequency is limited by the supply voltage, operating cycle time and frequency divider ratio. 2. Oscillator constants are listed in table 3. A/D converter Voo = 5.0 V +10%, Vss = 0 V, T, = -40 to 85 deg. C Parameter [ting a Lops Tee 1/1 conversion speed = 26 x tye BS 7 (leye = 0.92 to 12 ys) Conversion time 1/2 conversion speed = 51 x toe 612 ps (teye = 0.92 to 12 us) pep pe fv] Input reference voltage ea AV * = Vpp, Input ret 75 Peto input voage ee Includes output OFF-stale leakage HA Analog input current current, Val = Vpo a Ng, 6588/24
LC65102A, LC65104A eee Comparator Voo = 5.0 V +10%, Vss = 0 V, T, = -40 to 85 deg. C perme fm ee | ff = [| mes votuge [own Pe PO Pe TT a pee Input reference voltage ee 4A comparison = 12 x tye "1 144 us (lye = 0.92 to 12 ps) Comparison time tec 1/2 comparison = 23 x eye 276 ys (teye = 0.92 to 12 ps) INSTRUCTION SET Abbreviations AC Accumulator ACt Accumulator bit t CF Carry flag CTL Control register DP Data pointer E E register bFn Flag bit n GP(DP) Pseudo port specified by DP Ly to Immediate data M Memory M(DP) Memory addressed by DP MSTEN Master interrupt enable flag P(DPL) I/O port specified by DPL PC Program counter STACK Stack register fo, t Immediate data which specifies the bit within the addressed nibble as follows. bAt, bHa, bLa Working registers ZF Zero flag 0) 01 Indicates memory or register contents © Transfer in indicated direction + Add - Subtract A AND Vv OR v XOR No. 3653—10/24
LC65102A, LC65104A —tasstoza tossioge eel] el et ooooooc [a ewe ee eT PPP PP PPTs] oe CC CC CE 0 an Pe few dewwart tatefelete feof ppp [| Pee pee ferme fete fetepe pte pe [ | fm fowcmenme frareeaale fel [efoto fs [eff | aN peewee tere Pt ere PP hhh Td eee ED ce CC [wor ewan oom ms TT fete fetet fefalel || [we owns wwoee me [ef feeb feb fefafal pe [a ere erormefo le PtP pets]. | ee ee ooo Se [os pewmnnnonee fenvere fel Mt te[ ff felts | Se A [we powers enwoomontel [ett fetep ts fo [a fave tenvovmonte Tet Tr fetef fete t fo Lo femren remo Pele PPE Ee EET Ts | [ese firmmrermns fares Toe fs T Tessa eal = Te | [cise fomovnnmnanonfonvonwe [eT [sts tele atale fats [| fom fesceermer= Demoe TTP TTT PEt tL [| Oe SC OPH with immediate data. The (AC) (M(DP)] zero flag is delermined by DPH @ (OPH) ¥ 1 [comparing the dala pointer high | OM2M+Mo. nibble with OMgM4 Mp. Exchange AC with M. The zero eee POEEEEEEE ETD ee ae increment DPL. The zero flag is |(AC) <+[M(OP)} 1 1 [determined by the contents of the |DPL — (DPL) + 1 ment DPL. The zero fiag is (AC) e+[M(DP)] 1 Jdetermined by the low nibble ot | |DPL + (DPL) - 1 [ow fewer Hr TPP PEEL LE | 5680 tie
LC65102A, LC65104A eee Instruction code: —_ fr T= [= [= T= [= [oqo] Data pointer manipulation Load DPH with zero and DPL with |DPH «— 0 immediate data, respectively. OPL & Igl2ilo [iam [ooo mane fowcwewe | [e[>telefe[e[afe[™ | | Oe Os [a fewer ee Pe fet [| rte 0 wa worow fat Tete ti fet fefets ts Te | [wm leetwaescwn ory Ju sore [TF to lt Pefefet Tet: Ts | Working registar ‘to (AC) <(0A0) 1] o | 0 Zar [Eeinge AE wan wating ei aa oe i1e a}o XA2 AC) o{bA2) 4] 0 ayo xa (AC) <>(ba3) 1] 9 oT? a Exchange DP} with working 0 (OPH) <(bHO} 1 | | register bHa OPH) <(bH1) 1 1 Mua exchange DPL with workin XL ats " (OPL) ¢+(bLO) xur | fevister bla (OP) ex(bLt) [sm morn —ferevere | t tet tpepepefetet = [| Bit manipulation EO CC [Clear flag bit. The flags are orga- nized in 18 x 4-bit nibbles from RFB tag |OFOH to OFSH to SFCH to SFFH. |bFn + 0 ba 1 a The zero flag is determined by the contants of the specitied nibbe Jump in the current bank. The Pan sup sae [DC chars when a uni PC. s- Pent (: in 2 4 alae] af instruction 1s followed by a BANK 7 6 3 ‘1 0 instruction. PioP10P10P3 P2PsPo [Jump in the current page modified Ea reli PCr to 0 < (EAC) STACK & (PC) + 1 PCI to 6 C2P addr | Call subroutine in the zero page /PC{ to 0 «- 0 PCS to 2 «~ PaP2PiPo STACK « (PO) + 2 1 1 ° CAL adr feat eubcoutin inthe zero bank |PCIE 10.0 OD, ’ Ps 3 co PP Po a PC e (STACK) z Pore (C13) 1 “un [Pee SPP) Lt | ‘ feted] ee oe Branch on AC bi. Immediate ata Tpc7 4, 9 jto and ty is appended to BA. 1 Bat addr [which is followed by the program ares PaPaPyPo it P6 Py Jcounter branch address Po to Pz. |ACt = Branch on no AC bit. Immediate }data to and ty is appended to PC? 0 0 — 1 A i] NAL addr |BNA, which is folowed by the | P7PgPsP4 P3P2P1Po i Ps | Pa Pt [program counter branch address |AC} = 0 Po to Pr. No, 3653—12/24
LC65102A, LC65104A eee rs
Description
[7 [on [os [oe [oe J oe [os [| Branch on M bit. Immediate data Por too = 1 |t to and ty is appended to 8M, 1 9 4} BMI addr Thich ie flowed by the program teres Ps Pa | Pe | Pt eounter branch address Pg to P7 Branch on no M bit. Immediate data to and ty is appended to | PC7 tp. 9 & 0 1 0 ts BNMt addr |BNM, which is followed by the | P7PgP5P4 PaP2P1Po it Py Ps Py Pi program counter branch address | [M(OP tito] = 0 Po to Pr, Branch on port bi Immediate — [PCr to 9 = data to and 11 is appended to BP, | P7PgPSP4 P3P2P4PO it a} oy 4 | which is followed by the program’ |[P(OPLtstg)) = 1 or 7 | Pe | Pr | Po jeounter branch address Po to P7. |(GP(DP,t;t9)) = 1 Branch on no port bit. Immeiate |. asta to and t1 is appended to [CZ t0.0 1 BNPt addr |BNP, which is followed by the eran oe « & Pa 5 h . program cuter branch wets | SPP Ni) = PC? to 0 BC addr PrP6PSPa PaPePsPo it crs f PC? to 1 1 BNC addr |Branch on no CF PrP6PSPa PaPaPAPo it Py Py cred PCr tog = i of 4 af 4 ! FrPePss PaPaPiPo i Pr | Ps Pa | Pa Pt POF to 9 0 1 Branch on no 2F PrP6P5Pq PaP2PsPo it Pr P3 La Branch on flag bit. Immediate cata ng, M1. ng. and ng is appended to }PC7 to 0 — a4 1 BFq adér |BF, which is followed by the P7PgPSP4 P3PaPIPo it Pr | Pe Pe program counter branch address jbFn = 1 9 to Py. Branch on no tag bit. Immediate }data no, ny, np and ng is PC? to 0 1 i Ny add | appended to BNF, which is PrPGP5P4 PyP2P4Po if ps Pa followed by the program counter |bFn = 0 ‘branch address Po to P7. JAC (P(DPL)] or P(DPL) or GP{DP) — '5P8 bit |Set port bit. The coments of [POL 8180) or register E are lost, GP(DP,ByBp) + 1 [Reset port bit. The contents of P(DPL B1B9) or 88 feat Ew le PCOPE 160) = 0 el feted fe fet fafet Te | ‘Set control repister bit CTL, 83828189 © 1 o SCTL bit Ice rate 2 lor MSTEN <= 1 80 Reset control register bit CTL, 83828189 + 0 1 o RCTL bit Vee nate 2 lor MSTEN «0 l=] [tle] o 8 a CC Notes 1, After LI and CLA instructions are executed in succession, subsequent instructions are NOPs. 2. BsB2B,By = 0000B to 1000B eee No, 3653—13/24
Table 1. Magnitude conditions Table 2. Magnitude conditions The following user-specified mask options are available. The 1/1 or 1/32 frequency divider ratio mask options can be selected as the default ratios following a reset. The 1/1 ratio is used for the 390 kHz to 4330 kHz external clock input or the 400 kHz ceramic resonators. The 1/32 ratio is used for the 4.19 MHz crystal or the 4.0 MHz ceramic resonators. Port C and D outputs can all be cleared to 0 or set to 1 after a reset. detector circuit as shown in figure 1.
Figure 4. EPROM address map The memory locations 800H to FFFH of LC65102 should be cleared to 00 during development.
00 Ceramic filter
01 Crystal oscilator
10 Rlosorved (do not use}
11 External cook
1 HIGH
1 Yes
1 AC zero-cressing input
Figure 5. Bit allocation
Figure 6. 1001H
01 MOS totern-poie
Figure 7. 1002H
01 MOS tctem-po's
Figure 8. 1003H
01 MOS totem-pole
Figure 9. 1004H
05 MOS totompole
Figure 10. 1005H
01 MOS totes polo
Figure 11. 1006H
01 MOS totempoie
Figure 12. 1007H The development system available for the LC65102A and LC65104A comprises the following aids. EVA-850 main unit and evaluation chip board) for program evaluation as shown in figure 13.
- MS-DOS is a trademark of Microsoft Corporation.
- Upgrades of the EVA-800 or EVA-850 emulators are indicated by an alphabetic character appended to
Figure 13. Development system components
LC65102A, LC65104A ESSENSE Evaluation Notes The following guidelines should be observed when evaluating programs for the LC65102A/LC65104A using the LC65999 and the LC6SPG10X. Selection RAM capacity The RC and RC2 pins are used to select RAM capacity. The LC65102A has a 128 x 4-bit RAM, and the LC65104A, a 256 x 4-bit RAM. The evaluation chip can have either. Stack nesting The STC pin is used to select the number of stack nesting levels. The LC65102A and LC65104A support eight levels of nesting. Ports C, D, E and F output configuration Ports C, D, E and F have 15 V breakdown-voltage, medium-current drive I/O circuits. The C/FLSEL pin of the evaluation tool is used to select the I/O configuration of ports C and D which can be either p-channel, high voltage or n-channel. Port F output drivers PFO to PF2 have normal breakdown voltage I/O circuits when masked for the totem-pole configuration, and output driver PF3, in either totem-pole or open-drain configurations, Mask options Oscillator circult . The resonator should be connected to OSC1 and OSC2. The oscillator type is selected by setting jumpers on the evaluation board. The simulation chip is identical to a volume-produced chip. Port C and D after reset The four bits of port C and D can be specified to go either all HIGH or all LOW following reset. The CHL pin is used to select the level for port C, and the DHL pin to select the level for port D. Watchdog reset function Specify whether to implement the watchdog reset function using the timer or not. The WDC pin is used to select or deselect the watchdog reset function. AC zero-crossing detector Specify whether or not to implement the AC zero-crossing detector input circuit on PF3/INTO. The ACZ/INTO pin is used to select or deselect the AC zero-crossing detector. Open-drain or totem-pole output Specify either totem-pole or open-drain configuration for each output. All evaluation chip ports have n-channel, open-drain outputs. Pull-up resistors of 10 kQ should be connected to the ports on the simulation and evaluation chips. Pull-up resistor configuration The evaluation and simulation chips have open-drain outputs which require external pull-up resistors, When the outputs are LOW, there is continuous current drain through the pull-up resistors. No external pull-up Tesistors are required and only leakage currents flow in the output transistors if the totem-pole output option is selected for volume-produced chips. No. 3653—19/24
result, wiring capacitance may lead to unstable oscillation. The external components should be trimmed as necessary to obtain stable oscillation. engineering samples ES and commercial samples CS. evaluate circuit operation over the entire supply voltage range of volume-produced chips. The guaranteed ambient operating temperature range is 10 to 40 deg. C. BANK followed by JMP instruction. Program does not exceed 2 Kbytes for the LC65102A or 4 Kbytes for the LC65104A. Figure 14. Oscillator circuit
- CL is the resonator’s built-in capacitor value
- Three-pin resonator with built-in capacitor
LC65102A, LC65104A PROGRAMMING NOTES The following guidelines should be observed when developing programs for the LC65102A/LC65104A. System Clock Functions System clock mode The LC65102A/LC65104A provides three software-selectable clock modes. Clock modes cannot be changed if the 1/1 frequency divider ratio after reset option is selected. * Clock 1/1 mode (tye = 0.95 us) * Clock 1/2 mode (tye = 1.90 ps) * Clock 1/32 mode (tye = 30.6 Us) Notes 1. These values apply for a main clock frequency of 4.19 MHz. 2. A clock signal must be supplied at system startup. System clock switching mode The system clock source is selected by the clock mode flags (CMF), a two-bit location in the control register. The default system clock frequency divider ratio after reset is 1/32. |__| ain cock x 1/82 (defaut on reset) i a Notes 1, Ensure that the clock oscillator is stable or an external clock signal is applied before changing modes. 2. The mode change occurs at a maximum of 64 main clock cycles after writing to the clock mode flag. A delay should be allowed between a mode change operation and a HALT instruction. 3. The system clock frequency divider ratio cannot be changed if this ratio is selected as the power-ON default. Standby Modes HALT mode The HALT command can be used to override the watchdog timer, which halts operation, whether the WG2 and WG3 flags are set to 1 or not. This enables release by either a HIGH on PB3/START or the interrupt release signal. Entry “Issuing the HALT instruction when the standby control register SLPF flag is 0 invokes HALT mode. However, it is equivalent to a NOP (no operation) instruction under the following exit conditions. «Reset * The PB3/START line goes HIGH while WG2 = 1. * The interrupt release signal goes active while WG3 = 1. * The 14-bit frequency divider overflows. Normal operation commences after a maximum of 0.5 seconds if a 4.19 MHz clock is used. No, 3653—23/24
LC65102A, LC65104A HOLD mode Entry Issuing the HALT instruction when the SLPF flag is 1 invokes HOLD mode. A single NOP instruction is issued prior to entering HOLD mode. The WG] flag must be set to 1 before entering HOLD mode to enable release by a HIGH on PB3/START. The timebase clock source should be set to 1/128 of the oscillator clock. Exit HOLD mode is exit when one of the following conditions occur. + Reset * The PB3/START line goes HIGH while WGI = 1. Watchdog Timer The watchdog timer is used to detect program runaway and generate a reset. The following guidelines should be observed. * Write a routine in the program that resets the TBF flag periodically before a timer overflow occurs. It should be written so that the instruction that resets the TBF flag is not issued at the same time as the timeout interrupt request signal is generated. + Select a timer divide ratio ; + If the timebase interrupt request flag TBF is 1 prior to invoking HALT mode, a timer overflow will initiate a watchdog reset and an exit from HALT mode. To prevent a watchdog reset when HALT mode is exit, either reset the TBF flag immediately before issuing the HALT instruction or set the TBF flag and the WG3 flag (interrupt-invoked HALT exit). Interrupts The following guidelines should be observed for interrupts. + Interrupts are enabled using control register bit 5. * Each of the 5 interrupt vectors is allocated its own enable flag. The desired interrupts can be enabled by setting the appropriate flags. It is not possible to access multiple bits simultaneously using the SCTLO to 7 instructions. All flags are cleared when a reset occurs. + Flags can be cleared by issuing a RCTL instruction for each flag. + Invoking HOLD mode disables all flags. They should be enabled after exiting HOLD mode. + The interrupt flags are configured as a pseudo port. Individual flags are selected by setting the corresponding accumulator bits to 1 and copying them to the interrupt request register. When a BANK instruction is issued after an IP instruction, the flags are cleared. When a BANK instruction is issued after an OP instruction, the selected flag is set. * All interrupt flags except timer 1 flag are cleared to 0 after a reset. + All interrupt flags are cleared to 0 after HOLD mode is invoked. + The serial 1/O flag SIOF is cleared to 0 when serial data transfer begins. + Each interrupt flag including the interrupt enable flag should be set individually following an interrupt. + A BANK instruction followed by a SPB or RPB instruction does not access the interrupt request register, No. 3653—24/24