LC5851

LC5851N SANYO | Alldatasheet

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+ A wide range of allowable operations Supply Option Cycle Time Supply Voltage Range EXT-V Vss2=-4.0 to -5.5V 400kHz Ceramic oscillator EXT-V Vss2=-4.0 to -5.5V 200kHz Ceramic oscillator EXT-V Vss2=-2.3 to -5.5V 65kHz Crystal oscillator EXT-V 122us, 244us Vss2=-2.0 to -5.5V 32kHz_ Crystal oscillator 122us, 244us Vss2=-2.6 to -3.6V (Note) | 32kHz Crystal oscillator 122us, 244us Vss1=-1.3 to -1.65V 32kHz Crystal oscillator (Note) If the backup flag is set, pin BAK is connected to Vss2. (For further details, refer to the User's Manual.) Notes for developing an LC5800 series microcomputer-used system The low current dissipation is a distinctive feature of the LC5800 series microcomputers. However, it is not easy to determine the total current to be dissipated in an LC5800 series microcomputer-used system by actual measurement when you develop a software, because much current flows in the peripherals of the evaluation tools. For a system which require low current dissipation, check the current dissipation using an evaluation sample before mass-producing the system. SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 00793JN B8-0421,22,23,25/7310JN/2280TA.TS KAWA No. 3341-1/31

+ Micro-current operation Only micro level current is needed to operate the LC5851N if the HALT function is used efficiently. + The actual current reguired, however, depends on the program structure. The following values are typical for normal clock programs, 1,5uA (typ) ... Li specifications (3.0V supply) + The terminals are capable of driving various types of LCD panel. (25 terminals) . LCD panel Number of LCD segments 1/3 bias - 1/3 duty 75 segments 1/2 bias - 1/3 duty 75 segments 1/2 bias - 1/2 duty 50 segments Static 25 segments + The built-in segment PLA circuit is capable of joining the LCD driver outputs to any patterns on the LCD panel without software. + A number of input and output terminals are provided. Input port: 2 ports/8 pins (With a chatter removal circuit) Input/output port: 2 ports/8 pins Output port: 1 port/4 pins (Also used as the pseudo-seria! output port) Control output terminal: 2 pins « The LCD pane! drive output terminal can be switched to the output-only port (mask option). + An initial reset terminal is provided. + ROM: 1024 x 15 bits + RAM: 64 x 4 bits + Built-in oscillation circuit for crystal oscillation or ceramic resonator oscillation. + Built-in voltage doubler/halver circuits for the LCD power source. + Form of shipment: QFP64 (QIP64) or chip Software Features + As many as 79 instructions, + Binary addition/subtractions and logical operation. + Input and output instructions in 4-bit units. + Conditional branch instructions. + 8 working registers and operation instructions. + LCD driver data transfer instructions. + 4-level subroutine nesting (common with interrupts) + Interrupt function ... External source: 2 (INT terminal, input ports S and M) Internal source: 2 (Timer, frequency divider circuit) + HALT/HOLD release functions ... The HALT release is caused by the same elements as in inter- rupt. + Built-in 6-bit programmable timer. + Built-in 15-bit clock frequency divider circuit. + All instructions are executable in one machine cycle. No, 3341-2/31

Application Development Tools + Relations between power specifications for cycle time and evaluation chip Cycle |Oscillation| A9 Specification | Li Specification EXTV Specification | one Time |Frequency lop(typ) top(typ) loo(typ) tpo(typ) | Evaluation Use Use Use /1.5V pov | YS | pov | YS | 5.0v | chip Board BDH = [x] = |x] = [To] fevatuation owe | x {= tx | = jx f= fof [ene es.sa5mre [| x | = | x | = | oO [io~awa | 0 | 20~80H4 evaluation 32.76Bktz | O | 4~20uA| O | 2~20uA| O | 8~a5uA | O | 15~60uA | Chip Board: emit [0 [2~eea] O Li~aualo | | o | __|tesest Table 1, Relations between power specifications for cycle time and evaluation chip. Note) The Ipp (typ) value is determined by the contents of the software. + Software support tool Cross assembler and mask option selection program for MS-DOS based system (1) Cross assembler :LC5851, EXE (2) Mask option selection program :SUS851N, EXE + Hardware support tool (1) Evaluation chip :LC5895HII (2) Mask option controller :DCB-1A (3) Evaluation chip board :TB5851 (4) Evaluation board 2EVA-520 (EVA-510) (5) Control ROM :SCR5851 + Development support too! system LPT y ee RS-2326 =k Pore SS Serial interface : LAUT co TORK f Personal computer EEE . I MS-DOS based syst rare sen pots fal Qa ( ystem) isolay lamps aun (near EVA-520 ae 4 (Eva-510) (OC LED cable EVA chip ePN ZO socket (160 cabte) M277 Ip, ——v (Lc5895HI1) secret LU [Arg TH o> a2 PAI 76) Cy ses 24s Be — IF poet (/ . PHS 2y vy, 785851 34PIN Note: These cables must not be connected on the cross or reversely. No, 3341-3/31

Equivalent Circuit Block Diagram 1/0 Bus 4bit Port Ta, if RAM 3 VoBt~voB4 eax |S Lerma] | 2M Pon z KX 18 bi (4) voa fal Gi Ga ee Voa1~V/oa4 il —_— (fro? ] ZORS i Pi~pa ir Tet ek 7 a System bus 15bir a | or M ——— ; [| Predivider oe Co N+ | | 7am (15 steps) Mi~Ma C| it om | F ISCF ISCF |B0F | SCF] ai { ISS re TESTA O-—~ I osc osc OUT Segment PLA 5 ore Oo ven oes cuP2 O—— ig!

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LIGHT ‘Sst —0 Vss3 84464 b b g 12.3 \\_Seament 2 ALARM LIGHT +O BAK CoM Ac : Accumulator cr : Carry flag ALU : Arithmetic and logic unit BCF : Backup flag INT CTL : Interrupt contro! circuit SCF1 : M port flag PC : Program counter SCF2 : STS3 flag ™ : Preset timer (8 bits) SCF3 : S port flag IR : Instruction register SCF4 —: INT signal change flag HALT —: Intermittent control circuit SCF5 —: Timer overflow flag sca : System clock generator 615 : Content of 15th step of divider sTst : Status register 1 SCF7 _: Overflow flag of divider sTs2 : Status register 2 STS3_: Status register 3 Application Examples + Portable equipment (timer, watch, clock, hand-held calculator, and thermometer) + Audio equipment (electronic controller, electronic tuning controller, and clock) + Home appliances (remote control, and timer control) + Telephone (dial/clock display) No. 3341-4/31

Application Circuit Examples. (1) Typical application circuit for the (2) Typical application circuit for Ag specifications the Li specifications (1/3 bias - 1/3 duty) (1/2 bias - 1/3 duty) com eo com veo | et — Led come as 15 duty) Pz 00M2] Wy bias 35 dut eSoft 3 cowat—] caves ssa) a Oe ee ‘SEO OHHH bend Lio ol or I} por oot OHHH 3 segment a seanes kay maton ‘voo} key matrix oD] st vss} st vssi 5S s2 — $2 ss TESTA| oy | 33 se o s4 VSS2} Se vs vO 42 vssa| {| 10A2 vss3| vo 1943 VO 54 gues 10a curt . by ES 2. 760KKe 5 22.7608 eid f lose out 4 ose out “ Way €) * Pau £) me € vo a1 LS "9 82 toe woes 1863 woes ® 138: 8 oo c ae vo RES IGHT. r res Lion Bo ox © om Unit (capacitance: F) WeUT OUTPUT PORT 10 AI~a, OBIS INPUT PORT Sima atin OUTPUT PORT Pi~s (3) Typical application circuit for the EXT-V specifications (1/2 bias - 1/3 duty) vor comyp—] LED

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Terminal input? | Circuit i Function ft Re Name {Output | Configuration | “ Status after Reset Used as the reference clock ond system | (@ Terminals for erystal oscMator OSC IN } clock. (XT option) @ Terminals for ceramle cesonator | ‘esciltator (CF option) ' The CF option is avsilable only OSC OUT | for the EXT-V specification. | Useo as an oscllintion phase compensating veo capacitor by comecting it to OSCOUT of J { oscin. ra | Used tor enip onty, ‘ee | i woo Inout-only port Selection of *L" level Hola Tr. [Translator for pull-down st § | Contains » O10(32ms), 98 (Sms) or 6 (28) | Chatter-removal time is either O10, | resistance Is ON. 8 | enattorromovaleirut, PLA mass option) | 98 oF 8. 2 iM *The values are for 32.768kHz crystal oscil- | GN incicates the output at the Nth $3 -§ | tation. step of the frequency divider $4 7 3 circuit. yoo Input terminals for writing date in RAM, Selection of "L" level Hold Tr, Transistor for pull-down Mi § resistence Is ON. me Input i inpul M3 p “. ma (es 3 oo | Ieutvoutput port with mode switched by VvoaAt Instructions to perform the following opera: tions VO A2 Input/ yoo! + trout port: Weltes date in RAM. VOA3 — J output oo ® Cutout port: Outpute dete from RAM. VO Aa ' woo Output-only port "H® oF "L" output (not PI Vinea). P2 1s voo Control Input port for external interrupt | Pultup resistor bh, request. ® Puit-cown resistor iNT Input © Fai tigger a @ Rise tener (2 wnoty voltage terminal for the loge Backup flag We eet/reset fection of USI circu depending on the power BAK In the Lt specitications a capacitor Is source option, Drovided between BAK ond VOD to prevent malfunction et Ue log section, oo ‘Oviput-only port, *U" output Suitable for delivering signal to drive high-current etiving. LIGHT Oviput-only port. © Modvloting signal (AKHE, 2aHe, |°L" output voo Able tooutput 4kHz-2kHz or 4kH2-TkHz modu~ Nonmodulation) lating signals according to instructions es | @ Modulating signal (éki2, TkH2, ALM | ya tmadiate be Novmesulton The value Is for 32.768HE crystal oscile lation. System reset terminal. woo Sets the program counter to eddress 00, "Ht" level signal should be input more than No, 3341-6/31

[wo | __ ET auonly voltage Termine * Connection of external device varies ac carding te the mask option: The (-) | © Ag soeciticettons Vss3 terminal is connected to Vsgi for the Ag | @ LI specifications Vssz specifications. © EXT-V wecitleations ‘The (-) terminal is connected to Vgs2 tor Vsst other specifications. + Terminals other than the (-) terminal are used as the source supply for the LCD ative, CUPI ‘Connection terminals for voltage doubler Cup2 (hatverd capacitor. Output terminals for common plate of LCO |@ LED ériving specitication panel > Static Use of terminals veries. 2 1/2bins-120uty + Uabias-1/30ut7 woo + 1/3bla8-1/300ty [| sa | tadury| Yaduty | |@ alternating treqvency seciti Fe Ceation (Tha following values re com fF com [Oo | o | o | for the 32.768kHr system clock.) come Output vssa come [=| oO To] |} te com3 CoM es SO pe ves Frequency Mew [Gree +The values ere for 32.760KHE crystol oxcillation. +172 0F couble of the Treauercy can be used cenending on the PLA, LCD pane! tegment cutout terminal. © ouput tor Leo Full lighting (for LEO) + The terminal can be switched to the out- | @ CMOS output port “H™ Level (except for put-only port by musk option (See the | @ Pch open drain outout cot | LCD) eACTIVE state Ontion instruction Sheet for the terminals | Options @.@, and @een be select- woo | to be ured.) ed In bit units, 7 + During the LSI system reset, the static | | fighting sigest ts ted to COMI to COMI Segment and to each of the LCD segmont outputs, driver fand sll LCD pane! segments go on. (Only Output + The segment PLA system is used to provide } ‘ny layout of the LCO panel. or 3 IF +The valves are for 32.769KHx crystal termi- food osciltation, nals) vss2_ “359 LCO panel segment ovtout terminat. Dovtout tor cd Full lighting (for LCO) +The terminal can be switened to the output | @CMOS ovtout port THY level (except for port by mask option. Options D and @ can be selected in| LCD}-ACTIVE state. + It the LSI system Is reset, the static [pit unite. vou. lighting signal is fed to COM! to COMI and 7” to ech of the LCD segment outputs, and 211 LOD panel segments go on. Segment Ik + The segment PLA system ie used to provioe driver any layout of the LCD parel. + The velues aco for 22.769KHE erystel (For i | oscnstion. other vss) termi- id | nats) Teer | Terminal for test (rot used by the weer) TEST TESTA | | [Terminal for test apply () voltage. i ‘Auriliaty supply voltage terminal, Do not Remarks: d@ Ag specifications: Vss1 Li specifications, EXT-V specifications: Vss2 No. 3341-7/31

Pad Assignment on LSI Chip Reference data for the shipment of chips seasz22 Chips size: 3.85mm X 3,48mm zs oecema-bGooccocoe Chip thickness: 480um 2222000 a se SSSS5s Pad size: 120m X 12ym) —s TesTA(O DOGO0OGCORO0oR0Gn0D Ovo Test| oO 20 10 o}s3 cur!} oO Oss oup2 | 030 O | uicet s2/O O} ALM sila D | Vss2 (Yoo) | 0 Oj Vsst ose-In| O D | Bak 10P | 0 Pad No 1D | Voo ose ouT] 0 + D | Vss3 com} o 0 0 | coma o 0D {coma o o seoment| | 5 4 OD a a test|O 50 60 test] OOODOO0000000000000 SEGMENT Package Dimensions 3057 Package Dimensions 3026B (unit:mm) (unitimm) — 20.0 — 19.6 14.0 ———~ 4.0 10 0.8 0.38 | 10 08 0.35 0.15 fl

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LUT | s | we ee : : —4 — = Era = SS — | 7 Lamm TDLLLALNUAUPYOURU APUG UT LHS = o 6 DUUUUGUUUUC TONED SANYO: QIP64A "as SANYO: QIP64B ‘has Please contact your local Sales Representative if you plan to use the QIP64B, (Special packages need to be specially ordered.) No. 3341-8/31

ree | [ita | hae Fa 64Pin No.| No Name | _x<um)| y(am) |64Pin No.| No Name Ee | a | 2 [eax | mee [eas sf 6 [osc-our | =1ma | 5 | [fe pvest me a ff [com | irae | aes [maa [vest ame ee fifa seco | ree a8 | ALM es LIGHT | tre | tos [ia fo [seeos | iva | 821 | i 7 [se |e | as |e | at | secoa | = a728 | 1001 | | je [ss fama | tes [| ae [rest | 1728 | 1365 | [oes vom |e 6 | jo [yong |e | ise |S ne [ste |voas | tose | tas |i? | a8 | secon | 1038 | 1548 | i a [voer | eee | ts | te | a [eons | 088 | 1508 | [ose [vo ee [08 | [|e 8600 are | Mise | | | 6 [vos | see [eas | a | [seein | ase | 505 | | | 6s [voea [we [sas | ai oo [sects | ara | 505 | | [7 [res | to6 | sas |e | ot [seore | ise | 1585 | [cae et) ee fe sess |e fe | 1 jas | tas | 25 | 83 [seca | 2a | 1868 | a_i [Pe = far [ps z ma | =vass | is | ae | oo [seoei tae | 1545 | TESTA 56625 | 4 {2 [ours | 176 | as || 63 | seed | 5 [30 [cure | =iree | tos | | oe |sec2s tea | et | p 8 [a [se ire | eas | | 5 [coms | tee | 088 j 7 [2 [si | mime | gus |e | 66 [come te | 265 | a [8 [3% [oscan | =a | ef TP + Pin 24 on the QFP64 (QIP64) package is NC. (Use the NC pin in the open position.) + The pad coordinates are determined with the center of these chip as origin. The values for (X, Y) are the coordinates for the center of each pad. +» Use the terminals for test in the open position. + When selecting the chip, connect the substrate to VDD. + When mounting the QFP64 (QIP64) package on the board, do not dip it in solder, No, 3341-9/31

Oscillation Circuit Options Unit (capacitance: F) a XT oscillation) fo + The 10P terminal can be used only for chip (32,768kH2z) ose Wy. selection. co ow XX BAKFLAG ge a out osc Yoo out toy e top Fd top 20° XT oscillation v 0 + The 10P terminal can be used only for chip (65kHz) ee i — & aaxetag| Selection. a + Used for the cycle time 61 version. oso SM Voo ouT pow) be Rd yop 1p 20P CF oscillation og ose IN { }—>e ouT Co grt cd | ri| osc out Input Port Options Option Hold Tr + The Hold Tr option is used to reduce the current required, for example, for a pushbutton switch for $1, and a slide NON switch for S2. + For example, the "L" level signal can be ii POFLAG| held after the pull-down resistor is set to ON for a short period of time by software in case of open type of input port. Open + Pull-down Tr can be used as a pull-down resistor. + Pull-down Tr can be set to ON/OFF by NF PoFLaG software. "L" level Hold Tr can be selected for ports $1 to S4 and M1 to M4, * Port S has an independent chatter-removal circuit (in bit units) that operates at @10 period, O8 period or @6 period. * Port M has a chatter-removal circuit that operates upon of the HALT release request signal. With this circuit, chatter at @10 period, @8 period or @6 period is removed when three terminales of M port are in the "L" level and any signa! to the other terminal changes. Note that @N indicates the output at the Nth step of the oscillator frequency divider circuit. If a 32.768kHz oscillator is used, @6...About 2msec, @8.,.About 8msec. @10...About 32msec. No, 3341-10/31

LCD output options for the LCD driver, the CMOS output port and the Pch open drain output port can be selected (the Pch open drain option can be specified only for the predetermined 3 bits). LCD drive + Terminal for LCD segment drive. +The drive is selected according to the LCD driving system specified separately. The LCD driving system is common to all terminals, and can be selected from among the static, 1/2bias-1/2duty, 1/2bias-1/3duty, and 1/3bias-1/3duty methods. CMOS output port |+General-purpose CMOS type output port Pch open drain *General-purpose Pch open drain type output port output port It's usable according to the PLA option for the predetermined three ports. Alternating waveform for the LCD driver for LCD output is generated by hardware logic. Segment PLA Circuit A schema of the structure of the segment PLA circuit is shown below. Data Bus (05US) if I Segment PLA Circuit (SPLA] Frogrant \\\\controt} | oata (oo) Bec] YS.) \\ = frewory| Yeireut | emer PRS] 251 18 wom) | f\\crc) | |iram a 83] /)88|_/| 8 The contents of the Data Memory are sent through to the LCD Latch Circuit for display as is or after being decoded by the Data Decoder, The PLA Circuit is used to rearrange the input data to output it to the LCD latches. With this circuit, data memory can be edited to suit to the LCD panel specifications without software processing. The PLA circuit can be specified by the ROM for PLA. The user must release the ROM for PLA with the program ROM. Output Port P The following two modes can be selected by software: 1) General-purpose output port 2) Pseudo-serial output port The time chart in the Pseudo-Serial mode is shown below: wl AL Fo+o+to+ototetotototsteto Ac=0 AC=5 AC=2 AC=1 P Whee Saar BATA Lat 1 tor Datars it 3 tor DATARS ma oan eee oe rs Pa H waters Te: Cycle Time D , @ «sss Initial processing for serial data transfer. @,©,@,@... The first and the second bits of the RAM data are output to ports P1 and P2, respectively. As shown above, the RAM data can be transferred in 1-bit serial data form every two machine cycles. (For this, however, it is necessary to process (e.g., replace) the RAM data every 4-bit transfer.) No. 3341-11/31

The following frequency divider output can be used directly as alarm output: 1) Output signal either at 43, 64 (or 05) 2) Any combination output signal at 910, O11, 012, 913, 014 and 915. 3) Modulating output signal of 1) or 2). These signals can be output by software. @N indicates the output at the Nth step of the oscillator frequency divider. Operation Mode of Internal Logic + The following diagram shows the supply voltages and the operation levets of internal logic. ‘Ag specifications (1.5V supply) Voo [ TP | Input/ E> — : Output Internal Lop Driver ES Circuit Logic \\ JL cag Vast Vsse Vss3 Li specifications (3V supply) voo CF aoe eee a ee | input/ Output Internal LCD Driver => Circuit =] Losie vss2 O Vss1 Vssz Vss3 pak The BAK terminal is connected to Vgsi or Vss2 by software. It is, however, connected to Vgs2 after the initial clear is issued. EXT-V specifications (3 to 5V supply) — — Input/ Out Internal Leb Driver E> utput Logic Circuit a vssa [J Vss1 Ves Vssa (=BAK) No. 3341-12/31

+ The level of voltage applied to BAK is shown below. BAK terminal level Power input/output « Relations between option port Usstrvssay and YSS3 EXT-V Vsse vssz Vo0-Vssz Vsso~Vssi x 3 (13 bies) * The LCD output used as general-purpose port is included. + The backup mode is called by setting the backup flag by software, and the normal mode is reinstated by resetting the flag. Backup Mode 1) The backup mode is useful with Li specifications to prevent malfunctions of LSI circuits under heavy load, An example of a time chart is shown below. Power source option ... Li specifications WO ee Voo an —_ BAK Vss2 Initial Backup Backup Heavy Battery clear flag flag load/ recovery Backup flag reset set ON time > reset . Heavy Load Operation Timing + To prevent a sudden change at BAK, a smoothing capacitor must be inserted between BAK and VDD. 2) In the Ag and Li specifications, the backup mode is called with an initial clear. The reason is: Ag specifications .. To shorten the oscillation start time of the crystal oscillator circuit. Li specifications ... To start oscillation by applying supply voltage to the oscillator. Be sure to reset the backup flag to return to normal mode, after the initial clear is released. The backup-mode-related elements enter the following. ti Set Brought to Vss2 level. Became EXT-V Reset Connected to Vss2 (Fixed). [As owe | Operation of Backup Flag at Initial Clear Mode 3) The current required in backup mode is 20 to 40 times that for normal mode. Therefore, be sure to reset the backup flag except when necessary. For the EXT-V specifications, it is unnecessary to set the backup flag. No, 3341-13/31

There are three functions for resetting internal logic: 1, On-chip power-ON clear function ... Use of this option can be determined by the mask option, 2. Reset terminal RES i ‘i . 5 fied k opti . 3, Simultaneous operation of S1 to sal Either option 2, or 3. can be specified (mask option). These reset functions are explained below. 1) Built-in power-ON clear circuit The initial clear circuit provided in the microcomputer automatically operates and resets internal logic when power is turned on. This function is very useful in that it can be activated without external devices, but it has the two disadvantages listed below. It is, therefore, recommended that this function be used with other reset functions or that other methods be used according to applications. a) The circuit may not operate under certain power-rise conditions during the power-ON sequence or due to chatter. b) Malfunctions may take place due to pulse noise in Vpp port or a sudden change in status. One of the following two reset options can be selected: INHIBIT: The built-in power-ON clear circuit is not used. Malfunction due to pulse noise in Vpp port can be-prevented, NORMAL ACTION: The built-in power-ON clear circuit is used, This option should be selected only when pulse noise in the power does not affect. Simultaneous ® push of St to S¢ 7 LL +_ RES Power-ON @ NORMAL To logic unit of clear Im ACTION ) microcomputer circuit \\ r (reset signal) i i ‘ Vgsa or V: Initial clear signal 'ss2 or Vssi Vgg2_ INHIBIT 415 or Vssi The built-in power-ON clear function in LSI circuits may not work under certain power-rise conditions. Use an external reset switch (the reset terminal or simultaneous operation of $1 to $4). 2) To activate the initial clear function completely with the reset terminal, the following conditions must be satisfied: 1 Oscillation must be normal. 2 The "H" level signa! must be applied for more than 20Qus. An example of the reset circuit is shown below. o Voo Supply Voltage RES L5851N . bs448 For Preventing spike pulse Vsse Oo Reset release os¢-out EET ccc t No. 3341-14/31

Even with this circuit, the above two requisites may not be satisfied due to the power-rise conditions or oscillation start time, and therefore the power-ON clear function may not work. To prevent this, an external reset switch should be used. 3) The same requisites as in 2) must be satisfied for the simultaneous operation of S1 to S4. If the timing for applying signals to $1 to S4 (i.e., the timing for signals changing from "H" to "L" levels) is not even, the microcomputer starts operating according to the built-in program. Option List Power Seiect * Ag specifications * Li specificaitons + EXT-V specifications LCD lighting * Static Select "non use" if all LCD outputs are + 1/2Bias -1/2O0uty to be used as general-purpose ports. * 1/2 Bias- 1/3 Duty + 1/3 Bias - 1/3 Duty + NON USE LCD frequency + SLOW (OSC/2048) *TYP (OSC/1024) *FAST (OSC/512) "L" level S PORT + Use “L"-level hold Tr HOLD Tr (Si-4) + Non Use “L"-level hold Tr M PORT + Use "L"-level hold Tr (M1—4) + Non Use “L"-level hold Tr S,M port chatter- + SLOW (OSC/1024) removal frequency “TYP (OSC/256) _ sFAST (OSC/64) INT Input * Pull-up. terminal resistance + Pull-down + Open Signal + Rise change + Fall External reset * RES terminal + Simultaneous operation of $1 to $4 Internal timer clock + SLOW (OSC/512) +FAST (OSC/8) ALARM signal modulating} *TYP (OSC/8, OSC/16) reference frequency | « SLOW (OSC/8, OSC/32) Built-in power-ON + Use clear function * Non Use Oscillator configuration * 32.768kHz crystal use * 65.536kHz crystal use + Ceramic oscillator use Cycle Time + SLOW (OSC/8) Select SLOW at 200kHz ceramic resonator + FAST (OSC/4) mode. No, 3341-15/31

Absolute Maximum Ratings at Ta=25C, Vpp=0V [tem Symbot_| Condition/Terminal Maximum Supply | Vss1 —7.0 to +0.3 Vv Voltage Vss2 —7.0 to +0.3 v Vss3 —8.5 to +0.3 Vv Maximum Input Vint Vss2 Vv Vottage ees to $0.3 Maximum Output | Vout! ALM, LIGHT, P1to4, CUP2, (vss? to +0.3 v Voltage OSCOUT, TEST, /O Al-4, VO —0.3 . B1-4,(I/0 A, 1/0 B: output mode.) Vout? | SEGOUT, COM1-3, CUP1 (vss3 to +0.3 v Operating —0.3 Temperature Topr —20 to +70 c Storage Temperature Tstg —30 to +125 c Allowable Operating Conditions at Ta=-20 to +70C, Vpp=0V Supply Voltage | Vss1 5.5 —13 / Vv Vss2 Joavre crystal mode —6.5 —2.0 Vv Vss3 8.25 —2.0 v Supply Voltage Vss1 5.5 1.3 v Vss2 Josie crystal mode 5.5 2.3 Vv Vss3 8.25 72.3 v Supply Voltage Vss1 5.6 17 v Vss2 ] External input mode 5.5 35 | v Vss3 —8.25 3.5 Vv Supply Voltage Vss1 —5.5 2.0 Vv Vss2 Jer mode (200kHz,400kHz,800kHz)| —5.5 -4.0 | Vv Vss3 8.25 4.0 v Input "H"-Level | V 0.3x o}]v Vosges St YM ] All Input. terminal (Vaso CIN Input "L"-Level | Vitt except OS Vss2 0.2 | v Voltage (ss2 Input "H'-Level Vin2 0.2x 0 Vv Voltage " ] OSCIN terminal, (seo external input mode Input "L"-Level Vice ‘np Vss2 (08% Vv Voltage Vss2 Operating fopg! Vss2=—2.0to —_OSCIN/OSCOUT 32 66 | kh Frequency —5.5v 32kHz crystal, Fig.2 Operating fopg2 Vss2=—2.3to OSCIN/OSCOUT 60 66 kHz, Frequency —5.5V 65kHz crystal, Fig.2| Operating fopg3 Vss2=—3.5to OSCIN, external 32 220 kHz Frequency —§.5V Input, Fig. Operating fops4 Vss@=—-4.0to OSCIN/OSCOUT 180 200 220 | kHz Frequency —§.5V CF 200kHz, Fig.1 | Operating fopg5 Vss2=—4.0to | OSCIN/OSCOUT 360 400 ago | kHz Frequency —5.5V CF 400kHz, Fig.1 Operating fops6 Vss2=—4.0to OSCIN/OSCOUT 720 800 B10 | kHz Frequency —§.5V CF800KHz = Fig.1 No. 3341-16/31

Electrical Characteristics at Ta=-20 to +70C, VpD=0V Input Resistance | Rin1A Vss2@=—2.9V "L" level hold Tr 10 200 | ka Vin=0.8:Vss2 *1, Fig.3 Rin1B Vss2=—2.8V."L" level pull-in 200 700 2000 | ka Vin=Voo Tr #1, Fig.d Rin2A Vss2@=—2.9V Resistance for INT 200 700 2000 kQ Vin=Vss2 pull-up Input Resistance | Rin2B Vss2=—2.9V Resistance for INT 200 700 2000 kQ Vin=Vob pull-down Rin3 Vss2=—2.9V RES. 6 50 kQ Vin=Vopd or Vss2 Output "H"-Level | VoH(1) Vss2=—2.4V ALM -1 —0.3 Vv Voltage lon=— 1 mA Output "L"-Level | Vou(1) Vss2=—2.4V ALM (yss2 (vssé v Voltage lor= 1mA +0.3 +1 Output "H"-Level | VoH(2) | Vss2=—2.4V LIGHT, port P -1 —0.3 Vv Voltage | lox=—-0.3mA Output "L"-Level | Vo.(2) Vss2=—2.4V LIGHT, port P (vss? (vss? Vv Voltage loc =0.5mA +0.3 +1 Output "H"-Level | VoH(3) Vss2=—2.4V VO port -1 —0.3 Vv Voltage loH=—0.1mA Output "H"-Level | Vor(4) Vss2=—2.4V VO port —0.6 —0.2 Vv Voltage | lon=—50uA Output "L"-Level | Voi(4) Vss2=—2.4V VO port (Yssé (vsse Vv Voltage | loL=0.1mA +0.3 +1 Segment Driver Output Impedance CMOS Output Port Mode Output "H"-Level | Von(5) |Vss2=—2.4v Segment —1 | 70.3 v Voltage lon=— 100A PAD No62to64 Output "L"-Level | Vou(5) Vss2=—2.4V [ avrse pin no. | (vss? Vss2 Vv Voltage | lor= 10044 34t036 +0.3 ¢ +1 Output "H"-Level | VoH(6) | Vss2=—2.4V Segment -1 0.3 Vv Voltage loH=— 6 vA PAD No Output "L"-Level | voL(6) Vss2=—2.4V 38to41, 44to61 (ss? Vss2 Vv Voltage lov=20uA, QIP64 pin No. +0.3 ( +1 11to23, 25to33 PCH Open Drain Output Port Mode Output "H"-Level | VoH(5) Vss2=—2.4V Segment -1 —0.3 Vv Voltage loH=—10HA PAD No62to64 Output OFF-State | lore Vss2=—-2.9V [ arse pin wo 1 | wa Leakage Current Vor=Vss2 34to36 Static Display Output "H"-Level | VoH(5) | Vss2=—2.4V. 0.2 Vv Voltage loH=—0.4uA All segments Output "L"-Level | VoL(5) ea (res Vv Voltage loL=0.4uA +02 Output "H"-Level | VoH(7) Vss2=—2.4V —0.2 Vv Voltage loH=— 4 nA coM1 Output "L"-Level | Vou(7) Vss2=—2 | (vss? Vv Voltage lov= 4 uA +0.2 Continued on next page. No. 3341-17/31

Continued from preceding page. Electrical Characteristics at Ta=-20 to +70C, VDD=0V © Duplex Disptay (1/2Bias, 1/2Duty) Output "H"-Level | VoH(5) | vose=—2.4v 0.2 v Voltage loH=—0.4uA All segments Output "L"-Level | Vo.i5) Vss2=—-2.4V se Vv Voltage lovr=0.4nA +0.2 Output "H"-Level | VoH'7) | Vss2=—2.4V —0.2 Vv Voltage lon=— 4 vA Output "M"-Level | Vom Vss2=—2.4V (vsse/2 (vsse/2 Vv Voltage lon=— 4 uA COM1-2 —0.2 40.2 lor= 4 nA Output "L"-Level | Voui7) Vss2=—2.4V (vss? Vv Voltage lor= 4 uA +02 @1/2Bias, 1/3Duty Display Output "H"-Level | Vor‘5) Vss0=~2.4V 0.2 v Voltage loH= 0.428 All segments Output "L"-Level | Vou‘5) Vss2=—2.4V (Yss2 Vv Voltage for=0.4nA +0.2 Output "H"-Level | Vou(?) Vss2=—2.4V —0.2 Vv Voltage lon=— 4 uA Output "M"-Level | Vom Vss2=—2.4V (vsse/2 (“sse/? Vv Voltage loH=— 4 uA COM1-3 —0.2 +0.2 lor= 4 uA Output "L"-Level | Vo.i?) | Vss2=—2.4V (vss2 v Voltage lov= 4A +0.2 © 1/3Bias, 1/3Duty Display Output "H'"-Level | Vou‘5) Vss2=—2.4V —0.2 Vv Voltage lou=—0.40A Output "M"-Level | Vom1-1 Vss2=~2.4V (vsse? (vsse72 Vv Voltage lon=—0.4uA All segments —0.2 +0.2 Vomt-2 | !or=0.4uA ( Vss2 (Ys? Vv 0.2 +0.2 Output "L"-Level | Voi(5) vss2=—2.4V (ys) Vv Voltage jo =0.4uA +02 Output "H"-Level | VoOH{7) Vss2=—2.4V —0.2 Vv Voltage loH=— 4 uA Output "M"-Level | Vom2-1 | Vss2=—2.4V (vsser2 (vsse/e Vv Voltage lon=— 4 uA COM1-3 0.2 +0.2 Vome-2 | loL= 4 4A (vss ee Vv —0.2 +0.2 Output "L"-Level | VoL(7) Vss2=—2.4V | Css Vv Voltage lov= 4 uA | +0.2 Continued on next page. No. 3341-18/31

Continued from preceding page. Electrical Characteristics at Ta=-20 to +700, Vpp=0V Item Input Resistance | Rin1A Vss2=—5.0V "L" level hold 10 45 150 | ka Vin=0.8-Vss2 Thy *4, Fig.3 RnB Vss2=—5.0V Pull-in "L" level 100 350 1000 j k2 Vin=Voo Tr, *1, Fig.3 RinzgA Vss2=—5.0V Resistance for 100 350 1000 | k2 Vin=Vss2 INT pull-up | Riw2B Vss2=—5.0V Resistance for 100 350 yo00 | ke Vin=Vop INT pull-down Rin3 Vss2=—5.0V RES 10 20 50 | ka Vin=Vood or Vss2 Output "H"-Level | VoH(1) | Vss2=—3.5Vto ALM -1 0.3 v Voltage ~5.5V loH=—1.5mA Output "L"-Level | Voit) | Vss@=—-3.5Vto ALM (Yss2 (vss? v Voltage —8.5V +0.3 +1 loL=1.5mA Output "H"-Level | VoH(2) | Vss2=—3.5Vto LIGHT, port P -1 —0.3 Vv Voltage —5.5V lon=0.5mA Output "L'-Level | VoL(2) Vss2=—3.5Vto LIGHT, port P (Yssé (vss? Vv Voltage —5.5V +0.3 +1 loL=0.7mA, Output "H"-Level | VoH(3) Vss2=—3.5Vto 1/0 port -1 —0.3 Vv Voltage —5.5V lox#=—0.13MA Output "H"-Level | VoH(4) | Vss2=—3.5Vto 1/0 port -0.6 0.2 v Voltage —5.5V loH=—50KA | Output "L"-Level | VoL(4) | Vss2=—3.5Vto 1/0 port { (¥ss2 Vss2 | V Voltage —5.5V j\\+0.3 ( +1 1oL=0.13MA Segment Driver Output Impedance CMOS Output Port Mode Output "H"-Level | VoH(5) | Vss2=—3.5Vto Segment -41 —0.3 Vv Voltage —§.5V PAD No62to64 foH=— 154A [ airse pin no | Output "L"-Level | VoL(5) Vss2@=—3.5V to 34to036 Vss2 Vss2 Vv Voltage —5.5V (st 3 ( +t 1oL=1504A, Output "H"-Level | VoH(6) | Vss2=—3.5Vto Segment -41 0.3 v Voltage —§.5V PAD No loH=— 102A, 38to41, 44to67 Output "L"-Level | VoL(6) | Vss2=—3.5Vto QIP64 pin No. Vss2 vss2 | V Voltage —§.5V 11to23, 25to33 ( 3 ( +1 foL=60KA Continued on next page. . No. 3341-19/31

Continued from preceding page. Electrical Characteristics at Ta=-20 to +70C, Vpp=0V PCH Open Drain Output Port Mode Output "H"-Level | VoH(5) Vss2=—3.5Vto Segment -1 —0.3 v Voltage —5.25V PAD No62to64 loH=— 1544 [ ase pin ne, | Output OFF-State| lore Vss2=—3.5Vto 34to36 1 | #A Leakage Current —5.25V Vot=Vss2 Static Display | Output "H"-Level | VoH(5) Vss2=—3.5V to ; 0.2 Vv Voltage —5§.25V loH=—0.4uA All segments | Output "L"-Level | VoL(5) Vss2=~—3.5Vto {| (vss? Vv Voltage —5.25V +02 lov=0.4uA Output "H"-Level | VoH(7) | Vss?=—3.5V to —0.2 Vv Voltage —5.25V loH=— 4 uA COM1 Output "L"-Level | VoL(7) Vss2=—3.6Vto ( Vss2 Vv Voltage —$.26V +0.2 Jor= 4 uA Duplex Display (1/2Bias, 1/2Duty) Output "H"-Level | VoH(5) | Vss2=—3.5V to 0.2 Vv Voltage —5.25V loH=—0.4uA All segments Output "L"-Level | Vo.(S) | Vss2=—3.5V to (vse v Voltage 5. 25V +0.2 lou=0.4uA Output "H"-Level | VoH(?) | Vss2=—3.5V to —0.2 Vv Voltage —5.25V loH=— 4 uA Output "M"-Level | Vom2-1 | Vss2=—3.5Vto Vss2/2 (vsse72 Vv Voltage —5.25V —0.2 +0.2 loH=— 4 nA COMi-2 Jor= 4 uA Output "L"-Level | VoL(7) Vss2=—3.5V to (vss? Vv Voltage —5.25V +0.2 loL= 4 nA @1/2Bias, 1/3Duty Display Output “H"-Level | VoH(5) Vss@=—3.5V to —0.2 Vv Voltage —5.25V loH=—0.42A All segments Output "L"-Level | vou(5) Vss2=—3.5V to (Yss2 v Voltage —5.25V +0.2 loL=0.4uA Output "H"-Level | VoH(7) Vss2=—3.5V to —0.2 Vv Voltage —5.25V lon=— 4 nA Output "M"-Level | Vom2 -1 | Vss2=—3.5V to ( Yss2/2 (Ysse72 Vv Voltage —5.25V —0.2 +0.2 loH=— 4 pA COM1-3 for= 4 nA Output "L"-Level | Vou(7) | Vss2=—3.5V to (Ysse Vv Voltage —5.25V +0.2 lov= 4 zA Continued on next page. No, 3341-20/31

Continued from preceding page. Electrical Characteristics at Ta=-20 to +70C, VDD=0V © 1/3Bias, 1/3Duty Display Output "H"-Level | VoH(5) Vss2=—3.5Vto —0.2 v Voltage —5.26V loH=—0.4nA | Output "M'-Level | Vom1-1 Vss2=—3.5Vto Vss2/2 | ( vsse/ Vv Voltage ~5.25V —0.2 | +0.2 loH=—0.4 2A All segments Vom1-2 lor=0.4uA (vss? ( vss2 | V —0.2} +0.2 Output "L"-Level | VoL(5) | Vss@=—3.5Vto | Vss3 } V Voltage —5.25V | +0.2 lor=0.4uA | Output "H"-Level | VoH(7) Vss2=—3.5Vto —0.2) Vv Voltage —5.25V loH=— 4 uA Output "M'"-Level | Vom2-1 Vss2=—3.5V to (vsse? (vsse2 Vv Voltage —5.25V 0.2 +0.2 loH=— 4 uA COM1-3 Vom2-2 |b lou=4 4A (vss? (Ys? Vv | —0.2 +0.2 Output "L"-Level | Vou(7) Vss2=—3.5V to Vss3 Vv Voltage —$.25V (te 2 Power Supply for= 4 uA Leakage Current | ILeK Vss2@=Vss3=—4.5V Ta=25T 10 | A Input Leakage hin, Vss2=—2.0to Vin=Vss2toVoD -1 1] uA Current —4.5V Output Voltage Vss1 Vss2=—2.9V C1=C2=C3= 1.45 1.35 Vv | vss3 Vss?=—2.9V 0.1 uF —4.35 | -41 | v | fopg=32.768kHz i Ta=25C — Fig.7 Output Voltage | Vss1 Vss@=—4.5V C1=C2=C3= —2.25 —2.2 Vv | fopg=32.768kHz Ta=25C — Fig.7 Supply Current llop 11 Vss2=—2.9V C1=C2=0.1uF 3.0 5 | wA Ta=25T, HALT mode] Ci=25k2 lipo 21 Vss2=—4.5V fopg=32.768kHz 10 20 uA | Ta=25C, HALT model Cg=20pF Static:Fig.9, 1/3B. 1/3D:Fig.7, others:Fig.4 Supply Current IIo 31 Vss2=—4.5V C1=C2=0.1uF 20 50 | #A Ta=25T Cl=25kQ HALT mode fopg=65.538kHz Cg=10pF Static:Fig.9, 1/38. 1/3D:Fig.7, others:Fig.4 Supply Current Hoo 41 Vss2=—4.5V C1=C2=0.1uF 100 300 | uA Ta=26T fopg=200kHz HALT mode Cg=Cd=330pF or 180pF Rf=1MQ Fig.6 Supply Current Itpo5 | Vss2=—4.5V C1=C2=0.1uF 160 400 | uA Ta=25T fopg=400kHz HALT mode Cg=Cd=100pF or 330pF Rf=1MQ Fig.6 Continued on next page. No. 3341-21/31

Continued from preceding page. Electrical Characteristics at Ta=-20 to +70C, Vpp=0V [tem __[ Simbot | ___Gonaition/Terminal [min [ op | mex [unt] Supply Current ltop Bi Vss2=—4.5V C1=C2=0.tuF 200 500 uh Ta=25T. fopg=800kHz HALT mode Cg=Co=100pF Rf=1Ma Fig.6 Oscillation Hold | IVHoLoI! | Ta=25°C rC1=C2=0.1uF 2.0 5.5 Vv Voltage Cl=25k2 fopg=32.768kHz Cg=200F Static:Fig.9, 1/3B. 1/3D:Fig.7, others:Fig.4 Oscillation Hold | |VHoLo2! | Ta=25°C. pCi=C2=0.1uF 2.3 5.5 Vv Voltage | Cl=25kQ : fopg=65.536kHz {Cg=10eF Static:Fig.10, 1/38, 1/3D:Fig.7, others:Fig.4 Oscillation Start |!vstt1l | Ta=25°C C1=C2=0.1nF 22) Vv Voltage Cl=25kQ = Fig.5 fopg=32.768kHz Ce=20pF Oscillation Start |lvstt2l. | Ta=25C C1=C2=0.1nF 2.6 | Vv Voltage Cl=25kQ — Fig.5 fopg=65.536kHz Cg=10pF Oscillation Start | Tsttl Vss2=—2.9V Ct=C2=0.1uF 10 s Time Ta=25T Ci=25kQ Fig.5 Vss2= —4.5V fopg=32.768kHz 10 s Ta=250 Cg=20pF Oscillation Start | Tstt2 Vss2=—2.9V C1=C2=0.1uF 10 s Time Ta=26C Cl=25kQ = Fig.5 Vss2=—4.5V fopg=65 .536kHz 10 s Ta=25T Cg=10pF Oscillation Start |{Vvstt4l | Ta=25°C fopg=200kHz Fig.6 4.0 | Vv Voltage Cg=Cd=330pF or 1809F RF=1MQ Oscillation Hold |IVHoLod| | Tas+25%C fops=200kHe Fig6 | 3.8 5% | v Voltage [ones or 180pF RF=1Ma Oscillation Start | Tsttd Vss?=—4.5V fopg=200kHz Fig.6 50 500 | ms Time Ta=25T Cg=Cd=330pF or 180pF RF=1MQ Oscillation Start | lVstt5l Ta=25T fopg=400kHz Fig.6 40] ov Voltage Cg=Cd=100pF or 330pF Rf=1MQ Oscillation Hold | VHoLoS! | Ta=25'°C fopg=400kHz Fig.6 3.5 5.6 Vv Voltage Cg=Cd=100pF or 330pF

5 Rf=1MQ

Oscillation Start | TsttS Vss2=—4.5V - fopg=400kHz Fig.6 30 | ms Time Ta=25T. Cg=Cd=100pF or 330pF Rf= 1 MQ No, 3341.22/31

LC5851N . Continued from preceding page. Electrical Characteristics at Ta=-20 to +70©, Vpp=0V Oscillation Start | IVstt6l | Ta=25°C fopg=800kHz Fig.6 4.0 Vv Voltage [ Cg=Cd=100pF Rf=1MQ Oscillation Hold IVHoLo 6] Ta=25°C fopg=800kHz Fig.6 5.5 Vv Voltage [ csecd= tor Rf= 1MQ Oscillation Start | Tstt6 Vss2=—4.5V fopg=800kHz Fig.6 30 ms Time Ta=25T. [ ceco=totoF Rf= 1MQ Oscillation 10P. Vss2=—2.9V 10p terminal 10 pF Compensation (for chip only) Capacitance 10P Vss2=—4.5V 10p terminal 10 pF (for chip only) 20P Vss2=—2.9V OSCOUT terminal 20 pF 20P Vss2=—4.5V OSCOUT terminal 20 pF MLNo products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and . the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: © Accept full responsibility and indemnify and defend SANYO ELECTRIC CO,, LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD,, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. W Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. No. 3341-23/31

. LC5851N son _oscour i DK o a aT =e Vio Yop Fig. 1 Ceramic Resonator Oscitlation Recommended Ceramic Resonator [zoe | CSB2000 | 330eF | 330pF KBR-2008 | 180pF | 180pF 400kHz csB4c0P_| 100pF | 100pF KBR-4008 | 330pF | 330pF 800kHz csesoo) | 100pF | t00pF | 1Mma | KBR-800H | 100pF | 100pF osc oscour o ce T Ceytal (32K, 654) aa = POFLAG Fig. 2. Crystal Oscillation (32kHz, 65kHz) Fig. 3. Input Configuration of S1 to S4, M1 to M4 ec Ce ce @ cup2 Veo ‘OsciIN 4 Vo oscw curl oUT —osoour Ofcom OUT gccoyr|_ crmczna.ue L Vss2 Vss2 vet J Fig. 4 Supply Current, Oscillation Hold Fig. 5 Oscillation Start Voltage, Voltage Test Circuit Oscillation Start Time, Frequency Stability Test Circuit m c2 Ce Ca] 3 2 . en| four veo osom by Jor cuPY Wo osom CUP? yy E f=] oup2 i=] oscouT C3 Vest Dur oscouT; crec2=ca=0.10 c1mc2=c320.10F Note: Connact 9 at U9di08 mode, Fig, 6 Oscillation Start Voltage, Fig. 7 Supply Current, Oscillation Hold Oscillation Start Time, Supply Current, Voltage, Test Circuit Oscillation Hold Voltage Test Circuit Yoo ‘OScIN mM a 0.2% Vs52 cuP2 Yoo OSCIN 2 | | esomany a ES Oven no Wi, re ue tnput waveform (OSCIN) : Fig. 9 Supply Current, Oscillation Hold Fig. 8 External Input Mode Voltage Test Circuit No. 3341.24/31

Absolute Maximum Ratings at Ta=25C, Vpp=0V Condition/ Terminal Rating Maximum Supply | Vss1 —4.0 to +0.3 Vv Voltage Vss2 —4.0 to +0.3 Vv Vss3 ALCO lighting:1/3bias display) —§.5 to +0.3 Vv Vss3 {LCD fighting:Other than 1/3bias display) —4.0 to +0.3 v Maximum Input Vint $1-4, M1-4, /OA1-4, 1/0B1-4, (“Ss to +0.3 Vv Voltage INT, TESTACI/OA1-4, 1/0B 1-4 are in 0.3 . the input moce.)] OP, OSCIN, RES, BAK Maximum Output | Vout! ALM, LIGHT, P1-4, I/OA1-4, (YS to +0.3 Vv Voltage V/OB1-4, CUP2(I/OA1-4, /OB1-4 —0.3 . are in the output mode.) TEST, OSCOUT Vout3 SEGOUT, COM1toCOM3, cup1 (vss to +0.3 Vv Operating 0.3 . gomperature Topr —20 to +65 c orage = Temperature Tstg 30 to +125 c Allowable Operating Conditions at Ta=25s2C,Vpp=0V item Supply Voltage Vss1 VBAK=Vsst —1.65 1.3 Vv Vss2 3.3 2.4) Vv Vss3 (LED tighting:1/3bias display) 4.95 -3.7 Vv Vss3 (LCD lighting:Other than 1/3bias display) Vss3=Vss2 Input "H'"-Level Viq S1-4, M1-4, I/OA1-4, /0B1-4, —0.2 | 0 Vv Voltage INT, (1/OA1-4, 1/0B 1-4 are in the input mode.) Input "L"-Level Vit S1-4, M1-4, /OA1-4, VOB1-4, Vssi Vsst Vv Voltage INT, (I/OA1~-4, 1/0B1-4 are in the (M02 Operating input mode.) Frequency fopg Ta=—20to+ 65°C 32 33 | kHz Electrical Characteristics at Ta=2542, Vpp=0V Input Resistance | RintA | Vsst=—1.55V, "L" level hold Tr 10 200 | ka Vi=Vsst+0.2V #1, Fig. RiwiB Vss1==—1.55V, pull-down resistor 200 2000 | ka *1, Fig. Rin2A Vss1=—1.55V, pull-up resistor for 200 2000 | ka Vit=Vsst INT Rw2B Vss1=—1.55V, pull-up resistor for 5 50 | ka Vin=Voo INT Rin3 Vss=—1.55V, pull-down resistor 5 50 | kQ Vin= VoD for RES Output "H"-Level |vou(t) | Vsst=—1.35V, ALM, LIGHT —0.65 Vv Voltage lon=— 2504 Output "L"-Level | VoL(1) Vssl=—1.36V, ALM, LIGHT ( Vss1 Vv Voltage foL=250 nA +0.65 Output "H"-Level | VoH(2) Vss1=—1.56V, VOA1-4, 1/0B1-4, —0.2 Vv Voitage lox=—20uA, P1-4 (I/OA1-4, OB 1-4 ore in the output mode.) Output "L"-Level | Vou(2) Vssl=—1.55V, /OA1-4, 1/OB1-4, (ssi v Voltage loH=20nA, P1-4, +0.2 (I/OA1~4, OB 1-4 are in the outout mode.) Continued on next page. No, 3341-25/31

Continued from preceding page. Electrical Characteristics at Ta=25+2C, Vpp=0V Segment Driver Output Impedance Static Display Output "H"-Level | VoH(3) Vssi=—1.55V, SEGOUT 0.2 Vv Voltage lox=—0.4nA Output "L"-Level | VoL(3) Vss1=—1.55V, SEGOUT (vse Vv Voltage loL=0.4uA +0.2 Output "H"-Level | VoH(4) Vss1=—1.55V, COMI —0.2 Vv Voltage lon=— 4 nA Output "L"-Level | Vo.(4) Vss1=—1.55V, COMI (ss Vv Voltage lor= 4 A +0.2 Duplex Display (1/2Bias, 1/2Duty) Output "H"-Level | VoH(3) | Vss1=—1.55V, al! SEGOUTs —0.2 v Voltage lon —0.4uA Output "L"-Level | VoL(3) | Vss1=—1.55V, all SEGOUTs (vss? v Voltage loL=0.4nA +0.2 Output "H"-level | VoH(4) Vssi=—1.56V, COM1 - COM2 —0.2 Vv Voltage lon=— 4 pA Output "M"-Level | Vom Vss1=—1.55V, COM1 - COM2 (vss) (Ys) Vv Voltage IOH=— 4 uA, lol 4 nA —0.2 +0.2 Output "L"-Level | Vou(4) Vss1=—1.55V, COM1 - COM2 (Ys Vv Voltage lor= 4 nA +0.2 ©1/2Bias, 1/3Duty Display Output "H"-Level | VoH(3) | Vssi =—1.55V, all SEGOUTs -0.2 Vv Voltage loH=—0.4uA Output "L"-Level | voL(3) | Vss1=—1.95V, all SEGOUTs (vss? v Voltage lor=0.4uA +0.2 Output "H"-Level | Vou(d) | vssi=—1.55V, COMI - COM2 - —0.2 v Voltage loH=— 4 uA COM3 Output "M"-Level | Vom Vss1=—1.55V, COM1 - COM? - (vss) (Ys) v Voltage JOH=— 4 uA, lov= 4 uA, COM3 —0.2 +0.2 Output "L"-Level | Void) | Vss1=—1.85V, COMI - COM2 - (vss? v Voltage for= 4 uA COM3 +0.2 ©1/3Bias, 1/3Duty Display Output "H"-Level | You(3) | Vsst=—1.56V, all SEGOUTs —0.2 v Voltage foH=—0.4uA Output "M1"-Level| VomI-3 | Vss1=—1.56V, all SEGOUTs ws} (Ms) Vv Voltage loH=—0.42A, lOL=0.4uA —0.2 +0.2 Output "M2"-Level| Vom2 - 3) Vss1=—1.55V, all SEGOUTs (se (vss Vv Voltage loH=—0.4uA, lor=0.4uA —0.2 +0.2 Output "L"-Level | Vo.(3) Vss1=—1.55V, all SEGOUTs (vee Vv Voltage loL=0.44A | \\+0.2 Output "H"-Level | VoH(4) Vss1=—1.55V, COM1- COM2 + 0.2 Vv Voltage loH=— 4 uA COMB Output "M1"-Level] Vom1-4 | Vssi1=—1.55V, COM1-COM2- (vss! | (vss Vv Voltage loH=— 4 HA, loL= 4 uA COM3 —0.2 +0.2 Output "M2"-Level] Vom2-4 | Vss1=—1.58V, COM1-COM2- (vss? (Yss? Vv Voltage lon=— 4 vA, loL=4 uA COM3 —0.2 +0.2 Output "L"-Level | VoL(4) | Vss1=—1.55V, COM1 + COM2- (sss Vv Voltage lou= 4 uA com3 +0.2 CMOS Output Port Mode Output "H"-Level | VoH(3) Vssl=—-1.55V Segment —0.3 Vv Voltage loH=— 3 uA PAD Na Output "L"-Level | Vov(3) Vss1=—1.55V 38to41, 44to61 (yssz Vv Voltage loL= 3 uA les pin “| +0.3 11to23, 25to33 Continued on next page. No. 3341-26/31

Continued from preceding page. Electrical Characteristics at Ta=2542C, VDD=0V © Output Voltage LCD Lighting: 1/38ias Method (doubler) Vss2 Vss1=—1.35V, fopg=32.768kHz —25]; Vv CltoC4=0.1ue Fig.7 (tripler) Vss3 Vss1=—1.35V. fopg=32.768kHz —3.75 | V CitoC4=0.1uF Fig.7 LCD Lighting: 1/2Bias Method (doubler) Vss2 Vss1=—1.36V, fopg=32.768ktHz 2.5 Vv C1=C2=0.1uF Fig.2 © Supply Current (Backup flag is reset.) LCO Lighting: I lool Vss1=--1.55V, HALT mode 3.5 HA 1/38ias Olsplay CltoC4=0.1uF, Cl=25k2 Fig.7 Cd=Cg=20pF, 32.768kHz X'tal LCD Lighting: | lool Vss1=—1.55V, HALT mode 2.0 uA Other than C1=C2=0.1uF, Cl=25k2 Fig.2 1/3Bias Display Cd=Cg=20pF, 32.768kHz X'tai Oscillation Start || Vstt | Cd=Cg=20pF, Cl=25k2 Fig.3 1.35 Vv Voltage Vss1 32. 768kHz X'tal Oscillation Hold ||VHotol Cd=Cg=20pF, Cl=25k2 Fig.2 1.6 Vv Voltage Vsst 32. 768kH2 X'tal Oscillation Start | Tstt Vss1=—1.35V. Cl=25k2 Fig.3 10 | sec Time Co=Cg=20pF, 32.768kH2 X'tal Gsciation 10P External terminal 10 12 | pF /ompensation Capacitance 20P OSCOUT 20 24 | pF 3*1 St, S2, $3, S4, Mi, M2, M3, M4 No, 3341-27/31

Absolute Maximum Ratings at Ta=2542C, VoD=0V Gondition/ Terminal Maximum Supply | Vss1 Veak=Vsst or Vss2 —4.0 to +0.3 Vv Voltage vss2 —4.0 to +0.3 v Vss3 (LCD lighting:1/3bias display) —6.5 to +0.3 Vv Vss3 {LCD lighting:Other than 1/3bias display) —4.0 to +0.3 Vv Maximum Input. Vint 10p, OSCIN Veak Vv Voltage eae to +0.3 Vin2 S1-4, M1-4, I/OA1-4, /OB1-4, ( vss? to +0.3 Vv INT, TESTACI/OA1-4, 1/0B1-4 —0.3 are in the input mode.) Maximum Output | Vout1 TEST, OSCOUT VBaK Vv Voltage we to +0.3 Vout2 ALM, LIGHT, P1-4, I/OA1-4, Vss2 to +0.3 Vv VOB1-4, CUP2 oe in the output Co's : (/OA1~4, 081-4 mae’) MP OUPe ; Vout3 SEGOUT, COM1toCOM3, CUP1 (Yss2 to +0.3 Vv Operating 0.3 Broeeee Topr 20 to +65 c 0! —! Temperature Tsts 30 to +125 c Allowable Operating Conditions at Ta=2522C, Vpp=0V [em | Synbor [____Gonaltion/ Terminal Supply Voltage Veak 3.6 1.3 Vv Vss2 Veak=Vss2/2 —3.6 —2.6 Vv (Backup flag is reset.) Vss2 VBaAK=Vss2 ~3.6 1.3 Vv (Backup flag is set.) Vss3 {LCD lighting:1/3bias display) 4.95 -3.7 | Vv Vss3 {LCD lighting:Other than 1/3bias display) Vss3=Vss2 Input "H'-Level | Vin S1-4, M1-4, V/OA1-4, 1/0B1-4, 0.4 oj) Vv Voltage INT, (1/OA1-4, 1/0B1-4 are in the input mode.) Input "L"-Level Vit S1-4, M1-4, VOA1-4, 1/08 1-4, Vss2 (yes Vv Voltage INT, (1/0A1-4, I/OB1-4 +0.4 Operatin are in the input mode.) Frequency fopg Ta=—20to+65C 32 33 | kHz Electrical Characteristics at Ta=2522b, Vpp=0V Conaiton/ Terminal Input Resistance | RintA Vss2=—2.9V, "L" level hold Tr 10 200 | ka Vi=Vss2+0.4y “ls Fig RintB Vss2=—2.9V, pull-down resistor 200 2000 | ka #1, Fig.d Rin2A Vss2=—2.9V, pull-up resistor for 200 2000 | ka Vi=Vss2 INT RineB Vss@=—2.9V, pull-down resistor 200 2000 | k2 Vin=Voo for INT Rin3 Vss2=—2.9V, pull-down resistor 5 50 | ka Vid=Vod for RES Continued on next page. No. 3341-28/31

Continued from preceding page. Electrical Characteristics at Ta=25420, Vpp=0V Output "H"-Level | VoH(1) | Vss@=—2.4v, ALM 0.65 v Voltage lon#=— 25044 Output "L"-Level | Vo.(1) | Vss2=—2.4V, ALM ( vss2 | v Voltage lov=250 uA +0.65 Output "H"-Level | VoH(2) | Vss2=—2.9V, /OA1-4, /OB1-4, 0.4 i Vv Voltage loH=—40uA, P1-4 (IOA1-4, (0B 1-4 are in tne output mode.) Output "L"-Level | Vou(2) | Vss2=—2.9V, VOA1-4, /0B1-4, ( vss? v Voltage lor=40uA, P1-4 +0.4 (VOA1~4, 1/0B 1-4 ore in the ovtovt mode) Output "H"-Level | VoH(3) | Vss2=—-2.9V, LIGHT -1.5 Vv Voltage foH= ~ 150A Output "L"-Level | Voi(3) Vss2=—2.9V, LIGHT Cs Vv Voltage lor =150uA +15 Segment Driver Output Impedance @ Static Display Output “H"-Level | VoH(4) | Vss2=—2.9V, all SEGOUTs 0.2 v Voltage loH=—0.4n4 Output "L"-Level | VoL(4) | Vss2=—2.9V, all SEGOUTS (yss2 Vv Voltage loc=0.4nA +0.2 Output “H"-Level | Von(5) | Vss@=—2.9V, COM1 ~0.2 v Voltage loH=— 4 uA Output "L"-Level | Vou(5) | Vss2=—2.9V, COM1 (vss2 v Voltage loL= 4 uA +0.2 Duplex Display (1/2Bias, 1/2Duty) Output "H"-Level | VoH(4) | Vss2=—2.9V, all SEGOUTSs 0.2 v Voltage tox=—0.4n4 Output "L"-Level | Voi(4) Vss2=~—2.9V, all SEGOUTS (see v Voltage Jo.=0.4uA +0.2 Output "H"-Level | VoH(5) | Vss@=—2.9V, COM1 » COM2 ~0.2 v Voltage | !oH=— 4 nA Output "M"-Level | Vom | Vss2=—2.9V, COM1 - COM2 (vsse/2 (vssere Vv Voltage Hlon=— 4A, lov= 4 uA 0.2 +0.2 Output "L"-Level | Vou(5) | Vss2=—2.9V, COM1 - COM2 (vsse v Voltage lor= 4 uA +0.2 ©1/2Bias, 1/3Duty Display Output "H"-Level | VoH(4) | Vss2=—2.9V, all SEGOUTs 0.2 v Voltage | lonH=—0.4 uA. Output "L"-Level | Vou(4) Vss2=—2.9V, all SEGOUTs Vss2 Vv Voltage foL=0.4uA (oz Output "H"-Level | VoH(5) | Vss2=—2.9V, COMI - COM? - —0.2 v Voltage lon=— 4 uA COM3 Output "M"-Level | Vom Vss2=~2.9V, COM1 - COM? - (vsse/2 (vse v Voltage loH=— 4 uA, loL=4 nA COM3 0.2 +0.2 Output "L"-Level | Voi(5) | Vss2=—2.9V, COM1 - COM2 - ry Vv Voltage fo=4uA — COM3 +0.2 © CMOS Output Port Mode Output "H"-Level | VoH(4) Vss2=—2.9V Segment —0.3 Vv Voltage loH=— 5 nA PAD No Output "L"-Level | Vo.(4) | Vss2=—2.9V 38to041, 44to61 (vss? v Voltage lov=5 uA FLP64 pin No. +0.3 11to23, 25to33 Continued on next page. No. 3341-29/31

Continued from preceding page. Electrical Characteristics at Ta=2522C, Vpp=-0V @1/3Bias, 1/3Duty Display Output "H"-Level | Vox(4) | Vss2=—2.9V, all SEGOUTs —0.2 Vv Voltage loH=—0.4 4A Output "M1"-Level] Vom1-4 | Vss2=—2.9V, all SEGOUTs (vsse72 Vss2/2 Vv Voltage loH=—0.4uA, lor=0.4uA —0.2 +0.2 Output "M2"-Level] Vom2-4 | Vss2=—2.9V, all SEGOUTs (vss? (vss? Vv Voltage foH=—0.4uA, loc=0.4uA —0.2 +0.2 Output "L"-Level | VoL(4) Vss2=—2.9V, all SEGOUTs (Yss8 Vv Voltage foL=0.4uA +0.2 Output "H"-Level | VoH(S) | Vss2=—2.9V, COMI - COM? - —0.2 Vv Voltage lox=— 4uA COM3 Output "M1"-Level] Vom1-5 | Vss2=—2.9V, COM1 - COM2 - (vss2/2 Vss2/2 v Voltage lon=— 4 uA, lov=4uA COM3 —0.2 +0.2 Output "M2"-Level| Vom2-§ | Vss2=—2.9V, COMI - COM2 - (vss? (vss Vv Voltage lon=— 4 uA, loL=4 eA COM3 —0.2 +0.2 Output "L"-Level | VoL(5) Vss@=—2.9V, COM] - COM2 + (Yss8 Vv Voltage loc= 4 «A COM3 +0.2 Output Voltage LCD Lighting: 1/3Bias Display (nalver) Vss1 Vss2=—2.9V, fopg=32. 768kHz | 1.36 | Vv CitoC4=0.14F Fig.8 | Ctripler) Vss3 Vss2=—2.9V, fopg=32.768kHz —41] Vv CitoC4=0.14F Fig.8 LCD Lighting: Other than 1/3Bias Display (halver) Vss1 Vss2=~2.9V, fopg=32. 768kHz —1.35 | Vv C1=C2=0.1uF Fig.5 Supply Current (Backup flag is reset.) LOD Lighting: Hoo! Vss2=—2.9V, HALT mode 5.0 uA 1/3Bias Display CitoC4=0.1uF, Cl=2kQ —Fig.8 Cd=Cg=20pF, 32.768kHz X'tal LCD Lighting: {Ioo] Vss2™=—2.9V, HALT mode 1.0 uh Other than C1=C2=0.1uF, Cl=25k2 ——Fig.5 1/3Bias Display Cd=Cg=20pF, 32. 768kHz X’tal Oscillation Start jivstt! Veak=Vss2, Cl=25k2 Fig.6 1.35] V Voltage Vss2 Cd=Cg=20pF, 32.768kH2 X'tal Oscillation Hold teltage Vss2 IVHoLo(1)I| Vaak=Vss2/2, Cl=25k2 Fig. 2.6 3.6| V is reset.) 9 Cd=Cg=20pF, 32.768KHz X'tal {Backup flag IVHOLO(2)!) Vaak=Vss2, Cl=25kQ Fig.6 1.3 3.6) V is set. Cd=Cg=209F, 32.768kHz X'tal Oscillation Start Tstt VBAK=VsS2=—2.9V, Cl=26k2 , Fig.6 10 | sec Time Cd=Cg=20pF, 32.768kHz X'tal Oscillation 10P External terminal 8 10 12 | pF Compensation 20P OSCOUT 16 20 24 | pF Capacitance

1 Si, S2, $3, S4, M1, M2, M3, M4

No. 3341-30/31

Fig, 1 S1-4, M1-4 Input Configuration Fig. 2 Supply Current, Oscillation Hold Voltage Test Circuit 2p. ctfo. Low CUPL veo OSC IN ‘i Gurr OUT scour] vssz SS! VSS! Fig. 3. Oscillation Start Voltage, Fig. 4 S1-4, M1-4 Input Configuration Oscillation Start Time, Frequency Stability Test Circuit veo OSC IN ao oe tier our oscouT ‘VSS! NS8S2 —— | YSS2 Fig. 5 Supply Current, Oscitlation Hold Fig. 6 Oscillation Start Voltage Voltage Test Circuit Oscillation Start Time, Frequency Stability Test circuit ‘Dp; cue feu YO ewe ww 70; spot but a i? © vt er cuPt vo se Ss ws! wes? o—Jorcur2 YT oscour vss2__ VSS! _] Fig. 7 Supply Current, Oscillation Hold Fig. 8 Supply Current, Oscillation Hold Voltage Test Circuit Voltage Test Circuit Dp, a p, ei do.te art voo osc “re ca {eur VO osc wl = Orwkcue2 OUT gc qut| og Gwcurz out oscou,_=F p vss VSS? vssa_ BAK NST vgsy YS54 4c3 Fig. 9 Supply Current, Oscillation Hold Voltage Test Circuit als (oP. oan fcurr Oo cs : OSCIN Ole cure - vssi OSC OUT vss3_ VSSQ No, 3341-31/31