LC5812

LC5812 SANYO | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 24

Technical content

Features

e Awide supply voltage range = Pacietine [supply vonagerane LC5812 122s Vss2 = -2.0 to - 3.6V 32k crystal 122ps Vss2 = - 2.0 to -5.0V 32k crystal Vss2= -2.3to -5.0V 65k crystal LC5812H ¥ a Vss2= -3.5to -5.0V_ | 400k ceramic resonator | 20ns_ | Vss2= -4.5to -5.0V | 800k ceramic resonator Package Dimensions 3044B (unit: mm) 26.0 : ae 2.18 ~ [ET fagagdennnnr tne ‘ Les IITA NETTIE a | == > =| oo = == 5 SS = = = . 80 TMT. tC | 0.15 SANYO : QIP80A. SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 3029TA/D196K1/9115Ki,TS No.2058-1/24"

O Micro-level operating current Only micro-level current is needed to operate the equipment if the HALT function is used efficiently. Although the exact current dissipation depends on the oscillation frequency {and the oscillator) and the program structure, a typical current requirement is about 5yA to run the clock program if the optimum technique is used to design the program. © Enhanced HALT/HOLD release and interrupt functions © Five types of HALT/HOLD release functions and five types of interrupt functions e External interrupt function (included in the above 5 interrupt functions) © Up to 8 levels of subroutine nesting (common with interrupts} © Enhanced hardware for greater processing capability © Built-in segment PLA circuit: Is able to join the LCD driver outputs to any patterns on the LCD panel without software. © Built-in decimal up/down counter © Built-in 8-bit programmable timer @ The entire RAM area can be used as a working area (bank switching). e Built-in data pointer © All instructions per step operation @ Built-in clock oscillator and frequency divider circuit © Various LCD output terminals for LCD pane! drive (42 terminals) LCD panel Number of LCD segments 1/3 bias 1/3 duty 126 segments (max.) 1/2 bias 1/3 duty 126 segments (max.) 1/2 bias 1/2 duty 84 segments (max.) 42 segments (max.] © The LCD panel drive output terminal can be switched to the general-purpose output terminal. ° © A number of input and output terminals are provided. Input dedicated port: 2 ports/8 pins Input/output port: 2 ports/8 pins Output dedicated port: 1 port/4 pins © An initial reset terminal is provided. O Built-in oscillation circuit for system clock Two kinds of oscillation circuits are available: one for the system clock and the other for clock oscillation. © Number of instructions: 134 © ROM: 2,048 x 16 bits O RAM. 152 x 4 bits O Form of shipment: ipso (or chip) No.2058-2/24

Application Development Support System An evaluation chip (LC5897) and special devices for the application development tool will be provided. © $DS410 system Enables the user to create an application development program in assembler language (edit-assembling). © EVAS510 + TB5812 + DCB1 + Application Evaluation Board + LC5897 Modification and debugging of the application development program are possible by connecting to the SDS410. The EVA510 is identical with the EVA410 except that the control ROM has been replaced. © 1785812 + DCB1 + Application Evaluation Board + LC5897 Load and evaluation is possible using the EPROM (2732) in which the data for the appli- cation development program is contained. Note) The application evaluation board is created by the user. Either LEDs or on LCD can be used as the display element. Application Examples © Portable equipment (camera control, various card controls, high-quality electric calcu- lators and timers) © Acoustic equipment (electronic control, electronic tuning, and clocks) O Household electrical apparatus (remote control, and timer contro!) © Telephone equipment (telephone control, and display control) No.2058-3/24

= ae Ko gs Ks . P1—P4 Ey ‘ fe ROM .| | RAM 3kH ene }— 2K x16 152 x4 aa bit (Cy rere KL wr | Min Tt | cnt ne lore PPER GH ty ment 5 : po Ld Int ar System bus 16 bit a sR SO _ ls es Fo A Fo rer F) = zal UP/DOWN ™ STOP| HALT] xe | Ne [| ier [sor] fe Ly F Hy ion ons By | FEE hE period 1 Bl TESTI i i W " ose: [rOcROUT TEST2 OCRIN o> TO cuPt ali | fen, I Ir. cuP2 Predivider osc2 OxouT RES Segment PLA OXIN i ] ww: <—ovop LCD driver ALARM OVss1 control . <—OVss2 ToS eee <—OVss3 835 3 ) & 123 \\———Segment 42" ALARM com OP: Date pointer STS3. Status register 3 BNK: Bank register STS4: Status register4 ~ WR: Working register CF: Carry flag AC: — Accumulator ZF: Zero flag ALU: = Arithmetic and logical unit WRFO: Working flag 0 INT: Interrupt control WRF1: Working flag 1 circuit BCF: Test flag PC: Program counter SCF1: Sport flag UP/DOWN CNT: SCF2: STS4 flag Decimal up/down SCF3: K port flag counter SCF4: Divider overflow TIM: — Preset timer flag IR: Instruction register SCF5: UP/DOWN CNT STOP: HOLD control circuit overflow flag HALT. HALT control circuit SCF6:_ Timer overflow flag SCG: System clock generator SCF7: INT signal change STS1: Status register 1 flag STS2: Status register 2 ICF: Internal clock flag - No.2058-4/24

Application Circuit — Example (1/3 bias — 1/3 duty) LcD Pt OOM? P2 COM2>—J (1/Sbias-1/3dury) eas an 42x3=126 rex iseean Ot} K3 segment outputs occa ct Ot} HK 4 key matrix Yoo, Eat ls) VSS1 el “he ol Mi vss3 Ma CUPI XIN CUP2, Te 6332.768kHz XOUT canAP™ f) iN X INPUT/OUTPUT § | tS PORT P1-4.M1-4 Sor NTI INPUT PORT cNT2 K1~4,Si-4 S RES fr LUGHT| {) \\ LS Unit (capacitance: F) Pad Arrangement of LS! Chip a comfo7woo00c000000500000000000 0 oN|TEST 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 64 53° | CUP 50 0 s4]0 76 4g a] s2 eNnTi [O77 4g.0| Mt 47a | M2 46a | M3 cNT2 | 0 78 45 a} M4 LIGHT |o 79 4g 0] TESTI ALARM | 0 80 43 0| TEST2 vss3 | 0 81 42 0] INT vss2 |o 82 vss1 | 0 83 vpp}o 1 XIN |O 2 _ xOUT |G 3 (0.0) 41 0] RES / CRIN] o 4 40 0] Kt cR OUT} 9 5 39 0] K2 s3|o6 - 38 a| K3 Pi }o 7 p2|o0 8 p3}o 9 37 0] K4 36 0 | TEST 35 0 | TEST P4 }0 10 1112 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3233 com2|o05DG5o000 DD O00G0000 0000 5 340] TESTS 8 Chip size: 7.46mm x 5.69mm Thickness: 480}im Pad size: 120m x 120 um No.2058-5/24

QIP80 pin arrangement QIP80 pin arrangement Pad | Pad name Pad name x Y tum _| tum Ne. | wm | com |.

72 Vpb +214 32 | 43 TEST2 +3581 +878

73 XIN +3 33 | 44 TEST1 " +1105

74 XOUT -176 34 | 45 M4 +1285

75 CRIN 369 35 | 46 M3 “ +1465

76 CROUT —549 36_| 47 M2 " +1645

77 6 $3 —1048 37 | 48 M1 +1825 78 7 PI —1228 38 | 49 $2 +2005 79 8 P2 -1408 39 | 50 si +2317 80 9 P3. —1588 40 | 51 CuP2 +2497 1 | 10 P4 2380 - | 52 TEST +2696 1 com2 —2696 41 | 53 CUP1 +3300 12 cOmM3 ~—3367 | -2696 42 | 54 seg +3059 13 seg —2823 " 43 | 55 +2764 14 2528 “ 44 | 56 +2469 15 —2233 " 45 | 57 +2174 7 | 16 —1938 46 | 58 +1878 8 | 17 ~1643 47 | 59 +1583 9 | 18 -1347 48 | 60 +1288 10 | 19 —1052 49 | 61 +993 11 | 20 —757 50 | 62 +687 21 462 63 +381 22 —156 64 +75 23 +150 65 -231 24 +456 66 —537 25 +762 67 —843 17 | 26 +1068 56 | 68 -1149 18 | 27 +1374 57 | 69 ~1455 19 | 28 +1680 58 | 70 -1761 20 | 29 +1986 59) 71 —2067 21 | 30 +2292 60 | 72 —2373 22 | 31 +2598 " 61 | 73 —-2679 " 23 | 32 +2904 " 62 | 74 seg ~2985 24 | 33 seg +3210 ” 63 | 75 COM1 —3581 25 | 34 TESTS +3581 “ 64 | 76 84 " +2101 - | 35 TEST —1795 65 | 77 CNT1 “ +1849 . — | 36 TEST —1584 66 | 78 CNT2 +1298 26 | 37 K4 —1402 67 | 79 LIGHT +1114 27 | 38 K3 —1049 68 | 80 ALARM +934 28 | 39) K2 —868 69] 81| Vgs3 +754 29 | 40 | ki —515 70 | 82| Vsso +574 30 | 47 | RES +3681 | —335 71 Vss1 $394 @ The values (X, Y) indicate the coordinates of each pad center with the center of the chip as the origin. @ The TEST terminal should be open during normal operation. © If the chip is used, the substrate must be tied to Vpp. No.2058-6/24

3 ° Fs 8 o> i= 3 ge ; 3 g€ s o5 a Ba sz ao = ES 8 ° | be 3 2 leks = FSss

5 Ras a : :

¢ > Zee F iad F < Ss 2 3a 2 2 B 5 * 6 - 3 6 s sot a © 2a x x= 2 S225 ° F re 3 = = 288s oI 8 bd gS Ey = 2 @

3 Zefa 3 3 3 xgis

zB “po Fy 5 2 an aee-9

2 SES z 2 z 22zg2

# ees E r : ici => o- 8 = e+ 2e 2 ABS BSE 3 cS 6 Baz A oes Se2 5 § g SERRE 55 2 B38 Fs 2 g $334 geg | 878 8 8 F etez sao |eca 3 3 3 =a ess boES) B a a xs a 2 ot § 3% > & B GE ws 2 f=} 3 & 5 = £ 2. aan 2 2 g2 X 3 eo sot . is Eon 8 ga cox é : Q cf B BS 2208 S = o TP 9 ~ Bb Fo Sa0nN Ss < 5 BS > $ #8 ae g = 2 £8 2 gx

5 BS 5a ge 2 € 58 ¢€ ge

xn 5&2 SSzo g s& x 8s ¢ $6 2 23 sHZEZ £ <& s -e § go xebs Beg e > et S$ EB & fs eosgR 2585 Buck Eo 2 2s ; mes og°% pers = os 2 5 3 8

62 Bu cece BS6e°e < 8s € Se 8

BEES se 50 gene 2 0 = Eg = Seee| #286 | SESR e £2 = |28 $ SSa5| 2585 | ass s co 8 |£3 a ES8g/|Eooss 3 O56 222 & se 4 ESP S| ELLs8 go Bee § zs Sess] 8b ave 322, 550 © Ecc 3 SSesl|yusac§ Spt peat ¢ S§ € aCofl|sszis e258 8508 2 Be 5 8 >= 5 25 32 2:8 i ®xe8|SobE seo5 Seeessez lee = Bore} @eses 238 son ness | es 2 BESE | RR aeES| ESBS BeeesezelseE = eEze2|sct8s8 aeso Se2s2be|/ge& g o~ $ 3 ofl se foo -~ i i= a 8x3x|fFs2E8 |S5e8 ea ge é & ~~ §| € Be onda seous vonse wu 6 vonae spew word ream | 35 ee F SE] ateros|s ad Q 2] > g 3 a 69 AER oS > Oo: Be|> > $ 5S o£ 2 € z 8 al a cas ss . . s 53 2 3 32 8 3 as g 2 ag a a £8 é ls £8 £ £ ze|2|8 EE/ZI<a Ee|= enone caeeeal]eans 5 e x | x BBBS QLRE SSS5/ Uv Zz * No.2058-7/24

& | 3% 3% Sx a Bs as as £ 5 Se SE

5 Bg 2 or

8 re. ze re. Sa Se < see seelstPet 6 |F8S |Ses|igs 8 = a 78s PseRloss zr) g A ° 3 2 2 = = 2 x8 P= 8a s gua Fy 23 $2 3 ga 28 3 zeae 2 ss $8 88 OF 2 ‘eS oO lgPe |2F | 22 § 2 558 |55 |55 e 8 Z2an/22 | et go SsSxvE/ 55 $5 a & B85 )88 BB a Seo /ss | 3s F.8 287 a] 38 38 Sen Nan Ps Ras = BES@|hHE | E $8s esPsglecs Es = 2 8 . £ $ 5 < 2 y £ Bo 8 12 |2 w |8 FS ° 3 = 2 Ey gs = |2 g = 8 8 z 8 Q 3 -

3 E x 3 = oe

= 2 3 8 |£ |s 8 {8 5 2 82 = 13 |e 2 {8 3 ~ oF > 2 3 6 g 8 a s iy 2 £ NSB |e] e2 3 os > iy nu a s neoe ElE: id 5 2 |s a uae 2s S 4 £ EP | geFeg eles |2 Egs |o * Fs a tose 2) 50 3 ers a at 7k oe ge & gs zg BB |BEefe |8|s% le Po > a ges) 888528 &) 23 5 582 Ps 8 85s | 82583 3 | a3 s fee slole/é 2

3 Boe, 3eo8 83 Z| sz 2 258 818]/8) § &

4 22e)/EF2e292827/8)/4§ 8 E22] jojojo/s

5 Sa8)/so228ee/a\\/45 8 Sane =

2 ct 2 < i Bs. / Bas af lang € Boao

5 SSSI /S° ESSER |e | BB § S3fc8

6 68S [S64 78ES[E| SS 8 63ers Q 8/8 8 8 Bg gs = Oo B 8 > Psy s 3 =] Sa] 38 a a 22/8 & 2 25] 5 5 5 -9o le} o ° 3 = felen = ir _ rao eB|EE Fj < o/885|\\/Ea |BE5 52|22 9 a 98/68628!155)}6550 No.2058-8/24

¥ ¥

3 E ° E °

Fy os ° £ > 2

2 BF v3 Be BF of 8

€ 3 iz 2 p38 & 28 E 5 & gEgucptas, | & ffagsautes. ° BS vesoszEeszy YZ vpessZsesse 2 & Bee#8Ens a3 8 R252 Seor25 s | FcbOULYSEC UY | SF -ESECL USGL Y

6 ZSSsoF Sesc: i=} S9e5: egsere

£s0 @ 280 8 g a 3 © g 3 & 3 £8 ¥ ae 3 g 36 2 & ees 2.3 sts ste a bes gas 35865 : 53398 § . aot . BU 3 S ssc is £358 22 = goaas ees 3 £8802 a8 8 8 4 Qe SB 6§c5 2265 [oad Ooa se oss o a a = SB6CE ©8o0 = ze? o 2 Fa ” s g S38 E 2 256 E 3 , 8S £2E & 8 Eee s & 8 3S BSGy &F 3 BoPyx =F i = 3 =83% 58 3 238% = E 3 § o8'8 & 8 Ss%s 6 5 2 es FesE = + €98E = 3 a S Bees F 5 £2er 5 3 a B BIBS 2 B £FUBS 2 a -2#mog 3 :FmOf 8D gs ’ £8ee2% 8 £5223 2 | 3 é 5 ,2e8S58 B ,2h8SRR 8 8 is 3 goceaets 8 g5eece 3

3 SBxe SES F SBy SES 2 z 3

5 |sbegee2 2 |ebiesee 2 | 3 a rs ae&8eE52 § asF&E8eEesr §& & S fe 23. as 2 SRBesrF at B . $ S228- 25 & S'28-88 2B 5 Sgeeege s | sgtseze F_ | 8 3 EcoHOel aeleesGGeS «ag 2 ce Seo tFSe SE |S §o OSE SEE 38 Boeeees Al ELE sees Tals € FEZEDES Eo | BEPESSS EQ/8 §8 BERET OSL ES | SERFEGS_ES | ¢€ ss SS 22#SSe Ra | SES SLOSS eR. | E Se gocesiss 22) 8ftessssse | 38 OfsF FP oRe ofS 5208Fe]8 Cac OF ate Et lof ae Pe £5 13% 22 . Gr aE BERGE ogres aor Ee cee B S uondo 2 > & naorseu Bh Y | g £3 \\ > y > g bf 25 8 a ¥ Q > § 2) 2 fo iz! s 2 s S oe B B Fy 3S > > ¢ 8 E 28 = ag 8 £8 3 z = . a 2 Oo E -_ 3S € E o ao) @ 2 Fy ar =] Ee] 2ese gs FEREEEEL|2 € i fe) = EG a2 Sm NRANHHH 3 Be] sie Peo ww aw us | oo £ lad not. noo FRFRFREEFF!] OO 2 No.2058-9/24

Oscillation Circuit Option CR & X’tal Cycle time = f,/4 Yoo Output from the divider circuit is System clock used as program timer input Ly Timing ES ignal Leo d i f ’ 7 | a) signal, rive waveform C chow) tor ™ generating signal, or interrupt " srop AT signal generation, etc. . Note) For X’tal = 32.768kHz, set , Rd=02 byeyeceD Died circuit Tye Xa By eeeeeeee aie CF & Xtal Cycle time = f,/16 Veo Output from the divider circuit is oF System clock used as program timer input C orw) —- oF ; . & 7 1. | ose Hf signal, LCD drive waveform rasp C crovr_) for i generating signal, or interrupt b HALT signal generation, etc. me Note) For X’tal = 32.768kHz, set a Rd=0Q aaa circuit aC Kur) Xl Pi war ee eee SIS CR option Cycle time = 1/4 v Output from the divider circuit is u System clock used as program timer input Corn) aft . . eT | ose of |signal, LCD drive waveform o igenera-[ 1! ao. . itor ts | generating signal, or interrupt " HALT signal generation, etc. stop | Con) — (eI circuit Continued on next page. ~ No.2058-10/24

a Continued from preceding page. CF option Cycle time = f,/16 Output from the divider circuit is re System clock used as program timer input i AS - w signal, LCD drive waveform for v4 generating signal, or interrupt 6 ‘wat | signal generation, etc. a LC5812H only. Cx) Woes X'tal option Cycle time = f2/4 Output from the divider circuit is System dock | used as program timer input ~| P| " signal, LCD drive waveform Chor) tor 74 generating signal, or interrupt signal generation, etc. Note) For X’tal = 32.768kHz, set . Rd = 02 Com) = at) Birrer ere hs No.2058-1 1/24

— eee Input Port Option hoa +The Hold Tr option + ape is used to reduce the is used. UL level Hold Tr current required for a push-button switch for S1, or a slide switch for $2. +The “L” level signal can be held after the pull-down resistor is set to ON for a short period of time by software during the opening of input. “L" level Hold Tr +The pull-down Tr + can be used as a pull- is not down resistor, used. “The pull-down Tr can be set to ON/ OFF by software. Tr. for pull-down resistor These options are provided for the S, K, M, and P ports. Be sure to specify NOT USED for the M or P port when using it as an output port. No.2058-12/24

LCD output options for the LCD drive, the CMOS output port and the Pch open drain can be selected, LCD drive © Terminal for LCD segment drive, e@ The drive method is determined according to the LCD lighting system specified separately. The LCD lighting system is common to all terminals, and can be selected from among the static, duplex, 1/2 bias- 1/3 duty, and 1/3 bias-1/3 duty methods. CMOS output port e General-purpose CMOS type output port. Pch open drain General-purpose Pch open drain type output port. output port e Usable according to the PLA option for the predetermined ports. Alternating waveform for the LCD driver for LCD output is generated by hardware logic. Segment PLA Circuit The following figure is a schema of the structure of the segment PLA circuit. Data bus (DBUS) {i Segment PLA circuit (PLA) Dat Program Control Data {0D} circuit] Leo Leo Lep memory circuit memory — latch ari ane! {ROM) (eT) (RAM) Strobe| circuit river be Strobe PLA Pee [circuit The contents of data memory are sent to the LCD latch circuit for display either as is or after being decoded by the data decoder. The PLA circuit is used to rearrange the input data to output it to the display latch. With this circuit, data memory can be edited to suit LCD panel specifications without software processing. The PLA circuit can be specified by ROM for PLA, which is supplied with program ROM. * No.2058-13/24

The following frequency divider output can be used directly as an alarm output: : 1) Output signal either as 63 or 64 or 65. 2) Any combination output signal at 610, 611, 612, 613, 614 and 615. 3) Modulating output signal of 1) or 2). These signals can be output by software. ; ON indicates the output at the Nth step of the oscillator frequency divider. Resetting Internal Logic There are three functions for resetting internal logic: @ Built-in power-ON clear circuit ----- Use of this option can be determined by the mask option. @ Reset terminal RES ® Simultaneous operation of $1 through S4 ----- Use of this option can be determined by the mask option. These reset functions are explained below. 1) Built-in power-ON clear circuit The initial-clear circuit provided in the microcomputer automatically operates and resets internal logic when power is turned on. This function is very useful in that it can be activated without external devices. But it has the two disadvantages listed below. It is, therefore, recommended that this function be used with other reset functions, or that other methods be used according to applications. Disadvantages: a) The circuit may not operate under certain power-rise conditions during the power-ON sequence or due to chatter. b) Malfunctions may take place due to pulse noise in the power or a sudden change in status. No.2058-14/24°

One of the following two reset options can be selected: INHIBIT: The built-in power-ON clear circuit is not used . ---- Use this option where malfunctions due to pulse noise in the power may take place. NORMAL ACTION: The built-in power-ON clear circuit is used. --- This option should be selected only when pulse noise does not affect the power. 2) Reset terminal RES When the reset signal is fed to the reset terminal, the reset flag in the micrcomputer is set and part of the divider circuit is reset. Internal logic is reset by the internal reset flag which is reset by the overflow signal from the divider circuit. The reset status of the logic circuit is released and the program coutner starts operating. A Reset flag From reset terminal Thtegrating : circuit Initial-clear signal { in microcomputer . From other reset signal Voo Voo Voo RES To integrating Res ope circuit a Vss2 Vsse as Vss2 . a) with Pulldown R (H-RESET) b) with Pull-up R (L-RESET) - No.2058-15/24

3) Simultaneous operation of $1 through S4 By applying Vpp level voltage to $1 through S4 simultaneously, internal logic can be cleared (initial clear). (Use of this option can be specified by the mask option.) $1 signal $2 signal Reset flag $3 signal BD } > 5 0 Initial-clear signal { in microcomputer $4 signal From other reset signal R Interrupt Function e Five factors and four vector addresses are provided for the interrupt function. — External interrupt terminal (INT) } s tor add — Change of signal to port S ro K ame vector address — Underflow of programmable timer — Overflow of divider circuit — Overflow/underflow of decimal UP/DOWN counter No.2058-16/24

© Can stop the CPU’s system clock in HALT mode with the HALT instruction. © Reduces the operating current to the oscillation circuittHALT release signal+LCD drive circuit current during HALT. . @ The following five factors cause HALT release request signals: — External interrupt terminal (INT) — Change of signal to port S or K ~ Underflow of programmable timer — Overflow of divider circuit — Overflow or underflow of decimal UP/DOWN counter The factors for the HALT release request signal are the same as those for the interrupt request signal, but the use of any factor can be specified in programs. If an interrupt occurs in HALT mode, the operation called for by the interrupt is performed, and the CPU returns to HALT mode. Interrupt (Underflow of timer) Program retin KorKe 4 KeaXen Xn KE iain ae (et --~—----- 8X Ye es} -- Instruction at a HALT mode vectored address HALT mode Release of HALT by Interrupt : No.2058-17/24

© Can stop the operation of the oscillation circuit (OSC1) in HOLD mode with the STOP instruction. ® Reduces the current dissipation to the minimum during HOLD because OSC1 and CPU are stopped. Relationship between the oscillation options and the HOLD release functions i 1 HALT Item Reset signal nterrupt release Note (RES/RES) request signal | request signal fcropion [Of fd [creption [Oo | X'tal option x HOLD function can not be used. O: can be used to release HOLD. X: cannot be used to release HOLD. Decimal UP/DOWN Counter Function A hardware function that counts external pulse or the internal reference pulse in decimal notation. One of the following three operations can be selected by software: @ The counting of pulses from port K4 with UP and DOWN switched by the signal level of port K2. @ The counting of pulses from port K4 with UP and DOWN switched by the phase difference signal of port K2. ® The counting of divider circuit signals of the oscillator in ascending order. ----- With this function, a chrono counter in units of 1/100 second can be implemented by using a 32.768 kHz crystal oscillator. oo No.2058-18/24 «

Option List , when the LCD all used as general- 1/2 bias 1/3 duty 1/2 bias 1/3 duty Purpose ports. 1/3 bias 1/3 duty 1/3 bias 1/3 duty S ports (S1 to S4) |“L” tevel Hold Tr is used. “L" level Hold Tr is used. “L" level Hold Tr is not used. |“L” level Hold Tr is not used. | M ports “L" level Hold Tr is used. “L" level Hold Tr is used. | (MI to M4) “L" level Hold Tr is not used. |‘‘L’ level Hold Tr is not used. = | K ports. “L" level Hold Tr is used. “L" level Hold Tr is used. BI} AK1 to K4) “L" level Hold Tr is not used. |*L" level Hold Tr is not used. s_ | INT port “LY level Hold Tr is used. “L” level Hold Tr is used. y “L” level Hold Tr is not used. |‘’L” level Hold Tr is not used. P ports (P1 to P4) |"L" level Hold Tr is used. “L" level Hold Tr is used. “L” tevel Hold Tr is not used. |“’L"' level Hold Tr is not used. Oscillator selection CR & XTAL CR & XTAL Do not specify CF on the it is not allowed model. i Interna! power-on Unused Unused reset function Used Used Simultaneous opera- | Used Used tion of St through Unused Unused S4 for reset Selection of RES “H" level reset (Pull-down) “H" level reset (Pull-down) polarity “L” level reset (Pull-up) “'L" level reset (Pull-up) Selection | CNT1 “H" level during reset “'H" level during reset of output {Normal “H’) (Normal “H’") terminal “LU” level during reset “L" level during reset polarity (Normal “L‘") (Normal “L"’) CNT2 “H” level during reset “H"' level during reset (Normal “H") (Normal “H’’) “L* level during reset “L" level during reset (Normal “L’’) (Normal ‘’L”) ALARM |“H” level during reset “H'" tevel during reset {Normal “H) (Normal “H’’) “L” level during reset “L* level during reset {Normal “L’) (Normal “L’’) LIGHT “H” level during reset “H" level during reset (Normal ’H’) (Normal "“H”’) “L" level during reset ““L" level during reset . {Normal “L") (Normal “L") No.2058-19/24°

Lc5812 . Vpp=0V = 1/2bias 1/2duty Item Symbol Conditions Terminal Min) Typ Max — Unit Absolute Maximum Ratings Ta = 25°C, Vpp = OV Maximum supply voltage Vss1 —4.0 +0.3 v Vgs2 Vss2=Vss3 ~4.0 +0.3 v Maximum input voltage VINt Vss2 +0.3 Vv . -0.3 Maximum output voltage VouT1 Vss2 40.3 v 0.3 Operating ambient Topr -20 +70 °c temperature Storage ambient temperature Tstg -30 4125 °c Allowable Operating Conditions Ta=—20 to +70°C , Vpp = 0V Power supply voltage Vss1 -3.6 -1.3 v Vss2_ Vss2=Vss3 —3.6 2.0 Vv “H” level input voltage Vint RES 0.25 () v Vss2 ViH2 Input terminals 0.3% v other than RES Vss2 “L” level input voltage Vint RES Vss2 O7x Vv. Vss2 ViL2 Input terminals Vss2 0.7K Vv other than RES Vss2 Operation frequency fopg] — Vggq=—2.0 to—3.6V. XIN/XOUT 32 33 kHz . fopg2 Vss2=—-2.3 to —3.6V CRIN/CROUT 17. 33 50 kHz Electrical Characteristics Ta=—20 to +70°C , Vpp = OV Input resistance RintA Vss2=—2.9V, “L" level hold Tr 60 500 kohm VIN=0.8Vsgo “1, Fig. 1 Rinia Vsg2=—-2.9V, “L" level pull-in Tr 200 500 2000 kohm : VIN=Vop “1, Fig.1 Rin2a Vsso=-2.9V, “L" level hold Tr 50 500 kohm Vin=0.8Vssa" *2, Fig. 1 Rin2B Vgg==2.8v, “L" level pull-in Tr 200 2000 kohm . Vin=VbD "2, Fig. 1 Rin3- Vgs=—-2.9V RES, TEST1, TEST2 10 80 400 kohm “H" level output voltage VoH(1) Vss2=-2.4V, ALARM,LIGHT,CNT1, -1 -03 Vv loH=-0.4mA CNT2 “L" level output voltage VoLi1) Vss2=-2.4V, ALARM, LIGHT,CNT1, Vss2_ Vss2 v toL=0.4ma CNT2 40.3 =H “'H’" level output voltage VoH(2) Vss2=-2.4V, Port M, port P -1 -03 v 1OH=—90pA “H” level output voltage VOoH(3) Vss2=-2.4V, Port M, port P 06 —0.2 Vv IoH=—-50pA “L'" level output voltage Voui3) Vss2=-2.4V, Port M, port P Vgs2 Vss2 Vv toL=0.1mA +0.3 +1 “H" fevel output voltage VoHi4) Vss2=—2.4V, Segment -1 -0.3 Vv IOH=—20A “H” level output voltage VoH(5) Vsso=-2.4V, PAD No. -0.2 Vv 1QH=—0.4pA 13 to 21, 54 to 61 “L" level output voltage Vota) Vss2=-2.4V, QIP 80 pin number Vss2 Vss2 v loL=40pA 4to 12, 42 to 49 40.3 H “L’ level output voltage VOL(5) Vss2=-2.4V, Vss3 Vv 1oL=0.4uA 40.2 Continued on next page. No.2058-20/24

Continued from preceding page. Item Symbol Condition Terminal Min) Typ Max — Unit “H" level output voltage VoHi6) Vss2=-24V, Segment -1 -03 Vv loH=—5pA “H” fevel output voltage Voni7) Vsso=-2.4V, PAD No. -0.2 v IoH=—0.4pA 22 to 33, 62 to 74 “"" level output voltage Vot(e) Vss2=~-2.4V, QIP 80 pin number Vss2 Vss2 v toL=20uA 13 to 24, 50 to 62 40.3 +1 “L" level output voltage Voui7) Vss2=-2.4V, Vss2 Vv 19 L=0.4pA 40.2 “HI” level output voltage Vonie) Vss2=-2.4V, Common 1 — 2 0.2 v loH=—4pA “M" level output voltage Vom Vssg2=-2.4V, Common 1 — 2 Vss2/2 Vss2/2 Vv loH=—4pA -0.2 +0.2 1oL=4pA “L” level output voltage VoLis) Vss2=-2.4V, Common 1 — 2 Vss2 Vv IoL=4uA +0.2 Output voltage Vssi Vss2=—-2.9V C1=C2=0.1NF -1.35 Vv fopg=32.768kHz Power supply current \\Ippt Vgsg2=—-2.9V C1=C2=0,1nF 5 pA Ta=25°C Cl=25kohms : STOP fopg=32.768kHz Co=Cg=20pF Fig.2 Oscillation start voltage [Vstt| Co = Cg = 20pF Fig.3 2.2 Vv Oscillation hold voltage IVHOLDI Co=Cg=20pF Fig.3 - 2.0 Vv Oscillation start time tstt Vss2=-2.9V Co=Cg = 20pF Fig.3 10 s Oscillation correcting capacity 20P Vgg2=—-2.9V XOUT pin 18 22 26 pF CR oscillation characteristics fcR Vss2=—2.3V to —3.6V REXT=510kohm 16 33 50 kHz CEXT=30pF Fig. 4 No.2058-21/24

£05812 LC5812 Vpp=0V = 1/2bias 1/3duty item Symbol Conditions Terminal Min Typ Max Unit Absolute Maximum Ratings Ta = 25°C, Vpp = 0V Maximum supply voltage Vss1 —4.0 +0.3 Vv Vss2__ Vss2=Vss3 “4.0 +03 v Maximum input voltage Vind Vss2 +0.3 Vv 0.3 Maximum output voltage VouT1 Vss2 +0.3 Vv 0.3 Operating ambient Topr -20 +70 °c temperature Storage ambient temperature Tstg -30 4125 °c Allowable Operating Conditions — Ta=—20 to +70°C , Vpp = OV Power suppty voltage Vss1 -3.6 13 Vv Vss2__ Vss2=Vss3 —3.6 -2.0 v 5.0 -3.9 Vv “H" level input voltage Vin RES - 0.25X (e) v Vss2 ViH2 Input terminals 0.3x v other than RES Vss2 “L" level input voltage Vivi RES Vss2 0.75X Vv Vss2 ViIL2 Input terminals Vss2 0.7% Vv other than RES Vss2 Operation frequency fopg1 Vsg2=—-2.0 to—3.6V XIN/XOUT 32 33 kHz fopg2 Vsg2=—2.3 to -3.6V CRIN/CROUT 16 33 50 kHz Electrical Characteristics Ta=—20 to +70°C , Vpp = OV Input resistance RINIA Vsg2=-2.9V, “L"" level hold Tr 50 500 kohm Vin=0.8Vsso "1, Fig. 1 RiniB Vss2=-2.9V, “L" level pull-in Tr 200 500 2000 kohm Vin=Vop “1, Fig.1 Rinza Vssg2=—-2.9V, “L" level hold Tr 50 500 kohm ViN=0.8Vgg2 "2, Fig. 1 Rin2B Vss2=-2.9V, “Level pull-in Tr 200 2000 kohm Vin=Vpb "2, Fig. 1 RIN3 Vss2=—-2.9V RES, TEST1, TEST2 10 80 400 kohm “H" levet output voltage VoHi1) Vss2=-2.4V, ALARM,LIGHT,CNT1, —1 -0.3 Vv loH=—0.4mA CNT2 “L" level output voltage VoLt1) Vss2=-2.4V, ALARM,LIGHT,CNT1, Vss2 Vss2 v 1oL=0.4mA CNT2 40.30 «+1 “H” level output voltage VOH(2) Vss2=-2.4V, Port M, port P -1 -0.3 Vv 1OH=~90A “H" level output voltage VoH(3) Vss2=-2.4V, "Port M, port P 06 -0.2 Vv toH=—50pA “L" level output voltage Vou(3) Vss2=-2.4V, Port M, port P Vss2 Vss2 Vv loL=0.1mA +0.3 +1 “H" level output voltage Vou(4) Vss2=-2.4V, Segment -1 -03 Vv loH=—20uA “H" level output voltage VoH(5) Vss2=—-2.4V, PAD No. -0.2 Vv 1QH=—0.4pA, 13 to 21, 54 to 61 “L" level output voltage Vot(4) Vss2=-2.4V, QIP 80 pin number Vss2 Vss2 v toL=40uA 4to 12, 42 to 49 +0.3 +1 “L" level output voltage VOL(5) Vss2=-2.4V, Vss3 Vv Io =0.4pA +0.2 Continued on next page. No.2058-22/24 ,

Continued from preceding page. na Item Symbol Condition Terminal Min Typ Max — Unit “H" level output voltage VoHie) Vss2=-2.4V, Segment -1 -0.3 Vv {at CMOS output port) loH=—5yA “H" level output voltage Von(7) Vss2=-2.4V, PAD No. a) v 1OH=—-0.4yA 22 to 33, 62 to 74 “L" fevel output voltage VOL(6) Vss2=-2.4V, QIP 80 pin number Vss2 Vss2 Vv (at CMOS output port) VOL=20pA 13 to 24, 50 to 62 +0.3 +H “L" level output voltage VoL(7) Vss2=-2.4V, Vss2 v lol =0.4pA +0.2 “H" level output voltage Von(s) Vss2=—2.4V, Common 1 — 3 -0.2 Vv IOH=—4uA “M" level output voltage Vom — Vss2=-2.4V, Common 1 — 3 Vss2/2 Vss2/2 Vv loH=—4pA, 0.2 +0.2 IoL=4uA “L" level output voltage Vot(s) Vss2=~2.4V, Common 1-3 Vss3 v loL=4yA 40.2 Output voltage Vss1 Vss2=-2.9V C1=C2=0.1uF 1.35 Vv fopg=32.768kHz Power supply current llop| Vss2=-2.9V C1=C2=0.1pF 5 yA Ta=25°C Cl=250hms STOP fopg=32,768kHz Co=Cg=20pF Fig.5 Oscillation start voltage [Vstt] Co=Cg=20pF Fig.3 2.2 Vv Oscillation hold voltage IVHOLOI Co = Cg = 20pF Fig.3 2.0 Vv Oscillation start time tstt Vss2=—-2.9V Co=Cg = 20pF Fig.3 10 $ Oscillation correcting capacity 20P Vss2=—-2.9V XOUT pin 18 22 26 pF CR oscillation characteristics fcR Vsg2=-2.3V to -3.6V REXT=510kohm 17 33° «50 kHz CEXT=30pF Fig. 4 cAN ——eRoUT fof No.2058-23/24 '

C5812 ' Fig. 1 Input Configuration of $1-4, M1-4, K1-4, P1-4 Fig.4 CR OSC Circuit ; ‘CRIN OR OUT Program Ron applied Cent vase T Voo Fig. 2 Output Voltage, Supply Current, OSC HOLD Voltage Test Circuit Fig.5 Output Voltage, Supply Current, OSC Hold Voltage Test Circuit os Telos «i four Woo yy on % or PLE or in YS Stuloype2 ovr xour|_ Vssi ssa] ba cd ORIN Vss9 Op ——— | Fig. 3 OSC Start Voltage, OSC Start Time, Frequency Stability Test Circuit Fong vs xn curt Ss Jor CUP2 OUT x gyr| CRIN Vssz ss: es Unit (capacitance: F) TE No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. M Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO,, LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Mi Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties, No.2058-24/24