LC382161T-17

LC382161T-17 SANYO | Alldatasheet

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SA'VYO 2 MEG (65536 words x 16 bits x 2 banks) Synchronous DRAM Overview Package Dimensions The LC382161T is a 3.3 V single-voltage power supply unit: mm synchronous DRAMs with a 65536-word x 16-bit x 2-_3914-TSOPS0 bank organization. This DRAM features a large capacity, high speed, and low power due to the provision of 50 {L382161T) 6 synchronization circuits and the use of CMOS peripheral AARARRAAARSARRARARRARARAA circuits. Thus this is optimal for use in a wide range of applications, from main and graphic memory in computers to consumer products. The LC382161T DRAM uses multiplexed address inputs and is packaged in a 50-pin TSOP package that supports ° 4 high-density mounting. This DRAM uses auto-refresh PUUCETEEEE i THU TUEEeTeEE (CBR refresh) performed 512 times every 8 ms as the 08 alos 3 | ozs refresh technique. 21.20 § a 2 Features immo 4 * Organization: 65536 words x 16 bits x 2 banks | + All VO signals (except CKE) are synchronized with the SANYO : TSOP5O (TYPE I!) rising edge of the system clock. * Basic specifications conform to the JEDEC standards for 16 Mbit synchronous DRAM. * A pulse RAS scheme is used. + Two bank internal structure (2 banks x 65536 words x 16 bits). Continuous operation across the two banks is supported via the AQ pin. + Burst length setting (1, 2, 4, 8, or full page) * Burst type setting (sequential or interleaved) * Burst output operations are interruptible. + The CAS latency can be set using an address key. (CAS latency: 1 or 2) + Auto-refresh function * Power-down and suspend operations can be controlled from the CKE pin. + VO byte order is controlled by the DQM pin. * Fabrication in a CMOS process * Single 3.3 V power supply + LVTTL compatible + Low power Standby: 7.2 mW. Operating: 324 mW + Package: TSOP 50-pin (400 mil) plastic package : LC382161T SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 13097HA (OT)/33195TH (OT) No. 5055-1/55

vee [1 50] vss ovo [2 | 29] 0015 oa: [3] jae] 09:4 vsso [4 | vgs0 vez {5 | 26] 0033 003 [6 | 0012 veeo [7 [24] voce oaa[e] a} 0031 ons [3] 2] 0010 vsso [x9] 43] vsso oas [23 20] bos 007 [ra] [5s] 008 veco [13] [39] voco Loom [ra] we WE [5] voom as [16] 25} cLK crc cke = [re] [aa] sc as [rs] 3a] sc a [20 as] nc ao [es 30] 47 az [es 29} a8 a3 a7] as vee [25] 26] vss Tope Pin Functions a a C0 (2 CS [ADI0AB.AS | [Rowaddressinput oa = [asians Aino aasoss not Mog Peverey fodnrebais baw Mpg rd a 2S | a [ee onset cornet [ES] Row asoresssicbecommand a No. 5055-2/55

cK CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CKE input determines whether the CLK input is enabled within the device. When CKE is high, the next rising edge on the CLK signal will be valid, and when low, invalid. When CKE is CKE Input pin tow, the device will be in either the power-down mode, the clock suspend mode, or the solf refresh mode. The CKE signal must remain low for these modes to remain in elect. CKE is an asynchronous input. The CS input determines whether command input is enabled within the device, Command input [os is enabled when CS is low, and disabled when GS is high. The device remains in the previous state when CSis high. tnput pin RAS, in conjunction with CAS and WE, forms the device command. See the “Command Truth v7 input pi Table” item for details on device commands. — TAS, in conjunction with RAS and WE, forms the device command. See the “Command Truth cas “Table” item for details on device commands. WE Input pin WE, in conjunction with RAS and CAS, forms the device command. See the “Command Truth impure Table” item for details on device commands. LDQM and UDQM control the tower and upper bytes of the VO butters. {n read mode, LDQM and UDOM control the output butter. ‘When LDQM or UDQMis low, the corresponding butler byte is enabled, and when high, disabled. The outputs go to the high impedance state when LDOMUDOM is high. 14,98 LOOM, UDQM | Input pin This function corcesponds to OE in general-purpose DRAMS. Inwrite mode, LDQM and UDOM control the input butter. When LDQM or UDOM is iow, the corresponding butler byte is enabled, and data can be written to the device. When LDQM or UDOM is high, input data is masked and cannot be written to the device. AQ is the bank selection signal. 19 9 When AQ is low, bank 0 is selected and when high, bank 1 is selected This signal becomes part of the OP code during mode register sel command input. AB is used as a row address during active command input, and is used to determine the precharge mode during other commands. Input pin IAB is low during precharge command input the bank selected by AQ is precharged, but if AB is high, both banks will be precharged. This signal becomes part of the OP code during mode register set command input. 7 Inout A7 is a column address input. input pin This signal becomes part of the OP code during mode register set command input, AO to AG are address inputs. They are used as row address inputs during active command input 2110 24, A010 AB and as column address inputs during read or write command input 271029 ‘These signals become part of the OP code during mode register set command input. 2.3,5,6,8,9, 11, pars DQ0 to DAIS are VO pins. 12,39, 40,42, | DQ0t0 VO through these pins can be controlled in byte units using the LDQM and UDQM pins. 43, 45, 46, 48, 49 No. 5055-3/55

£C382161T-17 Block Diagram CKE } | ws Command _{f a jecoder 3| i | AAS 3 Row 11 | Memory celt | CAS clock address 8 g |256 array H WE enerator butler \\: i Es 9 Nose | a | Bank 0 -— DOM a9 P| | gsr || : ie { | Dara =) = pose ampbters. UO gate 16 oP rs En Oot av Refresh 230] 8 L]3é [3 Column decoder ae controller [*|sett-cetresh 6s $ 1°s controller 3 a 8 } 1 AS Daia a4 " Relresh Gomamnaioe WOK 16) ouput | 16 a3 counter eel puller x2 [—~y 3 At Row 3 Memory cell © Voge

20 Row address [3 > 8 array vneo

8») address [_Y butter z Bank + ses! latch a ‘A06217 a No. 5055-4/55

Spat [Gordons «dating [a] asm pu spy worage Woeamer[ Stow ea [Oupustoreseuren es | [Soeaingtenpemwe | te |r [Storage temperawe | tag | to Note: 1. This device may be destroyed if stresses in excess of the absolute maximum ratings are applied, DC Recommended Operating Ranges at Ta = 0 to +70°C [eras Symp [aos ee ma] Sanayvotage WWec.veca]SSCSCSC*d vt | ee Pe | [‘putninivervotege Tw |e [rewowieveivetege Py ca | fo Note: 2. All voltages are referenced to Veg. Symbol [onan min [max [Unt [note | ‘Operating current \\ Burst length = 1, tag 2 taag (min), mA (average current during operation} "CS" | tap > tap (min), Iqyt = 0 mA Precharge standby current COKE 2 Vya (rin) [tex=4ns Pie ma Active standby curent CKE 2%, (mag [texeaéns [Os ma {i power-down mode) ‘ ea A Active standby current KE 2 Vy (nin) [toceaens [te ma {0 non power-down mode) " eese Tt ma SC A OVS Vin $ Voc, with pins other [Suowtwireivetege | vo. Jow=2ma did a Pp Note: 3, These are the values at the minimum cycle time, Since the currents are transient, these values decrease as the cycle time increases. Also note that a bypass capacitor of at least 0.01 uF should be inserted between Voc and Vg for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 4. ICC1 and ICC4 depend on the output load. The maximum vatues for ICC1 and ICC4 occur in the Output open state. Sess No. 5055-5/55

£C382161T-17 ce Input/Output Capacitance at Ta = 25°C, Voc = VecQ = 3.3 + 0.3 V, f= 1 MHz [ate Siar ne [npueaactanes @OIOA wf | oe | [aout capachanee (CLK, CKE,CS, AAS. GAS, WE. LoGM, uDaM) | Ce | 5 | oF _| [vO-capaciance (DGdte0a1) TCL? | ee TT] [SAS tenet [tor | | es ee a Access time referenced to CLK [exstaney=1 [tues | |] es [8] [ot hig evel wit te es [CL tw vet with te ts cuit ane nts une [eaSiawney=2@ [ow | «[ | ef [exsteney=1 [tow | v0) ef [Spwowimpesines tie ge of es [Qupurigninpesaening |e 0 es a OS [npteatnoseme gy ef [aaeessseupome tng ae Adaress hold time [we [af ns KE setup time [exes fens KE hold time [tow ffs CKE-GLK recovery delay time [toca [tauren [Command seup ame (5, RAS OAS. WE DOW tes ap oe [ormina noite (TS, RAB. OAS WE, COM) | toe ee [conmenseyoetne eto ReiActoAa) | tag | |) [Commanseyse ime etioPre) tng | 000 | e000] sft [Conmendeysetmeaioaey | te ee [2ee conmandie RW conmanddaayme | rep ef) as [Conmanserc une AeOwae) tea | ef es [easier =2@ | yne | | i re Input data precharge command delay time [wstontwnecmecewne [eprgeerss fee ff} =} Retresh cycle time [ince es Note: 5. When power is first applied, memory operation should be started 100 HS after Voc and VecQ reach their stipulated voltages. Also note that the Power on sequence and an auto-refresh operation must be executed before starting memory operation. 6, Measured with ty = 1 ns. 7. Tho reference level is 1.4 V when measuring input signal timing. Rise and fall imes are measured between Viy and Vj. 8, Measured with the load shown in the figure below. 9. The time tyz (max) is defined as the time required for the output voltage to transition by #200 mV from Voy, (min) of Voy, (max) when the output is in the high impedance state.

0 Nia Ss

—_—- Operating Frequency/Latency Relationships OO Operating requency ee [CAS tatency te et AS to CAS delay time [aco fT acto [RAS tatoney eng 2 eveio [commandoyeletme te a gee _| [BASeyeietime mss ff vee | Precharge oyele time ee ee SS Command oye time (Act 10 Act) a SS Column command cycle time (READ, READA, WRIT, WRITA) | tccoon | ct | ot | yee | Input data precharge command delay time | te {| + | t+ | cee | Input data active (refresh) command delay time [tom | 2 | 2 | oye | Burst stop delay time (read) | _teo [2 ce | [Burst stop delay time wite) too yee | Burst stop delay ime due to precharge (read) [tan | 2 | + | oe | Burst stop detay time due to precharge (write) [wo fo To [oc AAitorecharge stan delay time (reac) a ee DOM to data delay timo (read) [tomo P22 ae | DOM to data delay tne (wie) [tow fo [ocr | Mode register set to command delay time twco 2 2 cycle Output Load 500g TT I | CL=30pF aosa7s eee No. $055-7/55

Active Command Read Command Write Command a AO-A6 TEED 0% TTI ao-a6 ZZZT7TTTTX catunn X7777/TIT ao-45 277777TDX coun 777 a EEX (8 TERT 8 TEX 28 XTZZTLEZT.

1 AUTO PRECHARGE AUTO PRECHARGE

Precharge Command No-Operation Command Device Deselect Command CLK ~~ f CLK f CLK ei ere BANK 0 ang BANK 1 : H © (MX * TEEEETTTETEEET. STE TLEEEXTEEETIXTLZILETI2. No. 5055-8/55

Mode Register Set Command Auto-Refresh Command Self-Refresh Command Power Down Command Clock Suspend Command Burst Stop Command cee ce TA = (ZA vow t cane Wo, 5055-9155

—SSSSSSSSSSSSSSSSSSSSsSSSSse Mode Register Set Command (CS, RAS, CAS, WE = Low) The LC382161T incorporates a register that defines the device operating mode. This command functions as a data input pin that loads this register from the pins AO to A9. When power is first applied, the stipulated power on sequence should be executed and then the LC382161 should be initialized by executing a mode register set command. Note that the mode register set command can be executed only when both banks are in the idle state, i.e., deactivated. Another command cannot be executed after a mode register set command until after the passage of the period tcp, which is the period required for mode register set command execution. Active Command (CS, RAS = Low, CAS, WE = High) The LC382161T includes two banks of 256 rows each. This command selects one of the two banks according to the A9 pin and activates the row selected by the pins AO to A6 and A8. This command corresponds to the fall of the RAS signal from high to low in a general-purpose DRAM. Precharge Command (CS, RAS, WE = Low, CAS = High) This command starts precharging the bank selected by pins A8 and A9. When A8 is high, both banks are precharged at the same time. When A8 is low, the bank selected by A9 is precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period tpp, which is the period required for bank precharging. ‘This command corresponds to the rise of the RAS signal from low to high in a general-purpose DRAM. Read Command (CS, CAS = Low, RAS, WE = High) This command selects the bank specified by the A9 pin and starts a burst read operation at the start address specified by pins AO to A6 and A7. Data is output following CAS latency. The selected bank must be activated before executing this command. When the A8 pin is high, this command functions as a read and auto-precharge command. After the burst read completes, the bank selected by pin A9 is precharged. When the A8 pin is low, the bank selected by the AQ pin remains in the activated state after the burst read completes. Write Command (CS, CAS, WE = Low, RAS = High) When burst write mode has been selected with the mode Tegister set command, this command selects the bank specified by the A9 pin and starts a burst write operation at the start address specified by pins AO to A6 and A7. The first data must be input to the DQ pins in the cycle in which this command is executed. The selected bank must be activated before executing this command. When the A8 pin is high, this command functions as a write and auto-precharge command. After the burst write completes, the bank selected by pin A9 is precharged. When the AS pin is low, the bank selected by the A9 pin remains in the activated state after the burst write completes. After the input of the last burst write data, the application must wait for the write recovery period (tpp,, tpaz) to elapse according to CAS latency. Auto-Refresh Command (CS, RAS, CAS = Low, WE, CKE = High) This command executes the auto-precharge operation. The row address and bank to be refreshed are automatically generated during this operation. Both banks must be placed in the idle state before executing this command. The stipulated period (tg¢) is required for a single refresh operation, and no other commands can be executed during this period. The device goes to the idle state after the device internal refresh operation completes. This command must be executed at least $12 times every 8 ms. This command corresponds to CBR auto-refresh in general-purpose DRAMs. eee No. 5055-10/5$

LC382161T-17 . a SSSSSSSSSSSSSSSSSSSSSSSSeSeeeseseseeeeeeeeSSS Self-Refresh Command (CS, RAS, CAS, CKE = Low, WE = High) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. The self-refresh operation is started by dropping the CKE pin from high to low. The self-refresh operation continues as long as the CKE pin remains low and there is no need for external control of any other pins. The self-refresh operation is terminated by raising the CKE pin from low to high. The next command cannot be executed until the device internal recovery period (t,..) has elapsed. Both banks must be placed in the idle state before executing this command. Burst Stop Command (CS, WE = Low, RAS, CAS = High) The command forcibly terminates burst read and write operations. When this command is executed during a burst read operation data output stops after the CAS latency period has elapsed. No Operation (CS = Low, RAS, CAS, WE = High) This command has no effect on the device. Device Deselect Command (CS = High) This command does not perform any object operation selection with respect to the device. In other words, it performs no operation with respect to the device. Power-Down Command (CKE = Low) When both banks are in the idle (inactive) state, or when at least one of the banks is not in the idle state (inactive) state, this command can be used to suppress device power dissipation by reducing device internal operations to the absolute minimum. Power-down mode is started by dropping the CKE pin from high to low. Power-down mode continues as long as the CKE pin is held low. All input pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. The power-down operation is terminated by raising the CKE pin from low to high. The next command cannot be executed until the recovery period (tx,) has elapsed. Since this command differs from the seif-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (ty,). Thus the maximum time that power-down mode can be held is just under the refresh cycle time. Clock Suspend (CKE = Low) This command can be used to stop the device internal clock temporarily during a read or write cycle. Clock suspend mode is started by dropping the CKE pin from high to low. Clock suspend mode continues as long as the CKE pin is held low. All input pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. Also note that the device internal state is maintained. Clock suspend mode is terminated by raising the CKE pin from low to high, at which point device operation restarts. The next command cannot be executed until the recovery period (t,,,) has elapsed. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (t,,,). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time. ee No. 5055-11/55

SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSsSSSSSSSSeseeSSSSSSS Command Truth Table (Notes 10, 11) cm re Fee mel [om fren on |] [astretsh commend Si rer fw peep wx [x [XX] [nz ve | [Setsetesnconmara id sre Pw pete pt fee] xx] x [x [riz fre | [Precharge seeoestankconmana «ene [ Px {atc [H[ilxes[cpx] x] x || [Peestargepombanis command ————*| pau PH [x|[u][c [wpe |xfespatx] «fx |] [Barkacnaterow seentaconmand «acu | xe | [mw] © 10s [Rowl x] Row x Te] a [wesavorpecaaecommand «war TH | x}upH{u ley @ tes] | coum [xa] [Resconmarg ine Tw Px emp x [espe | coum [x] 7 | [Ressevopresageconnand ~~ eam Tw Px] [wep x [espe] coum [x [a7] [Bustsonconnans Yast ex fiw [etc te|xte[x] x Px [| [Roeperaton nor ep pepe fo] ack suspend made ES CE ee CASS ESCA ESESES HT xfxp xt x] xT x] x [xy x Tien [7 ] DQM Truth Table (Notes 10, 11) (e=i[ [ero [aa waeoupierabe a [Lewerove daawretuputerabe | _enat_[H[x| x] 1 CKE Truth Table (Notes 10, 11) alle oe ed So [2sve Ian cueksnspontmece S| sm fe exe PR | [Gmersenes —Jotecxsuspond i ee px Pex [Goxeeoes —frennanensammeees Ye e a te Ppo Ile Auto-refresh command [rer [aya telcyc[a[x[x] x | [as ———onrarnenne |r He RR etten Pamettmme tt elt-retresh Terminate set-relresh mode po few px fx [xT [x = eee pHtctH[ x|x|x[x]xy x [Rowerdown [Terminate powersownmode | Lt HT x] x| x [x] x Ix KH: A high level input with V,, between V,, (min) and 4.6 V u A low level input with V,, between -0.3 V and V, (max) x Either a high or fow level input High-Z: A high impedance output No. 5055-12/55

£C382161T-17 oe SSSSSSSSSSSSSSSSSSSSSSSssSsSSSSSSSSSSSSSSSSSsSSSssses Operation Command Table (Notes 10, 11) [Goren saie TS JRAS|EAS] We [na [0 [a7 [Sto AO] commana opsaion [no] [a [x [x [x Pcie [x foes, [Ro cperatonerponeraown i a | [Pa Ta Te [x [Tic] [no | Ro open ae ponerown a] [Pe Pa Te Tx [x Dc] fast [no cperton orosveraoun | SN a a [ETOP Pc fx Pc reriseur —Tauoveren creoterem [| pe bebe pacbe pepe osx fesse} a LoD a Te Po [x P| fast Ye spt} epee Ta Dv [v [y [|v _reaomnenba [Resse A POTD x |e Jonereat—[Preonage J a A [ee] x [TD Px Tx oest [urs ced contra row acta whan eane |] [EP Te [coe [efor rst reasconniss, vase wend _[—] [EP Ps Pa PP De x fast st eadinopis ase aternceragt [| PETA TET [vy [vr nBrREAOa [irs cosineripes adres atarraomni | 25 | nese POPPE Te [ov Vv write [erst easier wi san ator mrp [0.28 eee egal orc pe etre peop a [CPE Pe Te |“ oncooeJns Yoga] COESES ES SES CODH Ta [x [x [ic [x [x Jno? [irr te sorives. wt rcovy whan done [| Pepe Te Te Dx [x Po [ x Jost Tussinee nace atria | | [OTH Te Pay |v Tv |v [ReAmrieOA [surat we erste ead sar ater erupt [20.25 a [OPO TH Pee [vx [x _[rneseait [aus wet rieraned peso skermneraet | 20 | 8 a a Dee foc f [Dx [x [ost aura ad conten pectage wien are [| PTET Da Pf fer [senses pete aeesis A a [eT Pe Die a] frst fra _ Continued on next page. No. 5055-13/55

Continued from preceding page. [Gicenisie [ES PRSIERS| WE] Ao [Aa [7 [Avvo] command [Operation ~~ Na] eee [x[x[x]x] x foe [eicirmas ne || precharge when done efwfefe[ eee] x fron [ines ees [| NO vite &avoprecnage FOLK LE Pap [v [vv |reanmenoe [nop ec a a [HD bec] x Px [x |__® Jest No paraion a saw args tas aapeod_—_ |] Pepa Dafa x Pc] [ x |Nor [Noosa ie ste atortgn has eapses |] Pepa TAT. Px [T(x fast No pean ie se atertan has eapses |_| rowpecns = [Epa pC Lee py [ev [wat |iepa | A Pee Pas [vv x [x [eneratt [No psaion ie sae aferige hs eapees [10 ] a a [we fe] [ x Px [x |X Yoest_—— [No peraionrowacve afortagg hes apses | Le Pea [WL [| x [x |HOe [no pean, row acne ater tac has eases] Leta Pale [x Px] x |x Jost —[Noepsaion rowacte ateriaco has oeeed |] renetacy ong CELEEE LED DO [VT nenmeRO Iie P| A ] a Pope pe wpe px xp xf erseur — |ega a [ee [|e Px Tx [Joes [No paraion ew acne aerign has eapsea |_| De De Pa Ta [|x [x nor [Ne operation, ew ace aeripn Pas oapsea | | [epic Perf e [x Pc [x [Jost [Ne parato, ew ace aripa ras eapaea |] oe i a Pepe te fe [op ece was tego [expe] x] x] x [x] _|oest [No cpsaton ie saw atopy tar oapend [| [ef De Tw [x ocx [x Ino [no opaan, est atorign as epee [| Lope Ta [ee [a [x [x [ast | No operation se sn ater nha eupees |] Te 8 8 a TA Continued on next page. No. 5055-14/55

Continued from preceding page. Guransiate [OS RRG[ORS We aa [ns [a7 [Ab t0A0] Conmand_[ ~~ opwaon [Wa] A Retesn | SS A a SS A Note: 10. H: High level input, L: Low level input, X: High or low level input (undefined state), V: Direct input voltage at a stipulated high or low level 11, All input signals are latched on the rising edge of the CLK signal, 12, Both banks must be placed in the inactive (idte) state in advance. 13. The state of the AO to A9 pins is loaded into the mode register as an OP code. 14, The row address is generated automatically intemally at this time. The DQ pin and the address pin data is ignored. 15. During a self-refresh operation, all pin data (states) other than CKE is ignored, 16. The selected bank must be placed in the inactive {idle) state in advance. 17. The selected bank must be placed in the active state in advance. 18, This command is valid only when the burst fength is set to full page. 19. This is possible depending on the state of the bank selected by the AS pin. 20. Time to switch internal busses is required. 21. The LC382161 can be switched to power-down mode by dropping the CKE pin low when both banks are in the idle state. Input pins other than CKE are ignored at this time. 22. The LC382161 can be switched to sell refresh mode by dropping the CKE pin low when both banks are in the idle ‘state. Input pins other than CKE are ignored at this time, 23. Possible if taap is satisfied. 24. Possible if tpag is satisfied. 25. The conditions for burst interruption must be observed. Also note that the LC382161 will enter the precharged state immediately after the burst operation completes if auto-precharge is selected, 26. Data must be masked by setting the DOM pin high when input data is available during the top, period. 27. Command input becomes possible after the period taco has elapsed. Also note that the LC382161 will enter the precharged state immediately atter the burst operation completes if auto-precharge is selected, a No. 5055-15/55

eo SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSssSssSsSsSSSSSSSSSSSSSSsssse CKE Related Command Truth Table (Note 28) rl ae ll AC a A sotvoesn [PET fof] x [Setactosnreovey a Ss a Dafa Pe [eT x [|x fit ae anor has apse] [eT Ta x Po [|x fi site ator Res pees A A sattretosn eeovery LE LED Dc [x [x [|x |Powordoun anita neyo a] OS a [Pe Pe [x ic] [ee sspondomnatonontwnenayse a] Pee Pe PD 9 Ying peo FERS eames — fo I CA Pepa Pee [x Do [ic [|x S00 cpatoncarman ie J a [eae Dep] x aoseemge [EPEC Px [Tx Teco i portion conmandiaie PA TET ETC Ta [ic] [x [sees opsatonconnend we] A Le pe Te Pee [eT op conk — [seein opertonconnandave J AC Da THT [xc P x Pf |x [see te eration conmansiab 5 [Pe [oP fo] Px [x [Xe auepenson me nenyes ther states [OP [xf Pa] x [x 3k cuspona tina nine neneyee Le [uJ x] x [x [x [x [x [x [oioaksuspendieminaton oniherenteyele = Note: 28. H: High level input, L: Low level input, X: High or low level input (undefined state), V: Direct input voltage at a stipulated high or low tevel 29. The CLK pin and the other inputs are reactivated asynchronously by Ihe transition of the CKE level from iow to high, ‘The minimum setup time required before all commands other than mode termination commands must be satisfied. 30. Both banks must be set to the inactive (idle) state in advance to switch to Power-down mode or sell-refresh mode. 31. The input must be a command defined in the operation command table. 32. The period tsmex must be satistied No. 5055-16/55

Two-Bank Manipulation Command Truth Table (Notes 33, 34) co CAS Ag AT | A610 AO Operation [Banko [Banks [Banko [Bark | pe fx [x [xP x PP [Toes pefaqat at [x [x [x [Nop any ay ay ary [awa [aaa es clalulelxllxl x. lest [a [va [wa a pov a [H#[H] ca | a [HHT ca | a DS pH fey ca | | va [wa a ee cfalel a 4 READ |__ awa [va Te a [eta] can [aA ew ae [efey ca] {awa [ww kw [ete ca] [aT pw Le faT ca] PWIA uA [HT aT ca | [rw aa wr tfafefe WRIT Le [ape_| A [ae [ws L} ela} a ACT —- a Depa tx_| a Cc A [a [wat [a A opcope uns Note: 93. H: High level input, L: Low level input, X: High or low level input (undefined state), V: Direct input voltage at a stipulated high or low level RA; Row address, CA: Column address 34. The device state symbols are interpreted as follows. I: Idle (inactive) state A: Row active state A: Read W: Write RP: Read & auto-precharge WP: Write & auto-precharge Any: Any state meee No, 5055-17/55

Simplified State Transition Diagram SAE enty (on) ner ext Mode ans ct register [| Autowelresh set KE. cxe idle act power down Active power down exe ne wary READ ast ost rea {write Zo NT Reas Clock CRE aural neaon SE Ctock suspend suspend exe. {\\ LS xe, cre te Write & auto- Read & auio- precharge precharge Pmt ‘Aulornatic iransition following ine ——>_ completion of command execution ———_ Transition due to command input 103622 No. 5055-18/55

Device Initialization at Power-on (power-on sequence) As is the case with general-purpose DRAMs, the LC382161T must be initialized by executing a stipulated power-on sequence after power is applied. After power is applied and Voc and VecQ reach their stipulated voltages, set and hold the CKE and DQM pins high for 100 is. Then, execute the precharge command to precharge both banks. Next, execute the auto-precharge command twice and define the device operating mode by executing a mode register set command. Mode Register Settings ‘The mode register set command sets the mode register. When this command is executed, pins AQ to A6, A7, A8, and A9 function as data input pins for setting the register, and this data becomes the device internal OP code. This OP code has four fields as listed in the table below. [te ne Note that the mode register set command can be executed only when both banks are in the idle (inactive) state. Wait at least two cycles after executing a mode register set command before executing the next command. CAS Latency During a read operation, the delay between the execution of the read command and data output is stipulated as the CAS latency. This period can be set using the mode register set command. The optimal CAS latency is determined by the clock frequency. See the “Operating Frequency/Latency Relationships” item on page 7 for details on the relationship between the clock frequency and the CAS latency. See the table on the next page for details on setting the mode register. Burst Length When writing or reading, data can be input or output data continuously. In these operations, an address is input only once and that address is taken as the starting address internally by the device. The device then automatically generates the following addresses. The mode register set command burst length field stipulates the number of data items input or output in sequence. In the LC382161T, a burst length of 1, 2, 4, 8, or full Page can be specified. See the table on the next page for details on setting the mode register. Burst Type The burst data order during a read or write operation is stipulated by the burst type, which can be set by the mode register set command. The LC382161T supports sequential mode and interleaved mode burst type settings. See the table on the next page for details on setting the mode register. See the “Burst Length and Column Address Sequence” item on page 21 for details on I/O data orders in these modes. eee No, 5055-19/55

oT oe Te Tornooe Tor] a] SS [we[wi [MoT Sequentas _[tntereaves | Jofofof sf Reserves fofo[s[ 2 Te [ofsfof ie ae susttergh [ofa[af oe fe (i [oTo | Reseveg "| Reserved [a To [a Reseveg | Reserves | itso} Resever | Reserved | [r[r [rj Futpage | Reserves sustype [oT Sequentiat | M4 CHS latency oO Reserved fofofa[ + fo[sfo[ 2 Latencymoes [o [1 [a | Reseves | [1 fofo} “Resenes | Latoli| peseves | [+ }1fo| peseves | [+ [1 [a [eserves [6 [we [wo wi [ofo[o| oeima[Wweaeregsrsee SS Co fof + | oelned | edeC sencasieaseteg = eC [=[= Ta [= Foe comeinatns re nceines. | No. 5055-2055

Burst Length and Column Address Sequence Po Se a a [esr doe [eres eer | [teers fee a a = Fat age) sone Note: The burst length in full page mode is 256. Bank Select and Precharge Address Allocation a [se [= rowases [98 = Trowassess a [xs [= TRowessess [os | = [Roweasess A [® Fo fretecttesisecarg ———[ersoemtncnne | Row address (active command) | "1_[ Precharge of both banks (precharge command) [0 [Banko ssesed orecharge and ecive commands [> fen es peep gene som] I [|= [ecumassess Lye [= [esa eases [We [= [esumnestess SSS [We [fest adaress [we [= [counsassess [xr [= [eeunnasses lO [1 _ | Auto-precharge performed | [0 [Sark oss (eas nsweioconmanas) No. 5055-2/55

The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data corresponding to this address is output in synchronization with the clock signal after the CAS latency period. Next, data corresponding to an address generated automatically by the device is output in synchronization with the clock signal. ‘The output buffers go to the low impedance state CAS latency minus one cycles after the read command, and go to the high impedance state automatically after the last data is output. However, the case where the burst length is a full page is an exception. In this case the output buffers must be set to the high impedance state by executing a burst stop command. Note that the upper byte and lower byte output data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tam) is fixed at two, regardless of the CAS latency setting, when this function is used. The selected bank must be set to the active state before executing this command. CAS latency = 2, burst length = 4 a _ : Burst length CAS latency Se A03623 Burst Write The write cycle is started by executing the write command. The address provided during write command execution is used as the starting address, and at the same time data for this address is input in synchronization with the clock signal. Next, data is input in order in synchronization with the clock signal. During this operation, data is written to addresses generated automatically by the device. This cycle terminates automatically after a number of clock cycles determined by the stipulated burst length. However, the case where the burst length is a full page is an exception. In this case the write cycle must be terminated by executing a burst stop command. The latency for DQ pin data input is zero, regardless of the CAS latency setting. However, a wait period (write recovery: tppz) after the last data input is required for the device to complete the write operation. Note that the upper byte and lower byte input data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tpyp) is fixed at zero, regardless of the CAS latency setting, when this function is used, The selected bank must be set to the active state before executing this command. CAS latency = 1 or 2, burst length = 4 «PLE LE LP Lelie ei i Burst length SS in, 03624 anne No. 5055-22/55

Read & Auto-Precharge The read & auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation. During this operation, the delay period (tpg) between the last burst data output and the start of the precharge operation differs depending on the CAS Jatency setting. When the CAS latency setting is one, the precharge operation starts at the same time as the last burst data is output (tear = 0), and when the CAS latency setting is two, the precharge operation starts on the clock cycle one cycle before the last burst data is output (ea. =-1). Therefore, the selected bank can be made active after a delay of tgp from the start position of this precharge operation. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. TAS latency = 1, burst length = 4 Read & auto-precharge (bank 0) Precharge start te __,! TAS latency = 2, burst length = 4 i Pou . a tae Read & auto-precharge (bank 0) Precharge start OO A03625 eee No, 5055-23/55

——_ SSS Write & Auto-Precharge The write & auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation. During this operation, the delay period (p41) between the last burst data input and the completion of the precharge operation is tap plus one CLK period. That is, the precharge operation starts one clock period after the last burst data input. Therefore, the selected bank can be made active after a delay of tpay. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. CAS latency = 1, burst length = 4 { . H i Precharge start Write & auto-precharge (bank 0) i fox. CAS latency = 2, burst length = 4 i Precharge start 7 i tae Write & auto-precharge (bank 0) H H toat A03626 SSSSSSSSSSSSSSSSsssSseSeEee No. 5055-24/55

ee SSSSSSeSSeSSSSSSSSSSSSSSSSSSsssSSSeeeSSSSSSSSSSSMMMeee Spacing between Read Commands A new read command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command. The interval between two read commands (t¢cp) must be at least one clock cycle. The selected bank must be set to the active state before executing this command. TAS tatency = 2, burst length = 4 ‘con Read (CA = a, bank 0) Read (CA =b, bank 0) 403627 Spacing between Write Commands A new write command can be executed while a write cycle is in progress, i.e., before that cycle completes. At the point the second write command is executed, data corresponding to the new write command can be input in place of the data for the previous write command. The interval between two write commands {tcep) must be at least one clock cycle. ‘The selected bank must be set to the active state before executing this command. CES latency = 2, burst length = 4 ko Write (CA =a, bank 0) Write (CA = b, bank 0) A03628 eee No. 5055-25/55

ee SSSSSSSSSSSSSeSSSSSSSSSSSSSsSSssssSsSSSSSSSSSSSSSSSSMMSSE Spacing between Write and Read Commands A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read command was executed. The DQn pins must be placed in the high impedance state at least one clock cycle before data is output during this operation. The interval (tg¢p) between commands must be at least 1 clock cycle. The selected bank must be set to the active state before executing this command. TAS latency = 1, burst length = 4 ‘eco | High-Z Write (CA = a, bank 0) Read (CA = b, bank 0) CAS latency = 2, burst length = 4 « FELL ELE i toon Write (CA =a, bank0) Read (CA = b, bank 0) A03629 eee No. 5055-26/55

Spacing between Read and Write Commands A read command can be interrupted and a new write command executed while the read cycle is in progress, i.e., before that cycle completes. Data corresponding to the new write command can be input at the point the new write command is executed. To prevent collision between input and output data at the DQn pins during this operation, the output data must be masked using the U/LDQM pins. The interval (tcp) between these commands must be at least 1 clock cycle. The selected bank must be set to the active state before executing this command. TAS latency = 1 of 2, burst length = 4 « TLL teen U/LDQM High-Z Qn Din b2 Din b3 Read (CA = a, bank 0) Write (CA = b, bank 0) TAS latency = 1, burst length « 4 i __ ‘cep U/LOQM Read (CA = a, bank 0) Write (CA = b, bank 0) 403630 No. 5055-27/55

eSSSSSSSSSSSSSSSSSeeeeeSeSSSSSSSeeeSSSSSSSSSSS Precharge The precharge command sets the bank selected by pin A9 to the precharged state. This command can be executed at a time (gas following the execution of an active command applied to the same bank. The selected bank goes to the idle state at time tgp following the execution of the precharge command, and an active command can be executed again for that bank. If pin A8 is low when this command is executed, the bank selected by pin A9 will be precharged, and if pin A8 is high, both banks will be precharged at the same time. The input to pin A9 is ignored in the latter case. Read Cycle Interruption Using the Precharge Command A read cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (trai) from the execution of the precharge command to the completion of the burst output, ie., the point the outputs go to the high impedance state will be one clock cycle if the CAS latency is one, and two clock cycles if the CAS latency is two. Inversely, to output burst data through the completion of the burst cycle, the precharge command must be executed either at the same time as or later than the last burst data output if the CAS latency is one, or no more than one clock cycle before the last output if the CAS latency is two. CAS latency = 1, burst length = 4 CLK i trot i — \\ = High-2 Read (CA = a, bank 0} Precharge (bank 0) CAS tatency = 2, burst length = 4 trot (wee X > Command READ aQ i : - High-Z Read (CA = a. bank 0) Precharge (bank 0) 403631 Sess No. 5055-28/55

a eeeSSSsSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSSSSSSSSssSSSeee Write Cycle Interruption Using the Precharge Command A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (wp) from the execution of the precharge command to the point where burst input is invalid, i.e., the point where input data is no longer written to device internal memory, is zero clock cycles, regardless of the CAS latency. Inversely, to write all the burst data to the device, the precharge command must be executed after the write data recovery period (tppy) has elapsed. Therefore, the precharge command must be executed on a clock cycle that follows the input of the last burst data item. CRS latency = 1 or 2, burst length = 4 clk i invalid data Write (CA = a, bank 0) Precharge (bank 0) TRS latency = 2, burst length = 4 e PLE LLLP i for, Write (CA = a. bank 0) Precharge (bank 0) A03632 eee No. 5055-29/55

1.C382161T-17 oo SSSSSSSSSSSSSSSSSSSSSsSSSSsSMSFSF Read Cycle (full page) Interruption Using the Burst Stop Command The LC382161 can output data continuously from the burst start address (a) to location a + 255 during a read cycle in which the burst length is set to full page. The LC382161 repeats the operation starting with the 256th cycle, with the data output returning to location (a) and continuing with a + 1, a +2, a + 3, etc. A burst stop command must be executed to terminate this cycle. A precharge command must be executed within the RAS cycle time (tpg max) following the burst stop command. After the period (tggp) required for burst data output to stop following the execution of the burst stop command has elapsed, the outputs go to the high impedance state. This period (tapp) is one clock cycle when the CAS latency is one and two clock cycles when the CAS latency is two. TAS latency = 1, burst length = full page CLK i tao - E High-z Read (CA = a, bank 0) Burst stop TAS latency = 2, burst length = full page cLK | f tago re! i . P High-z Read (CA = a, bank 0) Burst stop : 03633 No. 5055-30/55

Write Cycle (full page) Interruption Using the Burst Stop Command The LC38216] can input data continuously from the burst start address (a) to location a + 255 during a write cycle in which the burst length is set to full page. The LC382161 repeats the operation starting with the 256th cycle, with data input returning to location (a) and continuing with a + 1, a + 2, a + 3, etc. A burst stop command must be executed to terminate this cycle. A precharge command must be executed within the RAS cycle time (tgs max) following the burst stop command. After the period (twgp) required for burst data input to stop following the execution of the burst stop command has elapsed, the write cycle terminates. This period (lwp) is zero clock cycles, regardless of the CAS latency. TAS latency = 1 oF 2, burst length = full page CLK : = tne Invalid data: Write (CA = a, bank 0} Burst stop Precharge (bank 0) A03634 Burst Data Interruption Using the U/LDQM Pins (read cycle) Burst data output can be temporarily interrupted (masked) during a read cycle using the U/LDQM pins. Regardless of the CAS latency, two clock cycles (tgp) after one of the U/LDQM pins goes high, the corresponding outputs go to the high impedance state. Subsequently, the outputs are maintained in the high impedance state as long as that U/LDQM pin remains high. When the U/LDQM pin goes low, output is resumed at a time lamp later. This output control operates independently on a byte basis with the UDQM pin controlling upper byte output (pins DQ8 to DQ15) and the LDQM pin controlling lower byte output (pins DQO to DQ7). Since the U/LDQM pins control the device output buffers only, the read cycle continues internally and, in particular, incrementing of the internal burst counter continues. TAS latency = 2, burst length = 4 CLK i lone i U0QM / N Loam : Das to Das © High-Z High-Z . Dout ad Doutal High-Z Read Datamask Data mask (CA =a, bank 0) (upper byte) (lower bye) ‘03635 eee No, 5055-31/55

——- SSS Burst Data Interruption Using the U/LDQM Pins (write cycle) Burst data input can be temporarily interrupted (muted) during a write cycle using the U/LDQM pins. Regardless of the CAS latency, as soon as one of the U/LDQM pins goes high, the corresponding externally applied input data will no longer be written to the device internal circuits. Subsequently, the corresponding input continues to be muted as long as that U/LDQM pin remains high. The LC382161 will revert to accepting input as soon as that pin is dropped to low and data will be written to the device. This input control operates independently on a byte basis with the UDQM pin controlling upper byte intput (pins DQ8 to DQ15) and the LDQM pin controlling the lower byte input (pins DQO to DQ7). Since the U/LDQM pins control the device input buffers only, the write cycle continues internally and, in particular, incrementing of the internal burst counter continues. TAS latency « 2, burst length = 4 vom i i i : i : tomo : i wom : : ! : Din at [Din a2 Write Data mask . Data mask {CA =a, bank 0) (upper byte) (lower byte) 403636 Burst Read & Single Write ‘The burst read & single write command is set up using the mode register set command. During this operation, the burst read cycle operates normally but the write cycle only writes a single data item for each write cycle. The CAS latency and DQM latency are the same as in normal mode. TAB latency = 1 or 2 Write (CA = a, bank 0) 403637 eee No. $055:32/55

a SSSSSSSSSSSSSSSSSSSSSSSSSSSSSsssSSSSsSSSSSSSSSSSSSSSSSSSseeee Bank Active Command Spacing When the selected bank is precharged, the period tgp has elapsed and the bank has entered the idle state, the bank can be activated by executing the active command. If the other bank is in the idle state at that time, the active command can be executed for that bank after the period trap has elapsed. At that point both banks will be in the active state. When a bank active command has been executed, a precharge command must be executed for that bank within the RAS cycle time (tas max)- Also note that a precharge command cannot be executed for an active bank before tras min has elapsed. After a bank active command has been executed and the tcp period has elapsed, read and write (including auto- precharge) commands can be executed for that bank. CAS latency = 2 i taro ——— Bank active (bank 0) Bank active (vank 1) TAS latency = 2 ax | taco > A Bank active (bank 0) Read (bank 0) 03638 Clock Suspend When the CKE pin is dropped from high to low during a read or write cycle, the LC382161T enters clock suspend mode on the next CLK rising edge. This command reduces the device power dissipation by stopping the device internal clock. Clock suspend mode continues as long as the CKE pin remains low. In this state, all inputs other than the CKE pin are invalid and no other commands can be executed. Also, the device internal states are maintained. When the CKE pin goes from low to high, clock suspend mode is terminated on the next CLK rising edge and device operation resumes. The next command cannot be executed until the recovery period (tcx,) has elapsed. Since this command differs from the self-refresh command described previously in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tape). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time. TAS latency = 2, burst length = 4 CKE : \\ oo: J: : eee Read (bank 0) Clock suspend 403639 sss No. 5055-33/55

Power-On | Sequence, Mode Register Set Cycle CAS ateney oN a ‘e . vse vn ue vss ve cke a 4 — cs ill ms /M Hii] WA A WZ an om, Wil aRS an =n | ATTA. DYED. TIN a a cas mm LTT. TTL. mf mg we Tom |_ VEE WT} HN a AO-AB mama LEA OEE PELLET Se om Se a7 mm (22D OTTO _ Sommer a8 CT = Tk eos. OT TETLEK == NTT, PT TLL 9 [EDITTNIDUETETTTTETITELECTOTTTTCTEL POETIC OOOO TOPE 20= NOE _—_ NCATE TOLL Dam gum TTT on me mn ve / pot Power-Down Mode Cycle TAS latency = 1 cx 1. fo. faked ee ned AF coke mae { oy a | cs unt to bal enon | em Wh RAS TTS UA aE TAS a, WE cc cH AO-AB cc cn cc fmm emote a7 CE ee HI a8 oor Cpe mae om WE mn as [UMM NTT rom me LALLA RN EM Dom ae as hae ne neem 1 > To eee Power Oonn wode Soin kode” | teas Sener, <P> a pon Tt care — XY INVALIO CATA sane No. 5055-34/55

TAS latency = 1 CLK texs tex tens! ten} cke 1 er | ts ma fh_|_ 7 (nar oS mm. (mo ca} ec ro th. a we snort Er Wii \\ ono, | _ or oo LMJD$s$Miiii i <i; ac; eT —<MhLM ML L a8 TEE (+2 SO OO =< CO C= NO tas] tan BANK 4 = TT TT TO OX bom spun {CT A OT TT Tere6T2 an ST von tT cane = YX INVaLIO DATA

CAS latency = 1, burst length = 4 cLK a ewe] OT EY ET s lim wm | im | mmm in \\ |_| | as TMM | in || | besked ee ee Po) COOL YT iii | |X we nme m = WwW A0-A6 mmm =p ET NCS ar ne ae ae a a8 om _qmmmdmmmmmnn Se =e 49 ee Mi aT | Ee CK CT YD bam a a 99 emo l — <ACT> cc oe Read Cycle/Auto-Precharge TRS latency = 1, burst length = 4 CLK = [wm a | YC Wanh_|_ ans a en fm oS comm ha, a Wil We LL a Ty Wl TTT TS TEE =A . Ti nnn as n= meee As om mm mer pc 90 ei Sie Sata at act <READAD ene Don't care = XY INVALID DATA Ro, 5055-3655

TAS latency = 1, burst length = full page cLK ware ft PHY cke a = | @ Lm ow) ow | i /w; a n A _ a WE {ea TET fh_| A0-A6 sunt hee erm ee ee a 2ITIwWMMMIwI Kira wii TE ae mmm ctl, J ag hs an _ TTT (TN TD va 1 i Sd Read Cycle/Ping-Pong Operation (bank switching) a GAS latency = 1, burst length = 4 cLK wpe, PP PE ET EEE EYE cxe | om | a | aaS ee ee mbm | mm imma he oom naam v can a Winn} ik} ao-ae [IMMA YKeeom\\ IK 25 NT MMM TN > N2= XTT a SMM IS OATES OS TH

28 Oi ea ee nee Seay | “== MTT

as A ne Wl eee eons «MMU TTL CID XY hmmm ee ns MD enon oom mmm} || cc o eg fi ek paren oie <act o> SPEAB,03, cacr > a SREAD SZ, cpm o> <act o> con't CARE = BX INVALID DATA... No, 5055-37/55

CAS latency = 1, burst length = 4 i) " t2 13 4 15 16 "7 _ aa tt cs mdm oom} | CTT +L. RRS sl ATT__|_ tii tas mm a or al Wii | Wil WE moo _|_ sg iii | in 50a [IIIT TINITIN 2 XOTTITIX = = LT NOL a7 OT ee a e a a ag So comme SH °S TTT TTT TTT! Ta ER 1/1 /, CEMSEN 1/11, CE 1) eT TO RAS te Aas Write Cycle/Auto-Precharge _ TAS latency = 1, burst length = 4 10 1 te 13 te 15 te "7 es Ns es i : somo. | s/n war enum - Ras LTT nr} wnnfeneioon in eee np | WE ad ee a Wl AO-AG CEE ETE = CET EE 2 AT ne a a ca AB mun oe as TATTLE NEAL XTC OCT X i. com = TTT TET T=, men mmm 20 mmm = Sm t= me pe ee _— Don't cane = AXYY) INVALID DATA sous

a Write Cycle/Full Page CAS latency = 1, burst length = full page CLK jase! | OT es il ees ees CKE « wel lwtetetti. tt 1,| oe ee ee aS Ce | Win nnn |_| om mm smn ome eT MM WH WE como Mh_\\ Mm | a ee o~ a6 [MIMI ** YK ===) MANN LE es re a rs re ee

7 Ii“

AB mmm, = _ it nm mmm cme | as mmm ho of = TA TL A N+» (TD Dom mmm [| —_ Fmt Do momo Sik Se = Some Write Cycle/Ping-Pong Operation (bank switching) TAS latency = 1, burst length = 4 cuk weet! ea lalertetal al alee s MT BlLoa!l mio Ba Wa_| Ja | mn | | | WL on Tm a TLL | __(eaeou) a ee ee tS Com] M0 LD MN em we oma “cee Cm. I} o~ae [MMIII °° YOLK *9% TI ELLIE OK ==> NTT a7 ee ee ae a a a8 mmm ee = FF AC ag rmmmpmmi io oon he ooo MT TL bom ee oa mmo =e es ok Sines = Ue oe = MMM No. 5055-39/55

TAS latency = 1, burst length = 4 cLK ee rs i De Or le es ls lo CKE | mn | Lo = Wm | W_|_Mh -_ we -wt w ww — Ph aS anol ETE Metlaesae ah ih ams cae —Mii hs ae VT ¥ el ee ‘hmmm Re AT Ao-as == == a7 nog 5m s0 mmm =n |_mommnn monnemmn as momma = minal oom ee TLIO ae rat | Leet ent cent Ect Lt Read Cycle/Page Mode; Data Masking CAS latency = 1, burst length = 4 cL Reslten, AAS | Wa wee. fm om mom | mammal \\_ amma Wi We cm | mT na mu sso ZT YO == TTT LOL LE OT TT “7 CE a a I ae mm | cm mmc Aa mmm pom | ke touo ‘BANK Oo oom om a en Tm bo — fu Se cn gg a Don tT cane = AAR INVALIO DATA i 5055-40155

CAS latency = 1, burstiength = 4 * un mcm gman i “ en am “ mmf | mbm (imi, me es a so ae ITN 20% OTK XI TO TTT == TO “7 Fe a ae a 28 ee ee 49 mmo emf mom KY bo momoommmton o k k S ds a ~ — Write Cycle/Page Mode; Data Masking “ CAS latency = 1, burst length = 4 = ate letelwlalatelela| AAS Cnt | wn HH “ m-mec ue We C, A cE {a MT sso ae ZINN 0% ODA TL TT TT TET == TT OO “7 room mm rm == se a a cee 29 mmm mmm oox cm or | aw __ luau

06 C= Se ON = =

gon’ T cARE = XXX) INVALIO DATA TT, 5055-41155

CAS latency = 1, burst length = 4 oxe ZT] aoe | fealten, = | easing AA _ |e ee ee ee es OO, Fh, _ A | 2 iin | wn ccc ccc | vo TI == T= © ERX a8 a *9 mi em a oou a 90 |g gg Ei Write Cycle/Clock Suspend AS latency = 1, burst length = 4 “ [eee Pe one TM_| sen whl my EAI as Mmmm _|_ iy mmo | | so cms mmm yo._|_ mm mm mr} a A i Lh mb mmm, | oe = in | bio coro | co} a i <<oniin A a SwU_E_ rg

3 Tse uk VO OT EO OO

_WMWwWOTTvwttvUTVvPE TTT oon JOEL {| A TAL ox mmm kt od mc [ee ne Don T care = BX INVALID DATA No. 5055-42/55

Read Cycle/Precharge Termination EAS fatency = 1, burst length = 4 CLK cs Wi |W. an Wy) wy . | ml a | A [a | a Wl Aas Tel | SC HLUEELLITLTTETLEN _olo@ WL cas Cc | iii oo 7 om we mou a A0-A6 rom ea Tn =e 7 [ENTE 5 = XT TL = YC As aa os [co om mom [as Dae. MMT ese TTT

9 QUT 20 Toon TTT ET KO TT

cow TA | [TE i - co fy tl i | teas [tae | tras wR tae _ —_ Write Cycle/Precharge Termination CAS latency = 1, burst length = 4 cLK werjumtedey SP OP A SEP See Le etwpel al alee Fealien Ss Mi) Oma) ow Om mm | am | | Wa_|_ ARS Te at” | WL _m] Ln _| HS TD Minn wT Va_|_ | We mmm oye nlm | (mL AO-As Coe a a a7 [NCTA == OL m= ae mmm, _omma, | = re (gc oS, <_- lll [ t {| i BANK 4 BANK | BANK 4. Ag TMT oan (I IN vane onde ogn mommy —— | le rf fm. oo TATETTTTTOTTTATN +—o= Nes =< or= 2 ATL TILL oe» Ueno orn on \\ZHoen 5 ATT ' ee Se DON'T CARE = XX INVALID DATA No. 5055-43/55

CAS latency = 1, burst length = 4 Satter ale petwtal Ras ll Ti ec WE pon le Ail. AO-AG rane Cm hes § TET OE OE AT mmm = ee AB CT ee ha (till as CTE a me oe 1) uoeM mmm | Lar a coom = 7 Sar an wr | Fg lm ag eel) | Write Cycle/Byte Operation TAS latency = 1, burst length = 4 © Be lepetw tale wt ete RAS a el Ai CAS mm | LTE ETT ee on ell Wil We oe ee |__| il AO-A6B TR TEE XT a7 Me se XT TTT CEE TET = ec AB mh ag Comm aco upom mmm, WA. aon | Mimnniiiil Paes tes) Mala aly a oas— + SMI +" = XK oud == OAT => = NK o> - YUKO a = ee Da0-7 ee ec > (fs a sen, _t tn tae Don T caRE = RXR INVALIO OATA No 5055-4455

Read Cycle, Write Cycle/Burst Read, Single Write, CAS latency = 1, burst length = 4 cLK oe on | guar nla cs um Mh oar) | WwW rw] |W. aS mr Winn a, | oe aS TE | Ya In| a we wt - MTT wu Cm nono | __ ssa as a 0~ae [TITITIIINA #2" MOK =) TTI LLL ALL LO == VO az ee ee mmm 48 r= MWwIw(w[_t({((0t ti 0 i ae a CT as Somme Sammons hon rm bom moms ee | heel comm oe ae Ce ep | Sp | pont cane GRY rvarto oata No. 5055-45/55

Read oe ene = 2, burst length = 4 ~ Te aa pape cxe QM Tce _| oR late tele ete ate AS i i A a aS | nnn ane il Rana we ee i re lc A0-A5 EO == A a7 zp tp Aa m= | = apne ag remy yn bam momen os || tp Read Cycle/Auto-Precharge ™ CAS latency = 2, burst length = 4 2 py cxe | soa _| > Sfeletelotetetetee le ARS na a a cKS | YE nnn a io ae WE cl cs AO-As TT R= === TE EE = = a7 smd mt mp ae om = nT => as ro cc oom ee Peas, tear taco | pon tT cane = SX INVALID DATA sone TN, 5055-46155

TAS latency = 2, burst fength = full page. CLK { “ a ae [Ecs| ws ma) Wa ah. or) | | UW kK nm a | Wl ss IMM | oo Th ATL | _Kealtea| re ; | TAS HE | A Mi Winn. ve mm = | ahem | HIN | mmm AO-AB room ook mm = TEE rr or a a 7 io = eT as a a a commen, | oat ne he ao [MIMITTTTe«+ » TITTLE »« METTLE LTO Of pam comme | *peermemrinete oo Ty PLN omen SIRI omton | A oemen= NC ooston LE eoron YR) taco Sexe Te | aE OA Read Cycle/Ping-Pong Operation (bank switching) CAS latency = 2, burst length = 4 cLK eo mPPa Loomer) al oh cs MT hlLoT,TOo_hA! mo Mm!) oD | mm oS EE, TOE DM ninins_| ion ion We |, || Wn an ees ee WaA_|_ ml no~ a6 [IIMA °° YUMIKO 2 = a7 ee ee ag a= cals | a “su ma, lm ag mom ms woman me o fTATINTT +» TTT T pom romain {adem | Femme <act o> SREB, cae > BERD S2, cone o> <act o> <PRei> GZ oon t came AYR INVALIO DATA, yece No. 5055-47/S5

CAS latency = 2, burst length = 4 CLK aco Laan | a = MF) Mim) wo 7 Bans | am | Who} an ams EDO comme | mm ram tas i | meme | Fm ca mo mmm sr AO-AB som STN a7 DR ae CT As m= co eee a3 a a ee a ee ee bam mmm TE _ i ae i LA eS RR) MS OR taco i [_toeu_| Saco! Re tg Write Cycle/Auto-Precharge CAS latency < 2, burst length = 4 cLK ‘ wl hetel HE Sy ED ES | aw ww te or) Ss MM, Dim) Mm) wo [www Nn mT axs § T_\\ cnn emma amen __ on a a es iii nnn} ccc a es ™ ee <= cc ccc ccc aT WL Ao-A6 rm c= TT a7 rm ret =X TTT As mmo m= TET | teal a a | ss Tn XK XL oom — TMT LE Sehiccmememnnemn 08 rm unk 2 Sok kok ST oon T CARE = BXYY INVALID DATA

CAS latency = 2, burst Jength = full page cLK cut as mi} ta Loma are} WW pw] Mh a wa axe — ZT ‘a i ams CTE ea LETT Ce | WE ryt i A iN TLC mc iin |__| ccc AO-AG sm cosmo (LCT

7 TE TT Ee = TO

se mt, = i JTL TL ro = la a as mmm mmm. » sae «TTT TTT TT TTA oo mmm tN kL Write Cycle/Ping-Pong Operation (bank switching) TAS latency = 2, burst length = 4 2 tele ewtelal ete. cs] = MT) DO), OB) Al ow) el mo a fm ARS Tae | a | smi, | _ cas Lc a Lm [a ) le Wi _ me mm. | | ml : We CO la Mh nl Wi Ao-A6 smn m=O TT TOM OT as como omy | amy _ sms ao (TIT mmm ar aM A 20 zor et SSeS Se Se Sm <HRIT 0> er pon tT cane XX) INVALID OATA,... Ng 5055-4955

TAS latency = 2, burst length = 2 es TM Wh__ Wh | seston, i i \\ i j . iii iin iii “ni oo... _ ooo “ Tim iii | iii o_o oon +o j seston) \\ : ! \\ i i ! = Tl Tag | +" __ ATL o~ae TITIAN #2 YT OILY == XT TENN == YELLIN === YL ET H i | saslen i i i |

7 ILD ETE == TT == XT TO == LL

Sasitan, H i i aur eae pane! 2 1 ! Vas TT a TT MMe Som a C—O CT oom NUTT ro, _ i TTD oa licen Since pre ee ge ae : ate teas TE tee FO Fea te Aon on SZ Read Cycle/Page Mode; Data Masking CHS latency = 2, burst length = 2 CLK es As es ls io ee CKE [tena _| cs wl [ ri | @ or or Mi ae (i a ARS cnt TV oS TY — i i _ rr cc mm | we Fw ee

6 T= TT A TTT

bom en 7 (I Biren aio de CA AEE SERRE} CRO pg 1 CR CD DON’ T CARE INVALID DATA

CAS latency = 2, burst length = 2 oe etebef HY EY EET texs, “ |e on or Fes] ts ty Wo or) “Uh | or) Wh or) “D | Wil ARS | Td | iin nn} TAS a /TTTED_|__AEEETTVTETTT. a We mma whom | mem e_ Laren CE A0-A6 smh p= C= 5 a7 a a Ae mun ie ee ag 2 rmommbmmms | | oom ATMO LLL oe TINT ITOETMTN2*= YOK = XO 2» OKorm == IC 0m» Wom == OO Write Cycle/Page Mode; Data Masking TAS latency = 2, burst length = 2 CLK Le hotel YOU HY “ ce real v ts | Wh or) XO or) ar | Oh Oh J Wan ARS Teh | Wm a | a a TAS mm vim. |_ om Imi | ono | kes WE mo ~ geet | iam |_ ca Aono. A0-A6 TE ERE TE == == == ae ar mmr =m == x 28 mm =m Cee JED mom OT ag mnt =u, a bow cL mr y Wh a [| |__sos[ tony ostomy cosh fon, fOSLtoK, bo TE = = OK = XT =k OTT * wa Gunit> ewase> opetTE gene (77 con't cane = ARMY rNvAL10 DATA No. 5055-51/55

cs mt tl | ce el oe a mm | (TL ass TA _|__ oe Uninet LTTE (Till CaS = ee ta Wil A0-A6 Y= == OT TO TIX #0" YUL

7 To TK

ag CE EXE, EE EE TE T= OT) cose TEETTTTETTITOTETETTTEOTETOOE T= |_—_—_—— =" TTOETETO OLOT O oa ee eee Write Cycle/Clock Suspend TAS latency = 2, burst length = 2 cs aoa Lore eter am VA i) Wl RAS ae | a a cri ian a ne CaS a Sa, apenas -as WE ie Oe a i | nn A0-AB an a A a i i

47 EEA TTT == = XT

oom mmm | |_| mnt oa CA T= = taas tap tans —— pon T cane = BX) INVALID DATA sue

Read Cycle/Precharge Termination ae pete iin ln ee ee ee 2 ele eerie _ ate | a me CAS een es | | ii. cd amano |_ sus Wm 40-Aa6 TTX 2 XU 2" =X TDK 22 XK = TTT a7 ee eS an AB mt, |_scm=eme Ag TET es mpm emu mmm bow mem mmo} "oe Write Cycle/Precharge Termination . TAS latency = 2, burst length = 2 CLK

2 BR jete lee felete la fee

_ soni spor wats | aah anh i * cmb tomo [mmm many am | -_ ene ca se 40-48 TTT _#°* XU =) a th a7 ee ee a a a a ag mmm | tm," ag mmm HOTA = nr oh «Sem oom re ee a Te ce mmm mun mnt un oxy cane GRR) rnvaLzo cata No, 5055-53155

TAS latency = 2, burst length = 4 cs mm |‘ io; a a ams Co | CO whom. oom | oto eS mm | mom 3 HH) ~~ we mmm |_| soa ZR == TN == TT TO a7 TT cS a ae TET, YO OTE OO as pmo nr Oc upem mom | om Loom UNM | } eS ea bas-15 enue = Dace lene = Sy Se <ACT> : REARS. <MASKU> <ENBU.MASKL> <MASKL> a err — Write Cycle/Byte Operation AS latency = 2, burst length = 4 - Ltobel DY WO a a teks a ee KS C—O ummm, mm. ee ras cmp m_anmm woo +o = oo, |, __ CO cw AO-A6 mg YO TTT a7 Tr Me LE aa A Po ea as MK NOK XK — YO voom mmm Dh__ nnn Loom TMM | | | Ao ooo ooe- + s {MMT TL» XO) ead = Te = TTT Dao~7 pm pr pp Saco [EDP facp 0 ac SREIR, cwasei> —cwaser— <eNO>— SERE aoe = QZ oon t care = XY INVALID DATA No, 5055-54/55

Read Cycle, Write Cycle/Burst Read, Single Write CAS latency = 2, burst length = 4 cok woreda] PP TP Ee cke | tes | oa pe OO | Wal | i mmm ton | am aKS | FO I be (um ras CR LL i im. cd mm = von a fm A0-A6 C= == a7 EEE === = as T= TE cc ET ha) ag TI TL A Lote ral vw |_| bom mmm ono oo = pate = = Ut SS Te DON T CARE INVALID DATA No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. 'B Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTO., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or sé lly. 7 tnformation tincuding circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1997. Specifications and information herein are subject to change without notice eee No. 5055-55/55