LC378000RP SANYO | Alldatasheet

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Technical content

Features

  • Supply voltage range: 2.6 to 5.5 V
  • Access time (t AA ): 100 ns (VCC = 4.5 to 5.5 V) (tCA ): 110 ns (VCC = 4.5 to 5.5 V) 200 ns (VCC = 2.6 to 5.5 V)
  • Switchable between 8-bit and 16-bit data path widths Byte mode: 1,048,576 words · 8 bits Word mode: 524,288 words · 16 bits
  • Operating current drain: 90 mA (maximum)
  • Standby current: 30 µA (maximum)
  • Fully static operation (internal synchronization)
  • Three-state outputs
  • Package: 42-pin DIP (600 mil) plastic package Package Dimensions unit: mm 3014A-DIP42 CMOS IC 42098RM (OT) No. 5793-1/4 Preliminary SANYO: DIP42 [LC378000RP] SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN Internally Synchronized Silicon Gate 8M (1,048,576- word · 8-bit, 524,288-word · 16-bit) Mask ROM LC378000RP Ordering number : EN*5793

No. 5793-2/4 LC378000RP Block Diagram Pin Functions D15/A-1:In byte mode, this pin functions as the A-1 address input, and in word mode, it functions as the D15 data output pin. A0 to A19 Address inputs D0 to D15/A-1 Data outputs CE Chip enable input OE Output enable input BYTE Byte/word mode switching V CC Power VSS Ground Function Logic Table Note: X: A high-level or low-level input D8 to 14 are high impedance and D15 functions as the A-1 address input. CE OE BYTE Output pin state Current drain H X L High impedance Standby mode level L H L High impedance Operating mode level L L L DOUT · 8 (BYTE MODE) * Operating mode level H X H High impedance Standby mode level L H H High impedance Operating mode level L L H DOUT · 16 (WORD MODE) Operating mode level Address buffer Row decoder Memory array Column decoder + bias circuit Sense amplifier Byte/word output switching circuit Output buffer A-1 buffer CE buffer BYTE buffer OE buffer Internal timing generator

No. 5793-3/4 LC378000RP Parameter Symbol Conditions Ratings Unit Supply voltage VCC –0.3 to +7.0 V Input pin voltage VIN –0.3* to VCC + 0.3 V Output pin voltage VOUT –0.3 to VCC + 0.3 V Allowable power dissipation Pd max Ta = 25°C 1.0 W Operating temperature Topr –10 to +70 °C Storage temperature Tstg –55 to +125 °C Note: Application of stresses greater than or equal to the maximum ratings may lead to device destruction. *: Minimum value minus 3.0 V for pulses with widths of 30 ns or less. Note: These parameters are not tested in all units, but rather are sampled in a subset of units produced. Note: Values in parentheses are guaranteed at Ta = 25°C. Note: tOD is stipulated as the time from the rise of either CE or OE (whichever occurs first) to the point when the output goes to the high-impedance state. These parameters are not tested in all units, but rather are sampled in a subset of units produced. Values in parentheses are for V CC = 4.5 to 5.5 V. Specifications Absolute Maximum Ratings* Parameter Symbol Conditions Ratings Unit min typ max Input pin capacitance C IN VIN = 0 V. Reference value using the Sanyo DIP. 8 pF Output pin capacitance C OUT VOUT = 0 V. Reference value using the Sanyo DIP. 10 pF Capacitance Characteristics* at Ta = 25°C, f = 1.0 MHz Parameter Symbol Conditions Ratings Unit min typ max Supply voltage VCC max 2.6 5.0 5.5 V Input high-level voltage VIH 2.2 VCC + 0.3 V Input low-level voltage VIL –0.3 0.6 V DC Allowable Operating Ranges at Ta = –10 to +70°C Parameter Symbol Conditions Ratings Unit min typ max Operating current drain ICCA1 CE = 0.2 V, VI= VCC – 0.2 V/0.2 V 30 mA ICCA2 CE = VIL, IO = 0 mA, VI= VIH/VIL, f = 10 MHz 90 mA Standby current drain ICCS1 CE = VCC – 0.2 V 30 (1.0) µA ICCS2 CE = VIH 1.0 (0.3) mA Input leakage current ILI VIN = 0 to VCC ±1.0 µA Output leakage current ILO CE or OE = VIH, VOUT = 0 to VCC ±1.0 µA Output high-level voltage VOH IOH = –0.5 mA 0.8 VCC V Output low-level voltage VOL IOL = 0.5 mA 0.2 V Parameter Symbol Conditions Ratings Unit min typ max Cycle time tCYC 200 (100) ns Address access time tAA 200 (100) ns CE enable time tCEON 200 (135) ns CE access time tCA 200 (110) ns OE access time tOA 100 (40) ns Output hold time tOH 20 ns Output disable time* tOD 100 ns AC Characteristics at Ta = –10 to +70°C, VCC = 2.6 to 5.5 V

PS No. 5793-4/4 LC378000RP This catalog provides information as of April, 1998. Specifications and information herein are subject to change without notice. n No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n Anyone purchasing any products described or contained herein for an above-mentioned use shall: À Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: \` Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. Test Conditions Timing Waveforms Output Load Input voltage amplitude 0.4 V to 2.8 V Rise and fall times 5 ns Input discrimination level 1.5 V Output discrimination level 1.5 V Output load See figure. *: Includes the oscilloscope and jig capacitances. Note: Items in parentheses are for byte mode operation. Notes on System Design This IC adopts the ATD technique, in which operation starts when a change in either the CE or address inputs is detected. This means that the output data immediately after power is applied is invalid. When using this IC as program memory for the Z80 and similar microprocessors, applications must take into account the fact that valid data will not be output after power is first applied unless the value of either the CE line or at least one of the address lines is changed after the power supply has stabilized. Another point due to the use of the ATD technique is that this IC is sensitive to input noise. Do not apply voltages outside the allowable DC input levels for extended periods and do not apply input voltages with large noise components. Address input Data output tCEON