LC3664BL-10 SANYO | Alldatasheet

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Asynchronous Silicon Gate CMOS LS! | Nosx26 | LC3664BL, BML-70/85/10/12 ; | 64 K (8192 words x 8 bits) SRAM Overview Package Dimensions The LC3664BL, BML-70/85/10/12 are fully unit: mm asynchronous silicon gate CMOS static RAMs with an 3012A - DIP28 y 8192 words x 8 bits, This series has TE] and CE2 chip enable pins for device x 's selecnonselect control and an output enable pin for aValelelelalalolaWalalatata| output control, and features high speed as well as low IT power dissipation, , 33 For these reasons, the series is especially suited for use in systems requiring high speed, low power, and battery Sooo aoe oer er ey backup, and it is easy to expand memory capacity. = ms TS oo | Features TU a Festures AVOMUV TPIT 7Ons(max.) : LC3664BL-70, LC3664BML-70 oe tr ast SANYO: DIP28 85 ns(max.) : LC3664BL-85, LC3664BML-85 100 ns (max.) : LC3664BL-10, LC3664BML-10 120 ns (max.) : LC3664BL-12, LC3664BML-12 + Low current dissipation 3187 - SOP28D During standby O.5 pA(max.) /Ta = 25°C 35, 1pA(max.) /Ta=0to 40°C % 6pA(max.) /Ta=0to 70°C During data retention «| +] 0.2 yA (max.) /Ta = 25°C «| = 0.5 pA (max.) /Ta=0 to 40°C 3 2.5 1A (max.) (Ta =0 to 70°C = During operation (DC) ' u 10 mA (max.) = + Single 5 V power supply: 5 V 210% | + Data retention power supply voltage: 2.010 5.5 V asl td ; + No clock required (Fully static memory) SANTO SPEED + All inpuvoutput levels are TTL compatible + Common inpuvoutput pins, with three output states « Packages DIP 28-pin plastic package (600 mil) : LC3664BL SOP 28-pin plastic package (450 mil) : LC3664BML Terratios Grchading Cirrus dlagrams snd ¢uraii parwnauarn) Reowin 1 Toe G20 ob: em guaranteed fox votre prediction, © iephed raparting i wat oF hy salge rar of inetlecoal property rights cr evber Kgve of (bi partes t Specifications and iaformarion herea are subject lo change without netice. SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OF NICE Tokyo Bldgs. 1, LChome. Ueno. Tait TOKYO JAPAN DSOMN No, 4326.1/7

LC3664BL, BML-70/85/10/12 Pin Assignment Block Diagram TOP VIEW no Of [28] veo a GJ [) 0&2 “ 5 Ver a fy 5) “* a row cohen as G] [24] As Are eceter 128 «512 a OF) fa] An as © OND » GF fa} oe © TT a: (J [Zi} Are ae oo, a» & [zy Ey dw ts vo Oy [ta) (Or Ay WO ceeuit oe Be oo | | SS wos [73] (ia) VOs Ae r || ono [Te] fis) 0% “we nzaay “PTO te = phe io d b E20 L) VOr 1s AgtoAn : Address input WE + Read/write"control input OE + Output enable input CEI,CE2 =: Chip enable input VOr1 te YOs : Data input/output Vcc,GND : Powersupply pins Functions |__Mede [ces [cee | oe [we [wo Sumpiycurent | Readeyce | cf wf tT wf dateoupur cca [witecyee |e |» |x| 1] ano | eer |_Outputdisabie |e | Kf TH | Highimpedance [cca pw [x xT xT Hignimpedance tos Lx fe [ x [XT Highimpedance Tes | X:HorL Ne 4067

LC3664BL, BML-70/85/10/12 Specifications Absolute Maximum Ratings at Tae25°C | Maximum supply votage | Vocmex | TO | | Input pin vonage | vm Tf asttoveceos |v | | YOpinvotage | oT osttovecsos |v | Allowable power dissipation a |_tcosesame | or | ow [Storage temperaturerange | Tsig J] Tato vio [ec | * -3.0 V when pulse width is bess than 50 ns DC Allowable Operating Ranges at Ta = 0 to 70°C |____ Parameter | Symbot_ [min [ye max [unt | Power supply votage | veo | as | so | ss || [input H" level votage | vm | ae TT veo |v | [input t"tevelvonage | ve Tos [soe [| + ~3.0 V when pulse width is less than 50 ns [Parameter [Sb [ Conan «dT an | om [me | wt | [input ieakage current |i [Vaeowves «dT os | +t 8 | a | eames [Rance [| or WWE = Vi, Vwo = 0 to Veo | Outpt levelvotiage| Von | one =t.0ma | 2a TT | Ouiput*L"level vottage| vou [ia=2tma TT oe | Le} supply VEEISO.2V, .2V, Ving0.2V Smoker” [RY | Rieiaestoce || S| | il Eh Vins Vie or Vit Average operaing Va swveaye] [eel fe |] ounce Wor Oma mine mad aire] | 28 | 20 | ma “Estep Standby supply {Veezg0.2V) jowo7orct | oz | 6 | Current oF [VEErZVeC-0.2V, (Voe22Voo [0 to 40°C | | eof | os | [ccs | veers vecrv@ti=wavwsowovee | | o« | 2 | aa | * Reference values at Vec = $V, Ta = 25°C Nn avr

LC3664BL, BML-70/85/10/12 Input/Output Capacitance at Ta = 25°C, f= 1 MHz Note; These parameters were obtained through sampling, and not full-lot measurement. AC testing conditions Input pulse voltagelevel : O8V,22V Input rise and fall time : Sns Input - output timinglevel : I5V Output load : 1 TTL gate + CL = 100 pF (85 ns/100 ns/120 ns)

1 TTL gate + CL = 30 pF (70 ns)

(including scope and jig capacitance) Read Cycle ee a Aa Symbo LC3664BML-70 LC36648ML-85 LC3664BML-10 LC3664BML-12 |_min max [min Tmax [min Tmax | min] max | [Readcycietima [tac | 70 [as 00 20 Tn | [Address access time [taa__[ | 70 [es 00 20 | [CE1 access time ficar [70 as 00 920s | |CE2 access time [icaa [| 790 [as 00 20 ns | [OE accesstme [roa | | as fas co 60s | Outpthoid ime [ton | 20 [0 a a0 ns | Write Cycle ree nf a | CS | TREE, SER, [_] Symbos__LC3664BML-70 LC3664BML-85 LC3664BML-10 LC3664BML-12 |_min | max | min | max [min max | min Tmax | write cycietime [wo | 70 | | es [| 00 20 ns | [Address akiwendotmteluw | 60 | | eo ft 7s Pas as | |ce2setuptime _licwe | eo | | eo | {7s {as So 40 Ut

LC3664BL, BML-70/85/10/12 Timing Charts + Read Cycle (1): CE! = OE = Vit, CE2 = Vin, WE = Vin + Read Cycle (2): WE = Vin Astress CY a XXXSs = tZLZ/ cea LLL er| FANA ale = WAAL ALLL + Se * Write Cycle (1); WE Control Note (6) Adoven —_ 5 or rr]

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LC3664BL, BML-70/8510/12 * Write Cycle (2): TE! Control Note (6) haan > = | = WMAAMASSSAANY SEA 7 a « ZZZ SSS — dt Date out \\aZzy High weedance * Write Cycle (3): CE2 Control Note (6) a CAAA RSS m TASSA lop ey ee er cee LZ¥ YASS _AZTZ7 bade == den SOO a

LC3664BL, BML-70/85/10/12 ee Notes (1) tcops: tcop2: oop: 29d twop are defined as the time at which the outputs becomes the high impedance state and are not referred to output voltage levels, (2) An extemal antiphase signal must not be applied when DOUT is in the output state. (3) typ is the time interval that CE] and WE are low-level and CE2 is high-level, and is defined as the intervat from the falling of WE to the rising of CEI or WE, or the falling of CE2, whichever is earlier, (4) tow and tows are the time interval that CE] and WE are low-level and CE2 is high-level, and is defined a the time from the falling of CE1 or the rising of CE2 to the rising of CE1 or WE. or the falling of CE2, whichever is earlier. (5) DQUT goes to the high-impedance state when cither OE is high-level, CE] is high-level, CE2 is low-level, or WE is low-level. (6) When OE is high-level during the write cycle, DOUT goes to the high-impedance state. Data Retention Characteristics at Ta = 0 to 70°C | __Parameter_ [Symbol [Conditions min | tp | max | unit | emenveren| Now [Neva | || Cézs co-¥ 2x9 Data retention supply current Veo = 3.0¥ | oto7orc || [as | Vet 2Vec-0.2V, | oteaorc | | os | ua Veo = 3.0V, | ow7orc | | [2s | VoexS0.2V | owarc [| tos | pa Lac Tt foe | Chipenablehoidtime | ty S™—i ws | |S dC | * ipo = Read Cycle time Data Retention Waveform (1) (CE1 control) on Onis etgrtion mode w tw i fe Your ery fier eee f py / vee V1 @Ve0—0.2¥ Data Retention Waveform (2) (CE2 control) Owe Mierton mode Vee leon ALJ Veer eee Ne 40% UT