LC36256AL SANYO | Alldatasheet

Document overview

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Technical content

Features

  • Access time 70 ns (max.) : LC36256AL-70, LC36256AML-70 85 ns (max.) : LC36256AL-85, LC36256AML-85 100 ns (max.) : LC36256AL-10, LC36256AML-10 120 ns (max.) : LC36256AL-12, LC36256AML-12
  • Low current dissipation During standby 2 µA (max.) / Ta = 25°C 5 µA (max.) / Ta = 0 to +40°C 25 µA (max.) / Ta = 0 to +70°C During data retention 1 µA (max.) / Ta = 25°C 2 µA (max.) / Ta = 0 to +40°C 10 µA (max.) / Ta = 0 to +70°C During operation (DC) 10 mA (max.)
  • Single 5 V power supply: 5 V ±10%
  • Data retention power supply voltage: 2.0 to 5.5 V
  • No clock required (Fully static memory)
  • All input/output levels are TTL compatible
  • Common input/output pins, with three output states
  • Packages DIP 28 -pin (600 mil) plastic package : LC36256AL SOP 28-pin (450 mil) plastic package : LC36256AML Package Dimensions unit: mm 3012A - DIP28 unit : mm 3187 - SOP28D SANYO: DIP28 [LC36256AL] SANYO: SOP28D [LC36256AML] LC36256AL, AML-70/85/10/12 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN

256 K (32768 words · 8 bits) SRAM

Asynchronous Silicon Gate CMOS LSI

LC36256AL, AML-70/85/10/12 No. 4163-2/7 Pin Assignment Block Diagram Functions Mode CE OE WE I/O Supply current Read cycle L L H Data output ICCA Write cycle L X L Data input ICCA Output disable L H H High impedance ICCA Nonselect H X X High impedance ICCS X : H or L Pin Functions A0 to A14 Address input WE Read/write control input OE Output enable input CE Chip enable input I/O1 to I/O8 Data input/output VCC, GND Power supply pins

Absolute Maximum Ratingsat Ta=25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max 7.0 V Input pin voltage VIN –0.5* to VCC +0.5 V I/O pin voltage VI/O –0.5* to VCC +0.5 V Allowable power dissipationPd max LC36256AL 1.0 W LC36256AML 0.7 W Operating temperature rangeTopr 0 to +70 °C Storage temperature range Tstg –55 to +150 °C * –3.0 V when pulse width is less than 50 ns DC Recommended Operating Ranges at Ta = 0 to +70°C Parameter Symbol min typ max Unit Power supply voltage VCC 4.5* 5.0 5.5 V Input high level voltage VIH 2.2* VCC +0.3 V Input low level voltage VIL –0.3* +0.8 V * –3.0 V when pulse width is less than 50 ns Parameter Symbol Conditions min typ* max Unit Input leakage currentILI VIN = 0 to VCC –0.5 +0.5 µA I/O leakage current ILO VCE = VIH or VOE = VIH, –0.5 +0.5 µAVI/O= 0 to VCC Output high level voltageVOH IOH = –1.0mA 2.4 V Output low level voltageVOL IOL = 2.1mA 0.4 V Operating supply ICCA1 VCE £ 0.2V, 1 5 mA current (DC) VIN £ 0.2V or VIN ‡ VCC –0.2V ICCA2 VCE = VIL, II/O=0mA 3 10 mA min cycle 70ns 30 50 Average operating ICCA3 Duty = 100% 85ns 25 50 mAsupply current I I/O= 0mA 100ns 23 50 120ns 20 50 0 to +70°C 25 Standby supply ICCS1 VCE ‡VCC -0.2V 0 to +40°C 5 µA current 25°C 0.5 2 ICCS2 VCE = VIH 0.4 2 mA * Reference values at VCC = 5 V, Ta = 25°C LC36256AL, AML-70/85/10/12 No. 4163-3/7 Access time

LC36256AL, AML-70/85/10/12 No. 4163-4/7 Input/Output Capacitance at Ta = 25°C, f = 1 MHz Parameter Symbol Conditions min typ max Unit Input/output capacitance C I/O VI/O = 0V 8 pF Input capacitance C IN VIN = 0V 6 pF Note: These parameters were obtained through sampling, and not full-lot measurement. AC testing conditions Input pulse voltage level: 0.8 V, 2.2 V Input rise and fall time: 5 ns Input - output timing level: 1.5 V Output load : 1 TTL gate + CL = 100 pF (85 ns/100 ns/120 ns)

1 TTL gate + CL = 30 pF (70 ns)

(including scope and jig capacitance) Read Cycle Parameter Symbol LC36256AL, AML -70 -85 -10 -12 Unit min max min max min max min max Read cycle time tRC 70 85 100 120 ns Address access timetAA 70 85 100 120 ns CE access time tCA 70 85 100 120 ns OE access time tOA 35 45 50 60 ns Output hold time tOH 20 20 20 20 ns CE output enable timetCOE 10 10 10 10 ns OE output enable timetOOE 5 5 5 5 ns OE output disable timetCOD 0 30 0 30 0 30 0 30 ns OE output disable timetOOD 0 30 0 30 0 30 0 30 ns Write Cycle LC36256AL, AML Parameter -70 -85 -10 -12 Unit min max min max min max min max Write cycle time tWC 70 85 100 120 ns Address valid to end of writetAW 65 75 80 100 ns Address setup timetAS 0 0 0 0 ns Write pulse width tWP 50 50 60 70 ns CE setup time tCW 65 75 80 100 ns Write recovery time (WE)tWR 0 0 0 0 ns Write recovery time (CE)tWR 1 0 0 0 0 ns Data setup time tDS 30 30 35 40 ns Data hold time tDH 0 0 0 0 ns WE output enable timetWOE 10 10 10 10 ns WE output disable timetWOD 0 25 0 25 0 25 0 25 ns

LC36256AL, AML-70/85/10/12 No. 4163-5/7 Timing Chart

  • Read Cycle (1): CE = OE = VIL, WE = VIH
  • Read Cycle (2): WE = VIH
  • Write Cycle (1): WE Control Note (6)

LC36256AL, AML-70/85/10/12 No. 4163-6/7

  • Write Cycle (2): CE Control Note (6) Notes (1)tCOD , tOOD , and tWOD are defined as the time at which the outputs becomes the high impedance state and are not referred to output voltage levels. (2)An external antiphase signal must not be applied when DOUT is in the output state. (3)tWP is the time interval that CE and WE are low-level and is defined as the interval from the falling of WE to the rising of CE or WE whichever is earlier. (4)tCW is the time interval that CE and WE are low-level and is defined as the time from the falling of CE to the rising of CE or WE whichever is earlier. (5)D OUT goes to the high-impedance state when either OE is high-level, CE is high-level, or WE is low-level. (6)When OE is high-level during the write cycle, DOUT goes to the high-impedance state. Data Retention Characteristicsat Ta = 0 to +70°C Parameter Symbol Conditions min typ* max Unit Data retention supply voltageVDR VCE ‡ VCC –0.2V 2.0 5.5 V VCC = 3.0V, 0 to +70°C 10 ICCDR1 VCE ‡ 2.8V 0 to +40°C 2 µA Data retention supply current 25°C 0.25 1 ICCDR2 VCC = 2.0 to 5.5V, VCE ‡ VCC –0.2V 0.5 25 µA CE setup time tCDR 0 ns CE hold time tR tRC ** ns * Reference values at VCC = 5V, Ta = 25°C ** tRC = Read Cycle time Data Retention Waveform

LC36256AL, AML-70/85/10/12 PS No. 4163-7/7 This catalog provides information as of February, 1996. Specifications and information herein are subject to change without notice. n No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n Anyone purchasing any products described or contained herein for an above-mentioned use shall: À Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: \` Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.