LC361000AMLL SANYO | Alldatasheet

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  • Access time POOURTOOUETOOEDS } % 70 ns (max.): LC361000AMLL, ATLL, ARLL-70 i aloe ae 100 ns (max.): LC361000AMLL, ATLL, ARLL-10 + Low current drain During standby 2.0 pA (max.)/Ta = 25°C SANYO: SOP32 4.0 pA (max.)/Ta =0 to +40°C 20.0 A (max./Ta = 010 +70°C unit: mm During data retention 3224-TSOP32 1.2 pA (max,)Ta= 25°C 24 A (max.)/Ta=0 to +40 °C 12.0 pA (max. Ta = 0 to +70°C {LC361000ATLL, ARLL] E i During operating (DC) ‘en 15 mA (max.) { * Single 5 Vpower supply: 5 V +10% | + Data retention supply voltage: 2.0 to 5.5 V ¢ eo * No clock required (Fully static memory) | Es * All inpuvoutput levels are TTL compatible * Common input/output pins, three output states + Package Ey SOP 32-pin (525 mil) plastic package: ah LC361000AMLL TSOP 32-pin (8 mm x 20 mm) plastic package, normal: LC361000ATLL Be : TSOP 32-pin (8 mm x 20 mm) plastic package, reversed: i SANYO: TSOP92 (TYPE-) LC36!000ARLL SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 93096HA (OT) No. 5398-1/8

LC361000AMLL, ATLL, ARLL-70/10 a Pin Assignments , TSOP32 (normal sopaz _ wo [] [22] vee as Ce] FSzl ase as (3) [23] 1708 me Be ‘ae [zg] 1707 Bel “ 2 Cel [27] 1706 La cee Ce [ze] x05 ae [al [es] ve ass is] 725 , wee [24] GNo a7] [ee] «22 wc. C5) Fes oo te Ga [22) 1voe “e len “n : te (2) 1701 “oo [20] ao 1 as (44) ase} [as] ass vs tal ‘ sa [el za] OE Mec Top view soon ae fio] fea] aso as [i] ea] ET wt Ev ‘TSOPS2 (reversed) ve: [ia [za] 1707 ; = wee [ial [ia] 1706 See 2 as Ca] fea} a0 roa [i5| [2a] x05 ac ao ono [5] 10a a2 Tei Bes: Eel [24) sno Top view sear wc. Col Fes Sita [25] tvos ass C2 1708 aes [28] 1707 es f23) 1708 as3 Ca] fas) cos ae Co] [3a] azo as Cd Bal ass Top view aosz7e Block Diagram Aiio Ago ws vec toe 5 Memory Aage a coll matrix aise ag 1024 x 1024 exe A16 © A1ao Al2o a7 He AS oO | tae VO circuit AS oT Butter column decoder Azey A1o il Ad © =r FE ot P| butler CEi o {) joel “ I/704 1708 A05773

LC361000AMLL, ATLL, ARLL-70/10 ce RI Pin Functions A010 ATG [WE __|_Read/write control input [OE _|_Outputenabie input CET, Cee WO1toVO8 | Data inpuvoutput Function Logic a rT A A Ouiput cisable [tw [| HT High impedance Versa [eT ripen los X: Hort Specifications Absolute Maximum Ratings at Ta = 25°C a Taxiram apy vtoge ote: * —3.0 V when pulse width is fess than 50 ns. ‘Stresses greater than the above listed maximum value may result in damage to the device. DC Recommended Operating Ranges at Ta = 0 to +70°C a Power supply voltage [| veo fas [50 ss Pv input igh vet otago [vm [22 |_| “Vegeos |v | Note: * -3.0 V when pulse width is less than 50 ns. No. 5398-3/8

LC361000AMLL, ATLL, ARLL-70/10 SSS lecan VGET $0.2 V, Vogg 2 Veg - 0.2 V, Vin s0.2 Vor 10 mA Operating supply current (DC) Vin 2 Veo - 0.2 V, Iyq = 0 mA | ecne [Wert = Vi Voss =VinVin=Vin oVowoma | | 7 | | ma enn nasty, [oon [so | [owrsore | [a | “ieose[Veea=vaorvarevn | S| oe 8 [inputiesiageewrent [ks [Veg VGEI = Vin Of Voge = Vic. OF VE = Vin! Guiputhighieveivotage | Vow [lgu=-10mA_— S| i ae Note: * Reference value at Voc = 5 V, Ta = 25°C. Input/Output Capacitances at Ta = 25°C, f = 1 MHz a GP 6 Note: These parameters were obtained through sampling, and not full-lot measurement. AC Test Conditions Input pulse voltage level OB V,2.2V Input rise and (all time [so Input and output timing evel

1 TTL gate + C, = 100 pF (70 ns/100 ns)

Output load (including scope and jig capacitances) eee No. 5398-4/8

LC361000AMLL, ATLL, ARLL-70/10 CC Read Cycle LCO361000AMLL, ATLL, ARLL [Readeycietime | tae Poo es [Adsressaccesstime Tx Pts [CER accesstime tows P00 as [cee accesstime tone P00 ae [OE accesstime to Pe a oe A ‘TEX output enable time [toon [tte CE2 output enabie time [tcoee [to ts {GE output enable tine [tooe [Os Ps Ei output cisabie tine [tooo Pas GE2 output disable time [cove | es ‘SE output alsable time [tooo [as ae Write Cycle LC361000AMLL, ATLL, ARLL Parameter eB Write cycle time Pte [0 t00 ‘Adress valid 10 6nd of write [tow [60 ‘Adress setup time Jus [os Write pulse width [twe [so [CE sem time tows [0s CE2 setup time [tows [eo Pos [Wie ecoverytime wa [es [CEI witerecoverytime ftw PCs | GE2 wile recovery time Pewee [oP [Dswsouptne i os | | dT Data hoid time [ton fe EF ata hod ime [tow [os CE2 data hotd time [tow [oo Ps WE output enable time [wos | tg WE output disable timo [woo [as os Timing Chart Read Cycle (1): CEI = OF = Vj, CE2 = Vy, WE = Vix tac faa Date out Previous date vera KX XX pete veiid non774 a No. 5398-5/8

LC361000AMLL, ATLL, ARLL-70/10 a SS Read Cycle (2): WE = Vin trac KS taa me XXX ALLL =a te = AD)OR]R a LLL LA pe Write Cycle (1): WE control (Note 6) two i —_—, | = AWARD MARSA tas tw Note 3 om Note2 [> | ‘ | no? Note 1 twoe Noted “SZSZSZSZSZSZSZN ZSZNZNINZZNZV High impedence . No. 5398-6/8

LC361000AMLL, ATLL, ARLL-70/10 a Write Cycle (2): CEI control (Note 6) twe = AAA * AAKAAAAAAAAAAAR ot A x a 7 NI “ Cf ag SSS * YQ KZ ZZ * MAAN Z tons Note 2 twop toes To ote 4 Bete out SSS | WAVAY,{ Tigh impedence i 408777 Write Cycle (3): CE2 control (Note 6) twe * ANY * AAAAAAAAAAAANAAAA ter Y = \\NAAA lor typ =< i tone Note 4 N Date out DSBS WAVA A igh impedence n0s778 Note: 1. tcoo1 tone: toon: and twop are stipulated as the time until the outputs reach the high-impedance state, and are not determined by the output voltage levels. 2. Reverse phase signals must not be applied externally when the data outputs are in the output state. — — 3. {WP is datinad as the period when CE1 and WE are low and CE2 is high, from the falling edge of WE until either a rising edge of GEi or WE ora falling edge of CE2, whichever of these happens first. 4. twor and twce are defined as the periods when TE and WE are low and CE2 Is high, from either a falling edge of CET or a rising edge of CE2, Until a rising edge of CET or WE, or a falling edge of CE2, whichever happens first. _ 5. The data outputs will be in the high-impedance state if either OE Is high, CE1 Is high, CE2 is low, or WE Is low. 6. If OE goes high during a write cycle, the data outputs will go to the high-impedance state. ee No. 5398-7/8

LC361000AMLL, ATLL, ARLL-70/10 Data Retention Characteristics at Ta = 0 to +70°C aa a \\ VaET 2 Voo- 0.2 V, Voge 2 Voc - 0.2 V, v Data retention supply voltage ORY | orVoes $0.2 V | Von [Voezso2v 0 ss Woo =30¥, [temo [| Data retention supply current Mosz®Voc~O2ViorVceeso2v [asc [ [oa [12 | a [eso [es Te | SR SS Note: * Reference value at Ta = 25°C. Data Retention Waveforms (1): (CEI control) toon Data retention mode tr VE neneeeee ene nee cnc c enn eeeennneeetafennenneen eens VORA n-ea-Jfonn--n nnn nnn VoEa Voer 2 Vog=0.2V CN . 405778 Data Retention Waveforms (2): (CE2 control) Data retention mode Veo ABV cece eee eeteeeeeeene fon --snnnnnnnnne toon. tr Voee VDR2 ~mnnnn ne pose neces v nS BR ™ Voe2 $0.2 V GND wanna nn non nn En En 405760 @ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-pravention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. IB Anyone purchasing any products described or contained herein for an above-mentioned use shall: ig any pI ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and alll their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. @ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production, SANYO believes information herein Is accurate and reliable, but no guarantees ara made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1996. Specifications and information herein are subject to change without notice. No. 5398-8/8