LC35W1000BM SANYO | Alldatasheet

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Technical content

Features

  • Low-voltage operation: 2.7 to 3.6 V
  • Wide operating temperature range: –40 to +85°C
  • Access time: 70 ns (maximum): LC35W1000BM and LC35W1000BTS-70U. 100 ns (maximum): LC35W1000BM and LC35W1000BTS-10U.
  • Low current drain Standby mode: 0.1 µA (typical*) at Ta = +25°C 10.0 µA (maximum) at Ta = –40 to +70°C 20.0 µA (maximum) at Ta = –40 to +85°C
  • Data retention voltage: 2.0 to 3.6 V
  • No clock required (fully static circuits)
  • Input/output shared function pins, 3-state output pins
  • Package 32-pin SOP (525 mil) plastic package: LC35W1000BM 32-pin TSOP (8
  • 14 mm) plastic package (Normal): LC35W1000BTS Package Dimensions unit: mm 3205A-SOP32 unit: mm 3228A-TSOP32DA 0.2 3.1max 14.0 0.8 1732 20.5 11.2 0.41.27 0.15(0.73) (2.7) Preliminary SANYO: SOP32 [LC35W1000BM-70U/10U] 0.5 1 16 32 17 1.2max 8.0 0.08 12.4 14.0 0.5 0.2 0.125(0.25) (1.0) SANYO: TSOP32DA [LC35W1000BTS-70U/10U] LC35W1000BM, BTS-70U/10U SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN Asynchronous Silicon Gate 1M (131,072 words · 8 bits) SRAM CMOS IC Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

No. 6624-2/9 LC35W1000BM, BTS-70U/10U A13487 A13488

No. 6624-3/9 LC35W1000BM, BTS-70U/10U Control circuit Data control circuitOutput buffer Input data buffer Memor y cell array Ra w Decoder Address buffer Pin Functions A0 to A16 Address input WE Ready/write control input OE Output enable input CE, CE2 Chip enable input I/O1 to I/O8 Data I/O VCC , GND Power supply, ground Function Table Note: X indicates H or L. *: For pulse widths under 30 ns: –2.0 V Note: This chip may be destroyed if any stress in excess of the absolute maximum ratings is applied. Mode CE1 CE2 OE WE I/O Supply current Ready cycle L H L H Data output ICCA Write cycle L H X L Data input ICCA Output disable L H H H High impedance ICCA Unselected H X X X High impedance ICCS X L X X High impedance ICCS Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max 4.6 V Input pin voltage VIN –0.3* to VCC + 0.3 V I/O pin voltage VI/O –0.3 to VCC + 0.3 V Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Specifications Maximum Ratings at Ta = 25°C

No. 6624-4/9 LC35W1000BM, BTS-70U/10U Parameter Symbol Conditions Ratings Unit min typ max Supply volgate VCC 2.7 3.3 3.6 V High-level input voltage VIH 0.8VCC VCC + 0.3 V Low-level input voltage VIL –0.3* 0.2VCC V DC Allowable Operating Range at Ta = –40 to +85°C Note: * The minimum value is –3.0 V for pulse width under 50 ns. Note: * Reference values when VCC = 3.0 V and Ta = 25°C. Parameter Symbol Conditions Ratings Unit min typ max Input leakage current ILI VIN = 0 to VCC –1.0 +1.0 µA I/O leakage current ILO VCE1 = VIH or VCE2 = VILor VOE = VIH or –1.0 +1.0 µAVWE = VIL, VI/O= 0 to VCC Outpu high-level voltage VOH1 VOH1 = –2.0 mA VCC – 0.4 V VOH2 VOH2 = –100 µA VCC – 0.1 V Outpu low-level voltage VOL1 VOL1 = 2.0 mA 0.4 V VOL2 VOL2 = –100 µA 0.1 V Operating supply current ICCA2 VCE1 = VIL, VCE2 = VIH, II/O= 0 mA, VIN = VIH or VIL 1.2 mA (CMOS inputs) VCE1 = VIL, VCE2 = VIH, min cycle 70 ns 25 ICCA3 II/O= 0 mA, VIN = VIH or VIL, 100 ns 20 mA DUTY100% 1 µs cycle 2 Standby mode supply current VCE2 ≤ 0.2 V or Ta ≤ 85°C 20 (VCC – 0.2 V/0.2 V inputs) ICCS1 (VCE1 ‡ VCC – 0.2 V, Ta ≤ 70°C 10 µA VCE2 ‡ VCC – 0.2 V) Ta ≤ 25°C 0.1 (CMOS inputs) ICCS2 VCE1 = VIH or VCE2 = VIL, VIN = 0 to VCC 0.4 mA Note: These parameters are not measured for all devices, but are sampled values. Parameter Symbol Conditions Ratings Unit min typ max Input capacitance C IN VIN = 0 V 6 10 pF I/O capacitance C I/O VI/O= 0 V 6 10 pF I/O Capacitances at Ta = 25°C, f = 1 MHz

Input pulse voltage levels: VIL = 0.2 VCC , VIH = 0.8 VCC Input rise and fall times: 5 ns Input and output timing leves: 1/2 V CC Output load: 30 pF (including the jig capacitance) No. 6624-5/9 LC35W1000BM, BTS-70U/10U Read cycle Parameter Symbol –70U –10U min max min max Unit Read cyle time tRC 70 100 ns Address access time tAA 70 100 ns CE1 access time tCA1 70 100 ns CE2 access time tCA2 70 100 ns OE access time tOA 50 50 ns Output hold time tOH 10 10 ns CE1 output enable time tCOE1 10 10 ns CE2 output enable time tCOE2 10 10 ns OE output enable time tOCE 5 5 ns CE1 output disable time tCOD1 40 35 ns CE2 output disable time tCOD2 40 35 ns OE output disable time tOOD 35 30 ns Write cycle Parameter Symbol –70U –10U min max min max Unit Write cyle time tWC 70 100 ns Address setup time tAS 0 0 ns Write pulse width tWP 50 70 ns CE1 setup time tCW1 60 90 ns CE2 setup time tCW2 60 90 ns Write recovery time tWR 0 0 ns CE1 write recovery time tWR1 0 0 ns CE2 write recovery time tWR2 0 0 ns Data setup time tDS 40 50 ns Data hold time tDH 0 0 ns CE1 data hold time tDH1 0 0 ns CE2 data hold time tDH2 0 0 ns WE output enable time tWOE 5 5 ns WE output disable time tWOD 35 30 ns

Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH Read cycle (2) : WE = VIH No. 6624-6/9 LC35W1000BM, BTS-70U/10U

No. 6624-7/9 LC35W1000BM, BTS-70U/10U Write cycle (6) (WE = control) *6 A13492 Write cycle (2) (CE1 = control) *6 A13493

Notes:1. The times tCOD1 , tCOD2 , tOOD , and tWOD are stipulated as the times until the output reaches the high-impedance state. They are not stipulated by output voltage level. 2. Do not apply reverse phase signals to the data outputs when the data outputs are in the output state. 3. tWP is the period that CE1 and WE are at the low level and CE2 is at the high level, and is defined as the time from the fall of WE until the rise of CE1 or WE or the fall of CE2, whichever occurs first. 4. tCW1 and tCW2 are the period that CE1 and WE are at the low level and CE2 is at the high level, and are defined as the time from the fall of CE1 or the rise of CE2 to the rise of either CE1 or WE or the fall of CE2, whichever occurs first. 5. The data outputs go to the high-impedance state when any one of the following states hold: OE is at the high level, CE1 is at the high level, CE2 is at the low level, or WE is at the low level. 6. If OE is at the high level during the write cycle, the data outputs will go to the high-impedance state. No. 6624-8/9 LC35W1000BM, BTS-70U/10U Parameter Symbol Conditions Ratings Unit min typ max Data retention supply voltage VDR2 VCE2 ≤ 0.2 V 2.0 3.6 V VCC = 3.0 V, VCE1 ‡ VCC – 0.2 V, –40°C to +85°C 16 Data retention supply current ICCDR1 VCE2 ‡ VCC – 0.2 V, –40°C to +70°C 8 µA or VCE2 ≤ 0.2 V +25°C 0.1 Chip enable setup time tCDR 0 ns Chip enable hold time tR 5 ms Data Retention Characteristics at Ta = –40 to +85°C Data Retention Waveforms (1) (CE1 control) Note: * Ta = +25°C Data retention mode A13494 Data Retention Waveforms (2) (CE2 control) D ata retention m ode A 13495

PS No. 6624-9/9 LC35W1000BM, BTS-70U/10U This catalog provides information as of April, 2002. Specifications and information herein are subject to change without notice. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics,and functions of the described products in the independent state,and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.