LC3564CT

LC3564CM SANYO | Alldatasheet

Document overview

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Technical content

Features

• Supply voltage range: 2.7 to 5.5 V — In 5-V operation mode: 5.0 V ±10% — In 3-V operation mode: 3.0 V ±10%
• Address access time (tAA) — In 5-V operation mode: LC3564CM, and CT-55U: 55 ns (max) LC3564CM, and CT-70U: 70 ns (max) — In 3-V operation mode: LC3564CM, and CT-70U: 200 ns (max)
• Ultralow standby current — In 5-V operation mode: 1.0 µA (Ta ≤70°C), 3.0 µA (Ta ≤85°C) — In 3-V operation mode: 0.8 µA (Ta ≤70°C), 2.5 µA (Ta ≤85°C)
• Operating temperature range — In 5-V operation mode: –40 to 85°C — In 3-V operation mode: –40 to 85°C
• Data retention supply voltage: 2.0 to 5.5 V
• All input and output levels: — In 5-V operation mode: TTL compatible levels — In 3-V operation mode: VCC –0.2 V/0.2 V
• Three control inputs: OE, CE1, and CE2
• Shared input and output pins, three-state outputs
• No clock required
• Packages 28-pin SOP (450 mil) plastic package: LC3564CM 28-pin TSOP (8 × 13.4 mm) plastic package: LC3564CT CMOS IC 80502RM (OT) No. 6635-1/11 SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 64K (8192-word × 8-bit) SRAM with OE, CE1, and CE2 Control Pins LC3564CM, 3564CT-55U/70U

No. 6635-2/11 LC3564CM, CT-55U/70U Package Dimensions unit: mm 3187B-DIP28D unit: mm 3221-TSOP28A 0.15 18.0 (0.75) 1.27 0.4 8.4 11.8 1.0 (2.2) 0.1 2.5max SANYO: DIP28D [LC3564CM] 13.4 11.8 281 0.05 0.5 (1.0) 8.0 0.2 0.125 1.2max (0.43) 0.55 SANYO: TSOP28A [LC3564CT] Pin Assignments NC

28 VCC

26 CE2

23 A11

21 A10

20 CE1

19 I/O8

18 I/O7

17 I/O6

16 I/O5

15 I/O4

No. 6635-3/11 LC3564CM, CT-55U/70U Block Diagram Address buffer Pow decoder Memory cell array Output buffer Input data buffer Data control circuit Control circuit A0 to A12 I/O1 to I/O8 VCC GND CE1 CE2 WE OE A13512 Pin Functions A0 to A12 Address inputs WE Read/write control input OE Output enable input CE1, CE2 Chip enable inputs I/O1 to I/O8 Data I/O VCC, GND Power supply and ground Function Table X : H or L Mode CE1 CE2 OE WE I/O Supply current Read cycle L H L H Data output ICCA Write cycle L H X L Data input ICCA Output disable L H H H High impedance ICCA Not selected H X X X High impedance ICCS X L X X High impedance ICCS

No. 6635-4/11 LC3564CM, CT-55U/70U Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max 7.0 V Input voltage VIN –0.3* to VCC + 0.3 V I/O voltage VI/O –0.3 to VCC + 0.3 V Operating temperature Topr –40 to +85 Storage temperature Tstg –55 to +125 Specifications Absolute Maximum Ratings at Ta = 25°C Note: For pulse widths less than 30 ns: –3.0 V Note: These parameters are sampled, and are not measured for every unit. Note: For pulse widths less than 30 ns: –3.0 V Note *: Reference values at VCC = 5 V, Ta = 25°C [5-V Operation] Parameter Symbol Conditions Ratings Unit min typ max I/O pin capacitance CI/O VI/O = 0 V pF Input pin capacitance CIN VIN = 0 V pF Input and Output Capacitances at Ta = 25°C, f = 1 MHz Parameter Symbol Conditions Ratings Unit min typ max Supply voltage VCC 4.5 5.0 5.5 V Input voltage VIH 2.2 VCC + 0.3 V VIL –0.3* +0.8 V DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V Parameter Symbol Conditions Ratings Unit min typ * max Input leakage current ILI VIN = 0 to VCC –1.0 +1.0 µA I/O leakage current ILO VCE1 = VIH or VCE2 = VIL or VOE = VIH or –1.0 +1.0 µA VWE = VIL, VI/O = 0 to VCC Output high-level voltage VOH IOH = –1.0 mA 2.4 V Output low-level voltage VOL IOL = 2.0 mA 0.4 V VCE1 ≤0.2 V, VCE2 ≥VCC – 0.2 V, Ta ≤70°C 0.01 1.0 µA ICCA1 II/O = 0 mA, VIN ≤0.2 V or VCC – 0.2 V/0.2 V VIN ≥VCC – 0.2 V Ta ≤85°C 3.0 inputs min LC3564CM, CT-55U ICCA4 cycle LC3564CM, CT-70U mA 1 µs cycle Operating supply current ICCA2 VCE1 = VIL, VCE2 = VIH, II/O = 0 mA, mA VIN = VIH or VIL TTL inputs min LC3564CM, CT-55U ICCA3 cycle LC3564CM, CT-70U mA 1 µs cycle Standby mode supply VCC – 0.2 V/0.2 V VCE2 ≤0.2 V or Ta ≤70°C 0.01 1.0 µA current inputs ICCS1 VCE1 ≥VCC – 0.2 V VCE2 ≥VCC – 0.2 V Ta ≤85°C 3.0 TTL inputs ICC2 VCE2 = VIL or VCE1 = VIH, VIN = 0 to VCC 2.0 mA VCE1 ≤0.2 V, VCE2 ≥VCC – 0.2 V, II/O = 0 mA, DUTY = 100% VCE1 = VIL, VCE2 = VIH, II/O = 0 mA, DUTY = 100%

No. 6635-5/11 LC3564CM, CT-55U/70U LC3564CM, CT Parameter Symbol -55U -70U Unit min max min max Read cycle time tRC ns Address access time tAA ns CE1 access time tCA1 ns CE2 access time tCA2 ns OE access time tOA ns Output hold time tOH ns CE1 output enable time tCOE1 ns CE2 output enable time tCOE2 ns OE output enable time tOOE ns CE1 output disable time tCOD1 ns CE2 output disable time tCOD2 ns OE output disable time tOOD ns Read Cycle LC3564CM, CT Parameter Symbol -55U -70U Unit min max min max Write cycle time tWC ns Address setup time tAS ns Write pulse width tWP ns CE1 setup time tCW1 ns CE2 setup time tCW2 ns Write recovery time tWR ns CE1 write recovery time tWR1 ns CE2 write recovery time tWR2 ns Data setup time tDS ns Data hold time tDH ns CE1 data hold time tDH1 ns CE2 data hold time tDH2 ns WE output enable time tWOE ns WE output disable time tWOD ns Write Cycle Parameter Conditions [AC Test Conditions] Input pulse voltage VIH = 2.4 V, VIL = 0.6 V Input rise and fall times 5 ns Input and output timing level 1.5 V Output load LC3564CM and CT-55U/70U: 30 pF + 1 TTL gate (Including the jig capacitance.)

[3-V Operation] No. 6635-6/11 LC3564CM, CT-55U/70U Note *: Reference values at VCC = 3 V, Ta = 25°C Parameter Symbol Conditions Ratings Unit min typ max Supply voltage VCC 2.7 3.0 3.3 V Input voltage VIH VCC – 0.2 VCC V VIL 0.2 V DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 2.7 to 3.3 V Parameter Symbol Conditions Ratings Unit min typ * max Input leakage current ILI VIN = 0 to VCC –1.0 +1.0 µA I/O leakage current ILO VCE1 = VIH or VCE2 = VIL or VOE = VIH or –1.0 +1.0 µA VWE = VIL, VI/O = 0 to VCC Output high-level voltage VOH IOH = –0.5 mA VCC – 0.2 V Output low-level voltage VOL IOL = 1.0 mA 0.2 V VCE1 ≤VIL, VCE2 ≥VIH, Ta ≤70°C 0.01 0.8 µA ICCA1 II/O = 0 mA, VIN ≤VIL or VIN ≥VIH Ta ≤85°C 2.5 Operation supply current VCC – 0.2 V/0.2 V min LC3564CM, CT-70U mA inputs ICCA4 cycle 1 µs cycle mA Standby mode supply VCC – 0.2 V/0.2 V VCE2 ≤0.2 V or Ta ≤70°C 0.01 0.8 µA current inputs ICCS1 VCE1 ≥VIH VCE2 ≥VIH Ta ≤85°C 2.5 VCE1 ≤VIL, VCE2 ≥VIH, II/O = 0 mA, DUTY = 100%

No. 6635-7/11 LC3564CM, CT-55U/70U LC3564CM, CT-70U Parameter Symbol -10 Unit min max Read cycle time tRC 200 ns Address access time tAA 200 ns CE1 access time tCA1 200 ns CE2 access time tCA2 200 ns OE access time tOA 100 ns Output hold time tOH ns CE1 output enable time tCOE1 ns CE2 output enable time tCOE2 ns OE output enable time tOOE ns CE1 output disable time tCOD1 ns CE2 output disable time tCOD2 ns OE output disable time tOOD ns Read Cycle LC3564CM, CT-70U Parameter Symbol -70 Unit min max Write cycle time tWC 200 ns Address setup time tAS ns Write pulse width tWP 140 ns CE1 setup time tCW1 150 ns CE2 setup time tCW2 ns Write recovery time tWR ns CE1 write recovery time tWR1 ns CE2 write recovery time tWR2 130 ns Data setup time tDS ns Data hold time tDH ns CE1 data hold time tDH1 ns CE2 data hold time tDH2 ns WE output enable time tWOE ns WE output disable time tWOD ns Write Cycle Parameter Conditions [AC Test Conditions] Input pulse voltage VIH = VCC – 0.2 V, VIL = 0.2 V Input rise and fall times 10 ns Input and output timing level 1.5 V Output load LC3564CM, CT-70U : 30pF (Including the jig capacitance.)

Read Cycle *1 Write Cycle (1): WE Write *6 No. 6635-8/11 LC3564CM, CT-55U/70U tRC tAA tCA2 tCA1 tOA tOOE tOOD tCOD1 tCOD2 tOH tCOE1 tCOE2 A0 to A12 CE2 CE1 OE INVALID DATA H or L DOUT1 to 8 OUTPUT DATA VALID A13513 tWC tAS tWP *3 tCW2 *4 tCW1 *4 tWOD tWR tWOE tDH tDS tOH INVALID DATA H or L A0 to A12 WE CE2 CE1 DIN1 to 8 DOUT1 to 8 DATA IN STABLE A13514

No. 6635-9/11 LC3564CM, CT-55U/70U Write Cycle (2): CE1 Write *6 tWC tAS tWP *3 tCW2 *4 tCW1 *4 tWOD tWR1 tDH1 tDS tCOE1 A0 to A12 WE CE2 CE1 DIN1 to 8 DOUT1 to 8 DATA IN STABLE A13515 INVALID DATA H or L Write Cycle (3): CE2 Write *6 Notes: 1. Hold WE high during the read cycle. 2. Applications must not apply reverse phase signals to the DOUT pins when those pins are in the output state. 3. The time tWP is the period when CE1 and WE are low and CE2 is high, and is defined as the time from the fall of WE until either CE1 or WE rises, or CE2 falls, whichever occurs first. 4. The times tCW1 and tCW2 are periods when CE1 and WE are low and CE2 is high. They are defined as the times from the fall of CE1 or the rise of CE2 to the rise of CE1 and WE, or the fall of CE2, whichever occurs first. 5. The DOUT pins will be in the high-impedance state if either OE is high, CE1 is high, CE2 is low, or WE is low. 6. OE must be held either at VIH or VIL during the write cycle. 7. The DOUT pins have the same phase as the write cycle write data. tWC tAS tWP *3 tCW2 *4 tCW1 *4 tWOD tWR2 tDH2 tDS tCOE2 A0 to A12 WE CE2 CE1 DIN1 to 8 DOUT1 to 8 DATA IN STABLE A13516 INVALID DATA H or L

No. 6635-10/11 LC3564CM, CT-55U/70U Parameter Symbol Conditions Ratings Unit min typ max Data retention supply voltage VDR VCE2 ≤0.2 V or 2.0 5.5 µA VCE1 ≥VCC – 0.2 V, VCE2 ≥VCC – 0.2 V VCC = 3V, VCE2 ≤0.2 V, Ta ≤70°C 0.8 µA Data retention supply current ICCDR or VCE1 ≥VCC – 0.2 V, VCE2 ≥VCC – 0.2 V Ta ≤85°C 2.5 Chip enable setup time tCDR ns Chip enable hold time tR tRC* ns Data Retention Characteristics at Ta = –40 to +85°C Note *: tRC is the read cycle time. Note *:In 5-V operation: 4.5 V In 3-V operation: 2.7 V Data Retention Waveforms (1): CE1 Control Notes on Circuit Design When actually design a circuit using these devices, take the following points into consideration and design the circuit so that none of the maximum rating items are ever exceeded.

• Variations in the supply voltage
• Variations in the electrical characteristics of components such as semiconductor devices, resistors, and capacitors.
• Ambient temperature
• Variations in input and clock signals
• Possible application of abnormal pulses Also, these devices must be operated within the ranges stipulated in the allowable operating ranges. If CMOS IC input pins are left open, intermediate potential input voltages may occur leading to incorrect operation due to through currents or other phenomenon. Applications must handle unused input pins appropriately. tCDR Data retention mode VCE1 ≥ VCC–0.2V tR VCC VCCL VIH VDR VCE1 GND A13517 tCDR Data retention mode VCE2 ≤ 0.2V tR VCC VCCL VCE2 VDR VIL GND A13518 Data Retention Waveforms (2): CE2 Control

PS No. 6635-11/11 LC3564CM, CT-55U/70U This catalog provides information as of August, 2002. Specifications and information herein are subject to change without notice. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.