LC338128PL

LC338128P SANYO | Alldatasheet

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‘Ordering number : ENK4711A CMOS LSI LC338128P, M, PL, ML-70/80/10 yi 1 MEG (131072 words x 8 bits) Pseudo-SRAM Preliminary Overview Package Dimensions The LC338128 series is composed of pseudo static RAM unit: mm that operate on a single 5 V power supply and is organized 3192-DIP32 as 65536 words x 16 bits. By using memory cells each composed of a single transistor and capacitor, together (L0338128P, PL} with peripheral CMOS circuitry, this series achieves ease » ” of use with high density, high speed, and low power poe 2 0 ant dissipation. Since the LC338128 series products provide ala a refresh counter and timer on chip, this series can easily P a3 accomplish auto-refresh and self-refresh by means of Leen! i RFSH input. The available packages are the 32-pin DIP u 41.9 Bid S| with a width of 600 mil, and the 32-pin SOP with a width nn i THOD NOOO of $25 mil. AAR Re Features u O48 254] | Loti * 131072 words x 8 bits configuration SANYO: DIP32 + CE access time, OE access time, cycle time, operating supply current and self-refresh current 2. . unit: mm coanes 3205-SOP32 “mm | 70 [0 To [CEaccesstime | 7ons [eons | toons _| 0398128M, MU [OEeccessime | asns_ | sors | a0ns_| H0s98128M, MA] * Single 5 V + 10% power supply | * All inputs and outputs (I/O) TTL compatible i * Fast access time and low power dissipation aE i RECEEGE ry * 8 ms refresh using 512 refresh cycles lose fos * Supports auto-refresh, self-refresh and CE-only refresh + Low-power version: 100 wA standby current 2, lecsp2. = 100 WA * Packages SANYO: SOP32 32-pin DIP (600mil) plastic package: LC338128P, PL 32-pin SOP (450mil) plastic package: LC338128M, ML SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN j 53096HA (OT)/62494TH No. 4711-1/10

LC338128P, M, PL, ML-70/80/10 Block Diagram Voc GND j j = s 6 3 8 8 Sense amplitior 2 Column A150 AD address UO gate 3 5 ri butter (8) 2 3 (ra ‘AB to AO => Row address ‘ae =>) raaie EE) a

8 Memory call array

| K 512 x 256 x8 = Refresh ‘4 s counter (9) [s_ => eP* = — || 2 3 [8 i FI ce | H ce Refresh s bk

9 Clock controler [e—_|Reftesh timer 3

cs O— RFSH O ry) Eo rt) Wo 1) aoseas Pin Assignment Pin Functions DIP32, SOP32 AO to A16 ‘Address Input we pal 1° [or Output enatie input nul Bales oH a (| [eel we [cE Chip eae input oo Eas as [5] [ev] 40 1/01 to VO8 Data input/output fl fae] se Power supply Man fra] aca [eno Grong aa [o] [ea] 3E az [rol [es] A10 as [ty [ea] ce ao [xa] [aaj x00 i x03 [sa] [eo] 1707 x02 [ra] [z9] 106 ros [ial [ra] x08 ono [ie] 104 Top view sous No. 4711-2/10

LC338128P, M, PL, ML-70/80/10 $$ SsSseesesesseSeSSSSSSSSSSSSSSSSSse Function Logic [ ce [ cs [ oe [we | mri | aowoas Taowars [vorovos[ site t L H x VX vx OUT Read L x L x VX VX IN Write L H H x Vx x HZ TE only retresh L L x x x x HZ CS standby H x x x L x HZ Selt-refresh H x x x NP x HZ Auto-refresh Lo a eT stancy H: High-level Input of Viy = 6.5 V to Vj (min) . L: Low-level Input of Vixy = Vi, (max) to -1.0 V NP: Negatlve-polarity pulse input X: High: or low-level Input VX: "IN" when CE = L Is contirmed, then “x” HZ: High impedance IN: Input state OUT: Output state Specifications Absolute Maximum Ratings [Parameter Symon Ratings Ten Note] [ieuvotage ter a ET A [Atowabiepowerdsspaton i Pmt id [Ouputsroncurent tg mid [reraingtemperawerange iY tor oid i [Storage temperaturerange Tg Tetons | | Note: 1. Stresses greater than the above listed maximum values may result In damage to the device. DC Recommended Operating Ranges at Ta = 0 to +70°C [Parameter symbot mine max Tt TN [Svmpiyvotage oe fas so ss ['mputhighievelvokage Ty ees ve [Imputtow evetvorage Poe ve Note: 2. All voltages are referenced to GND. No. 4711-3/10

LC338126P, M, PL, ML-70/80/10 SSS [PaaS anions et] a a {average current during operation) cca | tao = tre (rin) cass time} 0ns_| ™ [toons [| 100 | Standby current 1 \\ CE-FFSH-v,, [eosserep.m Te ndby current = RFSH= CE-RFGH= — [Lossorzer.w [if Standby current 2 CE = FSI | ma renee ourent | vers CSM | RRSH=v [ucsserzerme [Tt TE=Vog-o2v, [toseereer.m [Tt ma femme feememeinme| eo [oe [oT [Seiputieakanecorent | ig, | Ouputasabe,0V=Van even | 0 | af af [Ouutrightevelvotage [Von [insta Tee TT [ouinutlowieveivotege | vo. [ius2tmA iT —SCSC*iT or vf | Note: 3. All current values are measured at minimum cycle rate. Since current flows immoderately, if cycle time is longer than shown here, current value becomes smaller. A bypass capacitor of 0.01 uF or larger should be inserted between Voc and GND for each memory chip to suppress power ‘supply noise (voltage drops) due to transient currents. 4. Dependent on output load. Maximum value is value during free state. Input/Output Capacitance at Ta = 25°C, Voc = 5 V + 10%, f= 1 MHz [arnt Stor [eas soaions [in [| [inwctcapactarce ROTOATS) |G [Mw eovSCdSSCSCSC*dCss da Input capaciiance (GE,CS,OE,AFSHandWE) | Gwe [Vngs0V TT [vOcapactance To |Mrov CC ‘Sampling inspections, and not full-lot inspections, are carried out for these parameters. pro to t00 Parmele i OO [Random readorwritecycietime [tac [nts [to Pte Ps | [Read-modiyawivcysetme | ww | 165 | | 95] | eos] __} ne [| [eEmisowan | toe | 70 | wooo | 60 | voo00 [100 | voo0o_| ns |_| [CE precrargetime tte as sos [CE accesstime ten Two t00 ns [Desccessime | toes | <i | «dT of oe [EE ouputenabictime tz feo os [CE outpuraisabieime tow [0 Pao Po as fo as 8 | [OE oupudsabeime | tog | 0 |» | 0 |e | o [| w | = | 0 | [WEodpaassseune | we | 0 | [0 |= [0 | | m= |_| [onpseecseupine | eas | 0 || 0 |_| 0 [Js] [cp ssecthowtine | tesu_| is || se || asp ie [Wate pusewan | tye to | | of «dr |r | id [Wie commancraiine | wen | 88 | 10000 [| 60 | voo00 | 70 | ooo | r= | | [Weie commandiesasme | tom | «0 | 1000 | 60 | 0000" | 70 | 10000 | me |_| [inutcstascupine WE | tpg | 20 | [35 || |_| =] w_| Continued on next page. No. 4711-4/10

LC338128P, M, PL, ML-70/80/10 Continued from preceding page. seme a put ata Paid ne fo WE [oe [oe | [_e} | o | [= | «| Input data hold time for CE [tow [oo Pe so Address hold time tor CE [wo fs [Teo Pass Rosh conmandhodine |e | 8 | | s | is | ds Auto-etresh cycie time [to [ss PT 30 tes FSH delay te for CE [eo [as [Po os FFSH precharge CE detay time tl (selt-refresh) IFRS Reteshtime (GrZcyeles,AOtOAB) | tee [fe [Te Ps os Note: 5, To accomplish internal initialization, CE Is fixed at Viy_ for an interval of 1 ms when Vgc reaches the specified voltage after power is switched on. At least eight cycles must be executed following that period. 6. Measured at ty = 5 ns. 7. When measuring input signal timing, Vij (min) and Vj, (max) are reference levels. 8. Measured using an equivalent of 100 pF and two standard TTL loads. 9. touz: tonz and twxz are defined as the time until output enters the open circuit state and the output voltage level becomes immeasurable 10.As with ordinary static RAM, write data is incorporated at the rise of WE input or CE input, whichever is earlier, and write data is therefore held during tow. tose: tow: OF toc: 11.Because address input is incorporated at the fall of CE, the address is maintained during tagc OF tay: 12.Auto-retresh and self-refresh are determined by RFSH pulse width when CE = Vi, and are defined as auto-refresh when below trap (max), or as self-reftesh when above tgag (min). In order to activate CE atter the completion of each refresh, tece must be assured for auto-refresh, or teas must be assured for selt-refresh. ‘Similarly, if self-refresh timing (RFSH = Low) is used after power is switched on, tzag must be assured. No. 4711-5/10

. LC338128P, M, PL, ML-70/80/10 Timing Chart Read Cycle = TTT i. MM ws ESS LL MU LALLLLLL LILLY eT og = | ae wwe YO eS s Hort (OOH : INVALID DATA Write Cycle 1 (OF Fix High) cs TT ALLL LLL ULL wn “LDL XODTTTTTTTTT TTPO tov [ps tee The,

LC338128P, M, PL, ML-70/80/10 Write Cycle 2 (OE Clock) tec _. toe te va — vn — fr tess vam = LLL) | LILITITLLLTITTILLLLLLLT 117 tasc| | cane _ ie soon TTT MOTTA Fa : ) ered] | ewcn | TOS a A 18 po ON ve Hp ee) al a, tH" of *L" EXXR : INVALID DATA Write Cycle 3 (OE Fix Low) tac toe _e — Yirn— se Vin. , seos_| | ecsn va os! ey LLLT/T) | IILLLLTILLLILLILLLILLLT TL EASC| tAHC _ oARh tee voone ee LLIN 288° MITT. come ve a 7 ] tose a a "Fee tFRS. RHC il tAFO rH" orl ERR : INVALID DATA No. 4711-7/10

LC338128P, M, PL, ML-70/80/10 Read-Modify- Write Cycle te — ee | cE view — | _ OY “ w ITLL, LILIIELLLETTEEP PIPETTE vem COTTON NLIITITITLLLIL LL TUTTLE wee a — eT Ses a oH or“L" (RX : INVALID DATA CE-Only Refresh Cycle a ee] “ * TITTLE TTT TUTTE we v0 LLLTIX = XLII TLE EIEIO TEPTETELED Note: A9 to A16:“H" or “L” SH" or"L

LC338128P, M, PL, ML-70/80/10 Auto-Refresh Cycle =e VIH— RHC. vn — ae ‘I i ae aFER vin — You — Ot to 08 High impedance Vou — Note: CS, OE, WE, AO to A16: *H™ of “L” ao1g38 Self-Refresh Cycle _ vin es io vu tRFD tre teas teas | | tanc — =VIK— aren vu — You — ; vorwes ya High impedance Note: CS, OE, WE, AO to A18:“H' or 1" potauo CS Standby Mode enc t sess| | ecst YIH— | You — . vor mies yo) High imp tanc $$ sores Note: OE, WE, AO to A16:"H" or “L" Hort" No. 4711-9/10

LC338128P, M, PL, ML-70/80/10 @ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. lm Anyone purchasing any products described or contained herein for an above-mentioned use shall: © Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and alll their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @® Not impose any responsibility for any fault or negligence which may be cited in any such claim or iitigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees | jointly or severally. | i Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for ! volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties i This catalog provides information as of May, 1996. Specifications and information herein are subject to change without notice. eee No. 4711-10/10