LC331632M-70 SANYO | Alldatasheet

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m7 512 K (32768 words x 16 bits) Pseudo-SRAM Preliminary Overview Package Dimensions The LC331632 series is composed of pseudo static RAM —_ unit: mm that operate on a single 5 V power supply and are 3495-SOP40 organized as 32768 words x 16 bits. By using memory cells each composed of a single transistor and capacitor, [LO331632M] together with peripheral CMOS circuitry, this series 26.20 achieves ease of use with high density, high speed, and ‘PARRARRAARARARAARRAY| low power dissipation. The LC331632 series can easily r _— q accomplish auto-refresh by means of LOE/RFSH input. 1. The available package is the 40-pin SOP with a width of { 525 mil. i | peuRUGuHHEEGaoH ae vay 5 Features : a | + 32768 words x 16 bits configuration Tho + CE access time/OE access time/Cycle time/Current q dissipation SANYO: SOP40 [a ee | GEaccesstme Tongs ens toons tz [OEeccesstime Tans Poms | Soms | [yee tn tans gong tons | Current dissipation * Single 5 V +10% power supply * All input and output (I/O) TTL compatible + Fast access time and low power dissipation * 4ms refresh using 256 refresh cycles + Supports CE-only refresh and auto-refresh * Supports byte unit read and write operations using the LOE/RFSH and UOE inputs or the LWE and UWE inputs. * Package SOP 40-pin (525 mil) plastic package: LC331632M SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 62096HA (OTY/61094TH/92093)N No. 4541-1/9

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, sae Column | Sense emaiior 225 8 AtaioAa [7 >} address | ‘oat 46 283 a} 2 butter(7) be L 8 ead] => Row address [ee ae 3 ATIOAO a 6 = [> butter (8) |= s Fol Memory coll array ry 388 14 ass LA $ 5 @ Refresh g 8X16 oeeretn, firey ex i 8 | 538 Ke e aes 2 | sae i] = Clock aij Refresh 32 CE O BP controller 8 8 LOE/AFSH © ro 5 ~28 ast P Re rt) S38 d Se [is WE O 4 _) we o—f{_) WE 0 {) Aowse7 Pin Assignment Pin Functions sOP40 [CWE _—_—=«d|-_ Lower byte wre enable Input Upper byte write enable Input GNOCT 1 40 F Vee LOE/AFSH Lower byte output enable Inpul/refresh Input ast] 2 39 [7 Owe Upper byte output enable Input sec] 3 ae Eine hip nab np a7C] 4 37 Ey asto VO1 to VOB Lower byte data Inpuvoutput ast 5 36 ass Upper byte data Inpuloutput ees a — Power supply Mo? ee a a3C7 6 a3) a14 azt] a 32 [9 U0E At [10 34 [7 LOE/AFSH Ao to 44 30 FO te Tvoi1 (oj 12 29 FJ 17016 Ivo2 (1) 13 26 17015

1703 C7] 14 27 [J 17014

1704 Cj 18 26, 7) 17013

r705 Cj 16 25 [7 Ivote 1706 (J 17 247 170it

1707 Cj ia 23 17010

1708 (J 19 22 [J 1/09 GND (J 20 21 Vee Top view a01se8 No, 4541-20

L.C331632M-70/80/10/12 SSS Functional Logic | | res | ome | eve | ome [own [owon] star [ole | om | SS L L L H VX VX OUT ouT Read (word) L L H H VX VX OUT HZ Read (lower byte) L H L H VX VX HZ OUT Read (upper byte) Lt L L VX VX IN ‘Write (word) t L H VX Vx IN Write (lower byte) L H L VX VX HZ Write (upper byte) [ee [enya i OS H: High-level input of Viy = 6.5 V to Vi (min) L: Low-level input of Vix = Vy (max) to ~1.0 V X: High: of low-level input NP: Negative-polarity pulse input VX: “IN" when CE = L Is confirmed, then “X" HZ: High impedance IN; Input state OUT: Output state Specifications Absolute Maximum Ratings a [Maximum suppW vonage | Vegmex | tower Sid Sv Td EZ A a 7 TE A [Atowabiepowerdaspaton | oman | SC*dC wid i [Sreatngtenperarerange SY toe «COC [Storasetemperaweranmge Yt «|B iso PS Cd d Note; 1. Stresses greater than the above tisted maximum values may result in damage to the device. DC Recommended Operating Ranges at Ta = 0 to +70°C a [Poversumpivoiwge SL Mec das | so] ts | Pd [put rignlevelvokege iY |e | SS ts | ed [rowtowieeivouse YY ef SCP oe | de Note: 2. All voltages are referenced to GND. [Paras Smtr [erties in [ma ot | [rons |_| 100 | Operating current \\ tae = tac (mi Access ime [20rs | [90 | 3.4 (Average current during operation) | CCA | !RO= te (min) [i0ons} | vs‘ , [wors[ [6s | [Standby curents | ccs) | CE=LOEAFSH=Vye CTS | ma | [Stoetycuren'2 | teose | CE + LOEFSH=Von-a2v————SC~d Sd | mm |_| [Inputleakage cuvent |, [OV sViveVco.pins other than measuringpinsov | -10 | +10 | vA | | [ouutteakage cure | tox | Ouputdsabe.0V=VoursVeg———SS*dY =f | 0 | va |_| [uputnigntevelvotage | Vor [lon=tma_ SS SSCSC~S aw | [Oupuiowevervorage | Yo. [lonssamaSSSC~wCSC‘id Ow PY Note: 3. All current values are measured at minimum cycle rate. Since current flows immoderately, if cycle time is longer than shown here, current value becomes smaller. A bypass capacitor of 0.01 wF or larger should be inserted between Vg and GND for each memory chip to suppress power ‘Supply noise (voltage drops) due to transient currents, 4, Dependent on oulput load. Maximum value Is value during free state. No. 4541-3/9

Input/Output Capacitance Characteristics at Ta = 25°C, f = 1 MHz, Vcc = 5 V + 10% ee ee [imput capacitance AdIOANA) TGs sov TO [Input cepactiance (CE,LOEAFSH,UOE CWE. UWE) [Gwe [Vme-ov [Tr nC Sampling inspections, and not ful-lot inspections, are carried out for thase parameters, a | em mee ae et met | OO | oe | [Randonreasorwiegeeime [me [ms | | wo | [io | [20 | | | | [OE pues | toe | 70 | vom | 00 | 0000 | s00 | 10000 | r20_| voone | ns |_| [CEnecraceime | tw | os ff of |] |p | [BEecousine cea | | ef] mt eee [CE ouiputenadietime tae | oo [PP oe Po Ts [COE WOE ouputenaieime [oz |e | |_| o |} oe | [| | [Eoupuasaveie [tox | 0 | | o | a[o | | 0] sf = | «| [TOE WOE oupuasatioime [tow |e | | o | as{o | of o| [| 0 | |Readcommandsetwptime | acs | O [ To P| oe Po fs [Resa conmanareine [wen |e | | 0 | [0 |} 0 | fs |_| [wite commandrogwne [won | | | eo | [os | | [= |_| [input cata sewp ime torEWE OWE | tosw [2s [| m0 || es |] > | |» |_| [ImputdatahoidimetortWEUWE | tow | 0 [ [oo [| fo | fo [ns [ot | [Address sewpimeforce | usc | of fo {| oe Pe Ps [Auoretesnayee ime [we | ms || mo | [wo | | 20 | fs |_| [FSH pssewaiharoveres | tear | 75 | oooo | eo | 000 | eo | ooo | eo | ooo} ms | | FSH active CE delay time lmwoaaran [wee | os || [fw | fs | [fe | [Retesnime ee | | ft af | [asso <i y | s[ »[ s][ »] s| | s][ [=] | Note: 5. To accomplish internal initialization, CE and LOE/RFSH are fixed at Vi, for an interval of 1 ms when Vic reaches the specified voltage after power is switched on. At least eight dummy cycles must be executed following that period. 6. Measured at ty = 5 ns. 7. When measuring input signal timing, V4 (min) and Vj__ (max) are reference levels. 8. Measured using an equivalent of 100 pF and two standard TTL loads. 9. COE/RFSH input tunctions as tower byte output enable input (COE) when CE = Vi, and as refresh input (RFSH ) when CE = Viy. 10. toyz and toyz are defined as the time until output enters the open circuit state and the output voltage level becomes immeasurable. 11. As with ordinary static RAM, write data is incorporated at the rise of LWE, UWE input or TE input, whichever is earlier, and write data is therefore held during togw. tpsc; tpHw: OF tone: 12. Because address input is incorporated at the fall of CE, the address is maintained during tag¢ oF tanic 13. After auto-refresh has completed, CE must not be made active until the tece period has elapsed. No. 4541-4/9

Read Cycle (word) tac ee es asc fomase nT CX WALLET LLL LLL LLL foun PT Ea tach nu tonz vosre1ore |" ee __vew four W270: "W or “L” QQXY: INVALID DATA aoisee Read Cycle (lower byte) tac oe Sasc roware DR 8§ MTT TLL TTT 11 : I Es rreton a) | a VIH— f—f woe Une Vin— Vu vostovore fe a sa etance You— QZZ2: “H” of “L" RAM: INVALID DATA Ao1s90

Read Cycle (upper byte) trac eo tasc smh hws WALTELTETTLTLTLALLIL EULA L LL | __[Eone YIL— : i | a Yu vortovos “OH High impecance | = fone oe 1 — Sez UZZA: “H" or “L” QXXH: INVALID DATA aorsas Write Cycle (word) tac own Oh a ROLLE TLL LELLLL ELS ELLE VIL me TN / pe ven — rvs (SoS Yxu— tose es Yu tow phy Yiu soisee No. 4541-6/9

Write Cycle (lower byte) tre ae [as tasc rowan ON TELL TLL LTE ELL Yu ine worst Yn (en YIL— a woe NT oe VINO vn vos vores Ve peace You— UZZA: “H" 0 “L" Write Cycle (upper byte) tre toe te a YIH— fowan Oo NELLIE LLELELT LS ELE TELL Vi tach ° = | Yiu. vortovos YOK High impedance You woe 0 tc | Yu tewe an tosm | |__ [ton rroron a Vit sosses No. 4541-7/9

va LLL) ST// [/ tosc tone ee yaeee |OVIK— TOE AF EH VIL: trcs tRCH tre YVIH— YL vortovos “Or Hign imcecance You tose tone, woe VIK— | woE Yr tacs tacn se (YIN owe Yu vostovors ee sl ae gance Yor— Note: A8 to Al4 = "H" or “L” QZ7A: “H" or “L" horses Auto-Refresh Cycle = VIH oF vn treo tec tece trap trp trap vu * d Vou— Vor 10 VOR ee epegance Yo.— Vou— YOR 10 VO es peconce Vor— Note: AO Al4, UOE, CWE, UWE =~H” or “L” ZA: “Ht or “L” Aosses

a eeeeSSSSSSSSeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSE m@ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss

1 Anyone purchasing any products described or contained herein for an above-mentioned use shall:

® Accept full responsibility and indemnity and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. lm Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1996. Specifications and information herein are subject to change without notice. ee No. 4541-9/9