LC321664AJ SANYO | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 30
Technical content
Features
- 65536-word · 16-bit configuration
- Single 5 V ±10% power supply
- All input and output (I/O) TTL compatible
- Supports fast page mode, read-modify-write, and byte- write.
- Supports output caching control using early write and Output Enable (OE) control.
- 4 ms refresh using 256 refresh cycles
- Supports RAS-only refresh, CAS-before-RAS refresh and hidden refresh.
- Packages SOJ 40-pin (400 mil) plastic package: LC321664AJ SOP 40-pin (525 mil) plastic package: LC321664AM TSOP 44-pin (400 mil) plastic package: LC321664AT
- RAS access time/column address access time/CAS access time/ cycle time/power dissipation Package Dimensions unit: mm 3200-SOJ40 unit : mm 3195-SOP40 SANYO:SOJ40 [LC321664AJ] SANYO:SOP40 [LC321664AM] LC321664AJ, AM, AT-80 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
1 MEG (65536 words · 16 bits) DRAM
Fast Page Mode, Byte Write CMOS LSI Parameter LC321664AJ, AM, AT-80 RAS access time 80 ns Column address access time 45 ns CAS access time 30 ns Cycle time 135 ns Power dissipation During operation 633 mW (max.) During standby 5.5 mW (CMOS level)/11 mW (TTL level)
LC321664AJ, AM, AT-80 No. 4795-2/30 Package Dimensions unit : mm Pin Assignments 3207-TSOP44 [LC321664AT] SANYO:TSOP44 (TYPE-II)
LC321664AJ, AM, AT-80 No. 4795-3/30 Block Diagram Specifications Absolute Maximum Ratings Parameter Symbol Ratings Unit Note Maximum supply voltage VCC max –1.0 to +7.0 V 1 Input voltage VIN –1.0 to +7.0 V 1 Output voltage VOUT –1.0 to +7.0 V 1 Allowable power dissipation LC321664AJ, AM Pd max 800 mW 1 LC321664AT 700 Output short-circuit current IOUT 50 mA 1 Operating temperature range Topr 0 to +70 °C 1 Storage temperature range Tstg –55 to +150 °C 1 Note: 1)Stresses greater than the above listed maximum values may result in damage to the device. DC Recommended Operating Ranges at Ta = 0 to +70°C Parameter Symbol min typ max Unit Note Power supply voltage VCC 4.5 5.0 5.5 V 2 Input high level voltage VIH 2.4 6.5 V 2 Input low level voltage (A0 to A7, VIL –1.0* +0.8 V 2RAS, CAS, UW, LW, OE) Input low level voltage VIL –0.5* +0.8 V 2(I/O1 to I/O16) Note: 2)All voltages are referenced to VSS . A bypass capacitor of about 0.1 µF should be connected between VCC and VSS of the device. * –2.0 V when pulse width is less than 20 ns
LC321664AJ, AM, AT-80 No. 4795-4/30 Parameter Symbol Conditions min max Unit Note Operating current ICC1 RAS, CAS, address cycling: 115 mA 3, 4, (Average current during operation) tRC = tRC min 5 Standby current ICC2 RAS = CAS = VIH 2 mA RAS-only refresh current ICC3 RAS cycling, CAS = VIH: 115 mA 3, 5tRC = tRC min Fast page mode current ICC4 RAS = VIL, CAS address cycling: 70 mA 3, 4, tPC = tPC min 5 Standby current ICC5 RAS = CAS = VCC –0.2V 1 mA CAS-before-RAS refresh current ICC6 RAS, CAS cycling: 115 mA 3tRC = tRC min Input leakage current IIL 0V ≤ VIN ≤ 6.5V, pins other than–10 +10 µAmeasuring pin = 0V Output leakage current IOL D OUT disable, –10 +10 µA0V ≤ VOUT ≤ 5.5V Output high level voltage VOH IOUT = –2.5mA 2.4 V Output low level voltage VOL IOUT = 2.1mA 0.4 V Note: 3)All current values are measured at minimum cycle rate. Since current flows immoderately, if cycle time is longer than shown here value becomes smaller. Note: 4) ICC1 and ICC4 are dependent on output loads. Maximum values for ICC1 and ICC4 represent values with output open. Note: 5) One address change can be performed while RAS = VIL(ICC1 and ICC3 ). One address change can be performed during one tPC cycle (ICC4 ).
LC321664AJ, AM, AT-80 No. 4795-5/30 Parameter Symbol min max Unit Note Random read or tRC 135 nswrite cycle time Read-write/read-modify-write tRWC 180 nscycle time Fast page mode cycle time tPC 55 ns Fast page mode Read-write/read-modify- tPRWC 100 ns write cycle time RAS access time tRAC 80 ns 9, 14 CAS access time tCAC 30 ns 9, 14 Column address access time tAA 45 ns 9, 15 CAS precharge access time tCPA 50 ns 9 Output low-impedance tCLZ 0 ns 9time from CAS low Output buffer turn-off delay timetOFF 0 20 ns 10 Rise or fall time tT 3 50 ns RAS precharge time tRP 45 ns RAS pulse width tRAS 80 10000 ns RAS pulse width for tRASP 80 100000 nsfast page mode only RAS hold time tRSH 30 ns CAS hold time tCSH 80 ns CAS pulse width tCAS 30 10000 ns RAS to CAS delay time tRCD 25 50 ns 14 RAS to column address delay timetRAD 17 35 ns 15 CAS to RAS precharge time tCRP 10 ns CAS precharge time tCP 10 ns Row address setup time tASR 0 ns Row address hold time tRAH 12 ns Column address setup time tASC 0 ns Column address hold time tCAH 20 ns Column address hold time tAR 60 nsreferenced to RAS Column address to RAS lead timetRAL 45 ns Read command setup time tRCS 0 ns Read command hold time tRCH 0 ns 11referenced to CAS Read command hold time tRRH 0 ns 11referenced to RAS Write command hold time tWCH 15 ns Write command hold time tWCR 60 nsreferenced to RAS Write command pulse width tWP 15 ns Continued on next page.
LC321664AJ, AM, AT-80 No. 4795-6/30 Continued from preceding page. Parameter Symbol min max Unit Note Write command to RAS lead time tRWL 20 ns Write command to CAS lead time tCWL 20 ns Data input setup time tDS 0 ns 12 Data input hold time tDH 20 ns 12 Data input hold time tDHR 60 nsreferenced to RAS Refresh period tREF 4 ms Write command setup time tWCS 0 ns 13 CAS to UW, LW delay time tCWD 50 ns 13 RAS to UW, LW delay time tRWD 100 ns 13 Column address to UW, LW tAWD 65 ns 13delay time CAS precharge to UW, LW delay tCPWD 70 ns 13time (fast page mode cycle only) CAS setup time for tCSR 10 nsCAS-before-RAS refresh CAS hold time for tCHR 15 nsCAS-before-RAS refresh RAS precharge time to tRPC 10 nsCAS active time CAS precharge time for tCPT 40 nsCAS-before-RAS counter test RAS hold time referenced to OEtROH 15 ns OE access time tOEA 25 ns 9 OE delay time tOED 15 ns OE to output buffer turn-off tOEZ 0 15 ns 10delay time OE command hold time tOEH 20 ns Data input to CAS delay time tDZC 0 ns 16 Data input to OE delay time tDZO 0 ns 16 Masked write setup time tMCS 0 ns Masked write hold time tMRH 0 nsreferenced to RAS Masked write hold time tMCH 0 nsreferenced to CAS Input/Output Capacitance at Ta = 25°C, f = 1 MHz, VCC = 5 V ± 10% Parameter Symbol min max Unit Input capacitance C IN 7 pF(A0 to A7, RAS, CAS, UW, LW, OE) I/O capacitance (I/O1 to I/O16) C I/O 7 pF
LC321664AJ, AM, AT-80 No. 4795-7/30 Notes: 6) After the power is turned on, 200 µs are required after the arrival of VCC stabilized current before memory is initialized and begins operation. In addition, before memory operation initializes, approximately 8 cycles worth of RAS dummy cycles are required. When the on-chip refresh counter is applied, approximately 8-cycles worth of CAS-before-RAS dummy cycles are required instead of the RAS dummy cycles. 7) Measured at t T = 5 ns. 8) When measuring input signal timing, VIH (min) and VIL (max) are used for reference points. In addition, rise and fall time are defined between VIH and VIL. 9) Measured using an equivalent of 50 pF and one standard TTL load. 10) tOFF (max) and tOEZ (max) are defined as the time until output voltage can no longer be measured when output switches to a high impedance condition. 11) Operation is guaranteed if either tRRH or tRCH are satisfied. 12) These parameters are measured from the falling edge of CAS for an early-write cycle, and from the falling edge of UW and LW for a read-write/read-modify-write cycle. 13) tWCS , tCWD , tRWD , tAWD and tCPWD are not restrictive operating parameters for memory in that they specify the operating mode. If tWCS ‡ tWCS (min), the cycle switches to an early-write cycle and output pins switch to high impedance throughout the cycle. If tCWD ‡ tCWD (min), tRWD ‡ tRWD (min), tAWD ‡ tAWD (min) and tCPWD ‡ tCPWD (min), the cycle switches to a read-write/read-modify-write cycle and data outputs equal information in the selected cells. If neither of the above conditions are satisfied, output pins are in an undefined state. 14) t RCD (max) does not indicate a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRCD ‡ tRCD (max), access time is determined according to tCAC . 15) tRAD (max) does not indicate a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRAD ‡ tRAD (max), access time is determined according to tAA . 16) Operation is guaranteed if either tDZC or tDZO are satisfied.
LC321664AJ, AM, AT-80 No. 4795-8/30 Timing Chart Read Cycle
LC321664AJ, AM, AT-80 No. 4795-9/30 Early Write Cycle
LC321664AJ, AM, AT-80 No. 4795-10/30 Upper Byte Early Write Cycle
LC321664AJ, AM, AT-80 No. 4795-11/30 Lower Byte Early Write Cycle
LC321664AJ, AM, AT-80 No. 4795-12/30 Write Cycle (OE Control)
LC321664AJ, AM, AT-80 No. 4795-13/30 Upper Byte Write Cycle (OE Control)
LC321664AJ, AM, AT-80 No. 4795-14/30 Lower Byte Write Cycle (OE Control)
LC321664AJ, AM, AT-80 No. 4795-15/30 Read-Modify-Write Cycle
LC321664AJ, AM, AT-80 No. 4795-16/30 Read-Modify Upper Byte Write Cycle
LC321664AJ, AM, AT-80 No. 4795-17/30 Read-Modify Lower Byte Write Cycle
LC321664AJ, AM, AT-80 No. 4795-18/30 Fast Page Mode Read Cycle
LC321664AJ, AM, AT-80 No. 4795-19/30 Fast Page Mode Early Write Cycle
LC321664AJ, AM, AT-80 No. 4795-20/30 Fast Page Mode Upper Byte Early Write Cycle
LC321664AJ, AM, AT-80 No. 4795-21/30 Fast Page Mode Lower Byte Early Write Cycle
LC321664AJ, AM, AT-80 No. 4795-22/30 Fast Page Mode Read-Modify-Write Cycle
LC321664AJ, AM, AT-80 No. 4795-23/30 Fast Page Mode Read-Modify Upper Byte Write Cycle
LC321664AJ, AM, AT-80 No. 4795-24/30 FastPage Mode Read-Modify Lower Byte Write Cycle
LC321664AJ, AM, AT-80 No. 4795-25/30 Hidden Refresh Cycle
LC321664AJ, AM, AT-80 No. 4795-26/30 RAS-Only Refresh Cycle CAS-Before-RAS Refresh Cycle
LC321664AJ, AM, AT-80 No. 4795-27/30 CAS-Before-RAS Refresh Counter Test Cycle (read)
LC321664AJ, AM, AT-80 No. 4795-28/30 CAS-Before-RAS Refresh Counter Test Cycle (write)
LC321664AJ, AM, AT-80 No. 4795-29/30 CAS-Before-RAS Refresh Counter Test Cycle (read-modify-write)
LC321664AJ, AM, AT-80 PS No. 4795-30/30 This catalog provides information as of March 1996. Specifications and information herein are subject to change without notice. n No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n Anyone purchasing any products described or contained herein for an above-mentioned use shall: À Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: \` Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.