LC3101

LC3101 SANYO | Alldatasheet

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© ROM capacity 128K bits © Access time 25.6ysec typ {for operation at 200kHz typ.) © Cycle time 30.6usec typ (for operation at 200kHz typ.) © Function (1) Contains an interface to an EPROM. (2) Contains an interface to the LCB100 (speech synthesizer LS!). (3) Possible to select the bit length of output data. - Bbit data 4-bit data Single-bit data @ Low power dissipation CMOS © Current dissipation 2mA max, (at operating mode) 1A max. (at nonoperating mode) @ Single +5V power supply: +2.7 to 6.0 V (supply voltage range) © Package DiP24 Pin Assignment Package Dimensions 30144-D42IC (unit: mm) a 2 ----- rar ae Eo [7] fd EAI7 ———= ty eal (2) a EA a 2 fd EAS 39.2 : a3 Gi] ii EAM = &™ Gi) me “ ove (7 }) COUT 5 ose. a {5) OREO do fa) ASTRB oO [Ao SANYO: DIP42 nc fat . . we a 1 Az Package Dimensions 3025B-D42SIC

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Equivalent Circuit Block Diagram _ ADtoA3: 18-bit address setting pins a a as ASTRB: AO to A3 strobe pin : DREQ: ROM data request pin DOUT: ROM data serial output pin | cT: Basic operation clock input pin asta 5 alrtose count] DO to D7: 8-bit input/output pins ° MODE: DREQ pin input pulse count control pin asta i f° DSEL: Output bit length select pin se i = t a a CE: Power-down control pin | EAO to EA17; 18-bit address output pins #00) | | | ROM matrix qa} ; conn : § vo 7] ODSEL, ott SETA 8-8 Description of Operation of Internal Block @ ASTRB COUNTER: Block which internally sets address information applied in 5 steps from AO to A3 pins. © 18bit ADDRESS COUNTER: Address counter organized with 18 bits. @ READ PULSE COUNTER: Block which generates signal to operate address decoder, data selector. © CHIPSELECT DECODER: Makes chip select signal with 214 to 217 bits of 18-bit address. ®@ 128kbit ROM MATRIX: ROM matrix cell organized with 128K bits. @ PARALLEL TO SERIAL: Shift register which serially outputs 8-bit parallel data to DOUT pin. @ t/O PORT: Selects input/output at DO to D7 pins. Pin Description Troe [rie [ween [am ASTRB Pin for inputting strobe signal which causes data AO to A3 to be latched at address setting mode. DOUT Pin for outputting ROM data serially. When used in conjunction with the LC8100, this pin is connected to DIN pin of the LC8100, 37 cT Input Pin for inputting basic operation clock of ROM inside, When used in conjunction with the LC8100, this pin is connected to CT pin of the LC8100. No1542-2/14

a eeeSSSSSSSSSSSSSSSSSSssssSSsSSSeee a cE Input Pin for controlling initialization of LSI inside imme- diately after application of power and internal operation stop (power-down). For performing synthesization or ROM data read-out, set CE to

7 MODE Pin for controfling number of input pulses at DREQ

pin. When ROM data read-out is performed serially in a single bit, set MODE to ‘L’, When ROM data read-out is performed in 8 bits or 4 bits, set MODE to DSEL Input Used when ROM data read-out is performed in 4 bits. When DSEL is set to ‘H’, 24 to 27 bits are outputted to DO to D3 pins. | eo | po | Pins for outputting ROM data in 8 bits and inputting a a data in 8 bits. a a a | 13] Input/output [is {6 : Pins for setting 18-bit address, At address setting } 3rs—i‘dE:‘C‘(SC<(CMA2C;‘dS Input mode, address information is inputted by 4 bits ee ee from high-order bit downward in 5 steps. ps | 1 | cao | Output 18-bit address output pins. ee ee a | ee a | 20 TAT ee ee | | 23 EAI a 2 [26 | EAT2 | 26 EAN ; a re [aa EA I7 eee N01542-3/14

es SSS, How to use the mask ROM and an EPROM jointly The mask ROM and an external EPROM can be used jointly. Two selections of operation mode shown below are available by high-order 4 bits (EA14 to EA17) of 18-bit address, (Operation Mode Pins[DOto D7 [| [ (1) ~____[Qutput__| The mask ROM contents are delivered at pins DO to D7 and DOUT. Input The EPROM output contents are read in from pins DO to D7 and are delivered at pin DOUT, How to select the operation mode The LC3101 contains a 4-bit chip select decoder (user option: Refer to“User mask’). Coincidence or uncoincidence with high-order 4 bits (EA14 to EA17) of 18-bit address is detected to select the operation mode. Operation Mode Abits of Chip Select Decoder Operation of LC3101 4) Coincidence with EA14 to EA17 Pins DO to D7: Output mode Mask ROM read enable mode 2) Uncoincidence with EA14 to EA17 | Pins DO to D7: Input mode Mask ROM read inhibit mode Fig. 1 shows the schematic diagram of the control section related to these operation modes. Fig. 2 shows the assign- ment of 256k-byte {128k bits x 16) that can be specified by 18-bit address. Fig. 1 Schematic Diagram of Control Section GAOWAS 7M ad i “ EAQ-EAI7 ‘ te address decoder <j 128kbit masked ROM Fig. 2 Address Space Assignement SYA en Midd OFFFF 10600 1BFFF 128k bits < specified for select al decoder. q T8600 ‘Som ‘% i 3BFFF | . Fc000- Texbye] | eee Ne1542-4/14

ROM Data Read-out Procedure The following flowchart shows the outline of read-out procedure, (1) to (7) give a more detailed description. Application of power (1) Initialization of internal mode (CE='H') {2) Setting of bit length of read-out data {3) Address setting EA14 to EA17: High-order 4 bits of 18-bit address Coincidence of EA14 No to EA17 with chip select decoder contents? js EPROM data inputted from pins DO (4) Output data is fetched from to D7 are delivered at pin DOUT. DOUT or DO to 07. This date are fetched.” Does ROM data read-out continue? NO Does standby continue et ves Power-down mode? NO (5) Is data at immediately YES following address read? YES (6) Data request signal is applied on, No date request signal is sent. (1) Initialization of internal mode There are 4 counter blocks (ASTRB counter, 18-bit ADDRESS counter, READ PULSE counter, DREQ counter) inside the LC3101. Since initialization is required immediately after application-of power, apply one ‘H’ level pulse to CE pin. When CE is set to’’L’ level, the power-down mode is released (refer to {7)) and it is possible to start read-out any time. (2) Setting of bit length of read-out data For the bit tength of ROM data output, a selection of 3 lengths is allowed: 8 bits, 4 bits, and a single bit. For controlling this selection, MODE, DSEL pins are used. The following Table shows 3 types of pin setting. eee No1542.5/14

“Lt Single-bit length 8-bit or 4-bit length or (speech synthesis) 4-bit length (Note) (Note) When DSEL is set to ‘L', 20 to 23 bits are outputted at DO to D3 pins. When DSEL is set to ‘H’, 24 to 27 bits are outputted at DO to D3. pins. (3) Address setting Apply 5 successive pulses to ASTRB pin. Synchronously with these pulses apply 18-bit address information to AO to A3 pins from high-order bit downward by 4 bits in 5 steps. At this address setting mode DREQ pin must be set to ‘L’ level. Shown below is the timing. RELG! 90% ASTRE TSTR TADST! [TapHO tdiress TL (Note) + **"=don’t care. + “20"=Binary number at the nth bit to be set in address counter. + For the numeric values of TST RH, TSTRL. TADST. TADHS. refer to Electrical Characteristics. Start of read-out of set address data Read-out of ROM data starts at the falling of the 5th ASTRB pulse or the first (MODE='H’) or the 8th (MODE='L’) DREQ pulse, and when access time Tact has elapsed 20 bit is outputted at DOUT pin and 20 to 27 data are outputted at DO to D7 pins. (Refer to the following Timing Chart.) Note) For the numeric value of Tac1, refer to Electrical Characteristics. “om row cour Wy J 507 toon 1) TR ono ou Wo1542-6/14

(4) Fetching of output data As shown above, whenever access time Tacy has elapsed, data can’ be fetched from output ports DOUT or DO to D7 pins. (Pin setting as shown in Table in (2) is required,) Counting one byte in a single bit from DOUT pin Count a single bit (29 bit) from DOUT pin. To count the following single bit (2"+7 bit), apply a shift clock to DREQ pin. Shown below is Timing Chart. For the numeric values of TAC1, TDRQH. TSHFT, refer to Electrical Characteristics. ASTRB(Sth) Dreatist or eth) 4.10% a Tart), 7 A Le ~ DOBQOO ‘30% i (shift clock) Abs Mow Ay, ror! TS tore | FS ozs 1 TORO + q TORO 1 2 7 Counting one byte in 4-bits from DO to D3 pins In accordance with Table and (Note) in (2), fetch one byte from DO to D3 pins by 4 bits in 2 steps. Shown below is Timing Chart. ASTRB(Sth) lowe bits higher 4 bits BREQ(Ist or 8th) renal _ $ ff FH 307. TIKI NOK: /) ] ) // ] 6

2 Hp ] i} yy V] i} (8)

0: TM i) 4 7] ae) DSEL 130% | Hose. eee . N1642-7/14

Counting one byte in 8 bits from DO to D7 pins Fetch 8 bits from DO to D7 pins, Shown below is Timing Chart. ASTRB(SIh) DREQ( Ist or 8th) owe A | | 30%, (P)

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FSO. 7 y) CP) (5) Setting address again and counting data (1) Timing for application of ASTRB pulse when address A is set and read out and then address B is set and read out. _——5th ASTRB pulse 5 azo ~~ 8 fb —Tact | 5 ASTRB 10% Low ra i pot UMM, SES VALID (B) 40-3 (3) XTX |) Xs) Teatess re WI) D ~ a) Address A setting Address B setting (2) Timing for application of ASTRB pulse when data is read out by application of DREQ signal (refer to (6) below) and then address B is set and read out. 1 57 Sth ASTRB pulse AT20 ASTRB I 10% 0% ortst 20-7 Teaser | tt WW ES WWW, SX ~ ane —— ie Cmeemee MMMM, a en . No1542-8/14

(6) Request of ROM data at the following address When the signal shown below is applied to the LS!, the LSI begins to read out data at the address immediately following the address at which preceding data is read out. Falling of 8th DREQ pulse (MODE='L’) Falling of 1st DREQ pulse (MODE="H’) Shown below is Timing Chart. TcyCLe: Tacn2y DRE ist or th) aka a a Bites SI | ——. | 90% al 20 oa ‘TTT 0 XT. vi prea | fos “0% AT=0 @ pulse (MODE - LY or 1 pase (MODE : H) Note) Apply ROM data request signal after TCYCLE or more has elapsed. For the numeric value of TCYCLE. refer to Electrical Characteristics. {7) Power-down mode When the input at CE pin is set to ‘H’ level, the LC3101 enters power-down mode (each block inside the LSI stops its operation, with no unnecessary current dissipated.). At this mode, the LSI inside becomes as follows and current dissipation is reduced, (1) Input at input ports (ASTRB, DREQ, AO to A3) is inhibited. (It should be noted that if input is floating, current dissipation increases.) (2) Both address decoder and data selector in 128K-bit ROM matrix stop their internal operation. (3) Output at 3-state output pins DOUT, DO to D7 is floating or fixed. (The user can select either of the two. Refer to “User mask"} When CE is set to ‘H’, in addition to reduction in current dissipation as mentioned above, 4 internal counters (ASTRB COUNTER, 18-BIT ADDRESS COUNTER, READ PULSE COUNTER, DREQ COUNTER) are initialized in readiness for read-out after power-down mode release (CE='L’). User mask (1) CHIP SELECT DECODER User mask option which makes LS! chip select signal (select, nonselect) with 214 to 217 bits of 18-bit addresses. Shown below is the output modes including CE pin conditions. Chip select DATA is outputted from DOUT, Data immediately before CE="H’ occurs DO to D7 pins. is held and outputted. (Note) Chip nonselect Output at DOUT, D0 to D7 pins Output at DOUT, DO to D7 pins has a high has a high impedance. impedance. Note) In this case, the LSI only, having CHIP SELECT DECODER whose 214 to 217 bits are all 0, outputs data and all others have a high impedance, eee No1642-9/14

(2) SW mask SW mask controls output at DOUT, DO to D7 output pins in the following two ways at power-down mode. The user can select either of the two beforehand. (i) Output at DOUT, DO to D7 pins is set to a high impedance. (ii) Data immediately before power-down mode is held and outputted. Sampte Application Circuit (1) One word to one key correspondence AHAOHH =e or vpp £68100 A 5 OSFRM ° 5 e—Ico 8 8 stow o c! FAST ° C2 voo L ch vss cs tilteramp sp START OA > {{| qe DIRECT a Reset |} CT loxe Eg 7 vooe O86 eggnba et 16 max Vono = {or open) \\\\ we 22822955 | {MODE 2 8 7 ve DSEL oa/at LC3101 Sample Application Circuit (2) CPU control: Edit and synthesis with CPU. ws (The mask ROM and a 64k-bit EPROM are used jointly.) fal al h itm [= 88 62g [ee ° © yoo a Pos vss lo titer ame od g es oat_T>-7 ae [ Istarr 22 tansy feseT| “Y 38 oe Ege 8 eeagkzr ge nt Ei il Lcb100 as LC3I01 a OSEL. es 28 : | ress .— ee EE 20max TSS oe cE 64kbit EPROM Ne1542-10/14,

oo eeeSSSSSSSSSSSSSSSsSsSssSSSSSSSSSSSSSSSFSSS Absolute Maximum Ratings at Ta=25°C, Vgs=0V . unit Maximum Supply Voltage Vpp max Vpp pin —3.0 to +7.0 v Input Voltage VIN All input pins ~0.3 to Vpp+0.3 v Output Voltage Vo All output pins -0.3 to Vppt+0.3 Vv Output Current fo All output pins, per pin —2,0 to +2.0 mA Allowable Power Dissipation Pq max Ta=—30 to +70°C 200 mW Operating Temperature Topr. —30 to +70 °c Storage Temperature Tstg —55 to +125 °c Allowable Operating Ranges at Ta=—30 to +70°C, Vss=0V, Vpp=4.5 to 6.5V min typ max unit Supply Voltage Vpp Vpp pin ‘ 45 5.0 65 Vv Input ‘H’-Level Voltage VIH(1) All input pins other than 0.7Vpp v DO to D7 Vin(2) DO to D7 pins 2.2 Vv Input ‘L’-Level Voltage ViL() All input pins other than 0.3VpD Vv DO to D7 Vit (2) DO to D7 pins 0.6 Vv Operating Clock Frequency fcT Fig. 1, Tg=—30 to +60°C 150 800 960 kHz Operating Clock ‘H’-Level twOH Fig. 1 03 us Pulse Width Operating Clock ‘L’-Level twOL Fig. 1 0.47 ps Pulse Width Electrical Characteristics at Tg=—30 to +70°C, Vpp=4.5 to 6.5V, Vgs=0V min typ) max unit Input ‘H’-Level Current 1H Vin=Vpp 10 yA Input ‘L'-Level Current YL VIN=Vss -1.0 BA Output ‘H’-Level Voltage VoH !oH=—-0.3mA Vpp-0.6 Vv Output ‘L’-Level Voltage VoL toH=0.3mA 0.6 Vv Output OFF Leak Current lOFF1 Vo=Vpp, DO to D7, DouT pin 1.0 BA lorrF2 Vo=Vss,D0toD7,DouT pin —-1.0 BA Input Pin Capacitance en 5 10 pF Pull-up Resistance Rup Each pin of MEP/EVA, 00/01 20 1000 kQ Current Dissipation Ipp(1} At operating mode, fcT=960kHz, Fig. 2 2.0 mA Ipp(2) At nonoperating mode, Tg=—30 to +50°C, 1.0 BA Fig. 2 AC Characteristics at Ta=~30 to +70°C, Vpp=4.5 to 6.5V, Vss=0V, RL=200kohm, CP=50pF min typ max unit Address Setup Time Tapst Fig. 3 0.3 US Address Hold Time TADHD Fig. 3 0.3 iy ASTRB ‘H’-Level Pulse Width TSTRH 03 us ASTRB ‘L’-Leve! Pulse Width TSTRL 03 us DREQ ‘H’-Level Pulse Width TDRQH 0.3 us OREQ ‘L’-Level Pulse Width TDROL 0.3 us ASTRB Pulse Duration TASTRB Fig. 3 1.5 us DREQ Pulse Duration =~ TDREQ Fig. 4 1.5 us ROM Data Access Time (1) Tact fCT=200kHz typ., Fig. 5, Note? 26.0 us ROM Data Access Time (2) Tac2 fCT=200kHz typ., Fig. 5,Note1 26.0 bs DREQ TO Dou Delay Time TSHFT Fig. 6 06 us DSEL TO DO-3 Delay Time TDSEL Fig. 7 03 us Cycle Time TCYCLE fcT=200kHz typ., Fig.8,Note1 30.6 us Ne1542-11/14

Fig. 1 Input waveform at CT pin . va o 30h » f 1 | i | tna ane 1a = — a ig ttt | tat +) Cee an Fig. 2 LO3101 Le3101 LC3101 AIT ) ) I) EAI? RB = BO D5 EAB D5 EAIS Ds EAN Ds Os EA DS EAM ° D3 EAS {D3 EAS [— D3 CEA pen 02 EAIZ D2 ANZ, Open 02 EAI DI EAN DI EAN DI EAI D0 EAIO Do EXO Do EAD EAS lnour FAS Open Ag out EAB Open] EA Dour EAs FAg{— | Open EAG gag {= jOpen EAS EAS EAS EAL AL EAL EA EA3 EAR EA2 EA? FAD EAY car EAL FAO FAO FAO MEP/EVA MER/EVA MeP/EVA oof MODE 00/07 if MoE oT DSEL cE MODE "ae ce DSeL aa 43 | AG A2 ct AZ i A2 AL 4 AY | ALL | AO AO | AQ) ) Lvoo__vss yob_vss | Lp_vss J 1 1@ ! hot Yoo Yoo Yoo Tp (1) Test Circuit (A) 101) Test Circuit (B) 1 00(2) Test Circuit Fig. 3 Fig. 4 Yoo: ———, 10% —~ ys = Cr _ via) Tapst TSTRH va) me vit) [v1 AO~AI i 5 data \\ WSs 10% TRL T_| YILO) "sod eee 1542-12/14

Fig. 5 (1) - ‘oo — ee TET) ASTRB 0% — viry vss —— thera! Y son NO bout y Ki | DATA VALIO ROM Data Access Time (1) Fig. 5 (2) Ist or 6th 10%. Wen = wt) Taca ima YO our 4), | _ DATA VALID Uy YUM, ff A ] Oe You Vey ROM Data Access Time (2) Fig. 6 Fig. 7 “ Ist 2nd on a ——— HD 0% Venn Rea One XN in vue) x ch | wt) i ohy TSH FT. | y oT) You 0 ! Yow ‘Do~03 Uf, YY DATAVALID ' You Fig. 8 REQ | | | ns an i (} Eos (} iy Vor D0~07 VALID VALID example of MOOE=H Note 1 Use the following formulas to calculate Tac max, Tcycle max. + _ 5000 . _ 6000 Tac max= Fetckuz) 10-6 Hs Teyele max FCT CkHTD *0.6 as eee Ne1542-13/14

J No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. HM Anyone purchasing any products described or contained herein for an above-mentioned use shall ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO. LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTO, its affiliates, subsidiaries and distributors or any of + their officers and employees jointly or severally. Mi Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. ¥o1542-14/14