LC01700PW

LC01700PW SANYO | Alldatasheet

Document overview

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Technical content

Features

• Dedicated FM tuner IC for VICS in Japan and RDS in Europe.
• Variable gain LNA incorporated.
• A pulse counter detection method employed in the FM detection circuit. No adjustment necessary.
• Less number of external parts.
• BUS control tuner IC enabling control with I2C BUS.
• OP AMP provided to adjust the composite frequency level appropriate to VICS and RDS.
• 6Bit-ADC incorporated to enable digital output of S meter. Functions
• FM-FE+IF+OP AMP+PLL Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage V DD max 6V Maximum input voltage V DD H 6V Maximum output voltage V DD L 6V Allowable power dissipation Pd max Ta ≤ 85°C 400 mW Operating temperature Topr -40 to +85 °C Storage temperature Tstg -50 to +150 °C CMOS LSI FM tuner IC for VICS

No.A1337-2/18 Operating supply voltage range at Ta = 25°C Parameter Symbol Conditions Ratings Unit Recommended supply voltage V DD Not to exceed the absolute maximum rating 4.5 to 5.5 V Supply voltage range V DD 5.0 V Serial interface voltage level VDD : Communications bus voltage Ratings Parameter Symbol Conditions min typ max Unit High level input voltage V IH 2.4 V DD V Low level input voltage V IL 0.0 0.7 V High level output voltage (open⋅drain) VOH V DD*V Low level output voltage (open·drain) VOL 0.0 0.2V DD V * High level output voltage causes the open drain to become the high-impedance state. Since the drain is pulled up to VDD, the voltage is equal to VDD. Electrical Characteristics at Ta = 25°C, unless otherwise specified. fc = 83MHz, Vin = 60dBµVEMF, fm = 1kHz, Audio filter : HPF =100Hz, LPF = 15kHz Sample application circuit (Sample application circuit) look-up Register map <writing> look-up Ratings Parameter Symbol Conditions min typ max Unit S/N 30dB sensitivity SN30 22.5kHz dev, fm = 1kHz, S/N = 30dB input level 15 20 dB µVEMF S/N 10dB sensitivity *1 SN10 7.5kHz dev, fm = 76kHz, S/N = 10dB input level *2 25 dB µVEMF Seek sensitivity (LO) Seek 22.5kHz dev, Vin = 40dB µVEMF Vsm = 2.0V adjustment Pin 18 (STDO) Lo → Hi input level 15 22 29 dB µVEMF S/N ratio 1 SN_1 22.5kHz dev, fm = 1kHz 50 60 dB S/N ratio 2 SN_2 7.5kHz dev, fm = 76kHz *2 35 dB Total harmonic distortion 1 THD_1 22. 5kHz dev, fm = 1kHz 0.1 1 % Total harmonic distortion 2 THD_2 75. 0kHz dev, fm = 1kHz 0.2 1 % Total harmonic distortion 3 THD_3 22. 5kHz dev, fm = 1kHz, Vin = 120dBµVEMF 0.1 1 % Image removal ratio Image 22.5kHz dev, fm = 1kHz 40 50 dB AM suppression ratio AMR AM 30% mod 45 55 dB Audio output level 1 Vo_1 75.0kHz dev, fm = 1kHz 170 270 430 mVrms Audio output level 2 Vo_2 7.5kHz dev, fm = 76kHz *2 16 25 40 mVrms Current drain I DD Input at no signal 30 45 mA *1 S/N = 10dB at BER = 1% *2 Audio filter : HPF = 100Hz, LPF = OFF

No.A1337-3/18 Package Dimensions unit : mm (typ) 3163B SANYO : SQFP48(7X7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (0.75) 11 2 2536

No.A1337-4/18 Sample Application Circuit (Block Diagram) 2 3 4 5 6 100pF 100pF 10pF SVC720 56pF 8pF X(*7) R3(*5) R2(*4) C( *6)0.1µF 8pF 12pF1SV249 22pF 100nH 110nH 110nH 1000pF 1000pF 22pF 2pF22pF 3300pF 18pF82pF COMPOUT 0.1µF 220Ω 0.1µF 0.1 µF 0.1µF T1(*1)T2(*1) CF(*3) R1(*2) SVC720 VDD_IO SCL SDA STDO VSS SVC720 0.1µF 0.1µF 1µF 5.6kΩ 100kΩ 1µF 180nH 3pF 180nH 100kΩ 100kΩ 33Ω 1µF VDD_AGC Prog. Counter Lock Det. Keyed-AGC RF AGC 0.1µF 1µF VDD_IF 42 1µF 0.1µF CF(*3) RF - IN VDD - RF GND - RF GND - LO VDD - LO 7 8 9 10 11 12 0.1µF N-AGC W-AGC Level Shift Ref. Counter POR I/F 1.8V REF1shot IF CNT IOBUS REG IRSSI Phase Det. Charge Pump44 35 34 33 32 31 30 28 2527 REG GND_IF 262936 0.1µF 10µF 1µF 0.1µF 0.1µF 10µF 47kΩ 500kΩ 1kΩ 1kΩ 10kΩ SD COMP Demod OPAMP AGC COMP ADC SMUT E CNT SMUTE BUFF1.5V SMETER (*1) T1 -TOKO : 5CCE #A638AN -1840YFZ T2 -TOKO : 5CCL ##613BG -0581WN (*2) R1 -TAIYO YUDEN: BK1608HS102 -T (*3) CF -MURATA : SFELL15M0GQQTS01 -B0 3dB Bandwidth 230 50kHz (*4) R2 -fm = 1kHz : NM fm = 76kHz : 6.8kΩ (*5) R3 -fm = 1kHz : 0Ω m = 76kHz : 6.8kΩ (*6) C -fm = 1kHz : NM fm = 76kHz : 680pF (*7) X -NIHON DENPA KOGYO CO.,LTD : AT41 14.55MHz

No.A1337-5/18 Pin Description Pin No. Pin Name Type Description

1 MIX_ON OUT 1stMIX signal output (-)

2 MIX_OP OUT 1stMIX signal output (+)

3 MIX_IP IN 1stMIX signal input (+)

4 MIX_IN IN 1stMIX signal input (-)

5 LNA_ON OUT LNA signal output (-)

6 LNA_OP OUT LNA signal output (+)

7 V DD_RF POWER RF block power

8 FM_IP IN FM signal input (+)

9 FM_IN IN FM signal input (-)

10 GND_RF GND RF block GND

11 GND_LO GND LO block GND

12 V DD_LO POWER LO block power

13 LOSC2 IN/OUT VCO resonant load pin 2

14 LOSC1 IN/OUT VCO resonant load pin 1

15 VT OUT Charge pump output

16 NC1 NC NC

17 NC2 NC NC

18 STDO OUT Monitor output/r eset detection output

19 SDA IN/OUT Serial data I/O (I 2C)

20 SCL IN Serial clock input (I 2C)

21 XOSC2 IN/OUT Crystal oscillator pin 2

22 XOSC1 IN/OUT Crystal oscillator pin 1

23 V SS GND Digital block GND

24 V DD_IO POWER 5V power for interface

25 V DD OUT Digital block power (built-in regulator output)

26 GND_IF GND IF block GND

27 COMPOUT OUT Composite signal output

28 DETREF IN/OUT FM detection si gnal amplifier reference voltage

29 DETADJ OUT FM detection signal amplitude adjustment

30 DETINP IN FM detection signal amplifier input (+)

31 DETINN IN FM detection signal amplifier input (-)

32 FDO OUT FM detection circuit output

33 SMETER IN/OUT S meter output

34 CRSSI IN/OUT Connection of smoothing capacitor for S-meter/S-meter output voltage adjustment

35 LIM2 IN/OUT Limiter offset canceling capacitor connection 2

36 LIM1 IN/OUT Limiter offset canceling capacitor connection 1

37 NC3 NC NC

38 NC4 NC NC

39 IF2nd_IN IN 2ndMIX signal input (-)

40 IF2nd_IP IN 2ndMIX signal input (+)

41 IF1stOUT OUT 1st IF am plifier signal output

42 V DD_IF POWER IF block power

43 IF1st_IN IN 1s t IF amplifier signal input (-)

44 IF1st_IP IN 1st IF am plifier signal input (+)

45 V DD_AGC POWER Pin diode AGC circuit power

46 FMAGC OUT FM pin diode driver output

47 CAGC IN/OUT AGC circuit smoothing capacitor connection 2

48 LNAAGC IN/OUT AGC circuit smoothing capacitor connection 1

No.A1337-6/18 Communications Specifications Communications specifications are shown below : Serial Interface(I 2C-bus) ; Serial interface (I2C-bus) Send/receive is made via I2C-bus that consists of two bus lines, each being a serial • data • line (SDA) and serial • clock

• line (SCL). This bus enables 8-bit bi-directional serial data transmission at maximum 400kbit/s (fast mode). This is not compatible with the Hs mode. 1. Terms used in I2C The following terms are used in I2C. Terms Description Transmitter Device to send data to the bus Receiver Device to receive data from the bus Master Device to start data transmission, to gener ate the clock signal, and to end data transmission Slave Device whose address is designated by the master 2. "Start" and "Stop" conditions "Start" condition must be satisfied at start of data communications and "Stop" condition must be satisfied at end of communications. The condition in which the SDA line changes from "H" to "L" with SCL at "H" is called the "Start" line. The condition in which the SDA line changes from "L" to "H" with SCL at "H" is called the "Stop" condition. SDA SCL SDA SCL S START condition STOP condition P

No.A1337-7/18 3. Data transmission The length of each byte output to the SDA line is always 8 bits. An acknowledge bit is always necessary after each byte, Data is transmitted sequentially from the most significant bit (MSB). During data transfer, the slave address is transmitted after the "Start" condition (S). Data transfer is always ended by the "Stop" condition (P) generated by the master. 4. Acknowledge (Confirmation of reception) When the master generates the acknowledge clock pulse, the transmitter opens the SDA line (SDA line entering the "H" state). When the acknowledge clock pulse is in the "H" state, the receiver sets the SDA line to "L" each time it receives one byte (eight bits) of data. When the master functions as receiver, the master informs the end of data to the slave by omitting acknowledgement at the end of data sent from the slave. START condition clock pulse for ACK ACK ; acknowledgement NACK ; not acknowledgement Dataoutput by Transmitter Release the SDA line(HIGH) NACK(master is reciever) ACK(master is transmitter) Dataoutput by Receiver SCL from Master S 9821 SDA SCL Most- significant bit of MSB byte complete, interrupt within slave clock line held low while interrupts are serviced D6 D1 D0 ACK signal from slsave clock pulse for ACK clock pulse for ACK START or repeated START condition STOP or repeated START condition ACK signal from receiver S or Sr Sr or P Sr 92 3-8189721 P ACK ; acknowledgement

No.A1337-8/18 5. Software reset After power ON, enter the signal as follows to avoid malfunction. If the communication is interrupted (microcomputer reset, etc.), entry of the following signal enables normal operation. 6. Electrical Specification and Timing for I/O Stages Bus line characteristics FAST-MODE Parameter Symbol min max unit For SCL = 100kHz (Example) SCL clock frequency fSCL - 400 kHz 100 SDA, SCL fall time t1 20+0.1Cb 300 ns - SDA, SCL rise time t2 20+0.1Cb 300 ns - SCL "H" time t3 0.6 - µs 3 SCL "L" time t4 1.3 - µs 7 "Start" condition hold time t5 0.6 - µs 10 Data hold time For I2C bus device t6 0.3 - µs - Data setup time t7 0.1 - µs 3 "Stop" condition setup time t8 0.6 - µs 10 "Stop"-"Start" bus free time t9 1.3 - µs 20 "Start" condition setup time t10 0.6 - µs - Bus line capacitive load Cb - 400 pF - SDA SCL PSrS 12 789 START condition STOP conditionreperted START condition SDA t10 SCL START condition STOP condition t2t4 t1t7 t9 t8t3t6t5

No.A1337-9/18 7. Definition of each bit in one byte 7-1. Slave address The slave address consists of a fixed seven-bit address "1110010" uniqueto the chip and the eighth bit or a data direction bit (R/W) : Send (Write) when this bit is "0" and Receive (Read) when this bit is "1". R/W BIT READ 1 WRITE 0 7-2. Register address Since the total number of internal registers is 16, 4-bit data set on the MSB side becomes invalid. 7-3. Register data Each register data consists of eight bits. 1 1 1 0 0 1 0 R/W MSB LSB Fixed address 0 0 0 0 A3 A2 A1 A0 MSB LSB Invalid address Valid address D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB

No.A1337-10/18 8. Command Format 8-1. Individual register • data writing 8-2. Individual register • data reading S111001000 0000 1 / 0 1 / 0 1 / 0 1 / 0 0 START condition SDA Slave address Register addressACK From master to slave From slave to master 1/0 0 P Register data ACK STOP condition Write Invalid address ACK S111001000 0 0 0 0 1/0 1/0 1/0 1/0 0 START condition SDA Slave address Register addressACK From master to slave From slave to master Write Invalid address ACK S r 111001010 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1 P Repeated START condition Slave address Register addressACK Read NACK STOP condition

No.A1337-11/18 8-3. Consecutive register • data writing Continuous data transmission after transmission of initially-set address data of register • data writing sequence enables writing of data in the consecutive register • data area. In this case, the register • address increases by one address from the initially-set address of the sequence and continues increasing till the "Stop" condition (P) is generated. 8-4. Consecutive register • data reading When the master returns ACK (0 data) after reading of the initial register • address • data of read sequence, the register

• address increases by one address, enabling consecutive reading of data corresponding to each register address. If the master does not return ACK (0 data), the register address does not increase. S111001000 0000 1 / 0 1 / 0 1 / 0 1 / 0 0 START condition SDA Slave address Register addressACK 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 Register data (of Register address) ACK Register data (of Register address+1) ACK Write Invalid address ACK From master to slave From slave to master 1/0 0 0 P Register data (of Register address+2) ACK Register data (of Register address+n) ACK STOP condition S111001000 0000 1 / 0 1 / 0 1 / 0 1 / 0 0 START condition SDA Slave address Register addressACK S r 111001010 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 Slave address ACKRepeated START condition Register data (of Register address) ACK Write Read Invalid address ACK 0 1/0 1/0 1/0 1/0 1/0 1/0 From master to slave From slave to master 1/0 1/0 0 1 P Register data (of Register address+1) ACKACK Register data (of Register address+n) NACK STOP condition

No.A1337-12/18 Register Map <writing> * Register value : Decimal notation Register address Bit Name Functions Bit operation Default value

7 PE Power enable (all blocks) 0:OFF 1:ON 1

6 0:RSTDET 1:SD 2:LDO 3:KAGC 5 4:IFCNT_CLK 5:RSSI_CLK SWSTD Selection of digital signal monitor pin output /reset detection output 6:PROCNTR 7:REFCNTR 3 0:Oscillation level small LOBIAS Oscillation level adjustment 15:Oscillation level large 7 15:10dB µV 5 *1dB STEP 3 55:50dB µV SDREG LO/DX changeover (seek determination level adjustment) (As for value reference value)

1 CTE 2ndIF count measurement start contro l 0:OFF 1:ON (automatically OFF) 0

0 RSTDET Initial register writing for reset detection 0:Reset 1:Normal 1

PCNT PLL synthesizer program data 0:LSB 7 0:4ms 1:8ms GT 2ndIF count time selection 2:32ms 3:64ms 5 0:10.95MHz 1:11.25MHz 4 2:14.55MHz 3:14.75MHz CSEL PLL master clock signal selection 4:21.15MHz 5:21.45MHz FSEL PLL comparative frequency setting 0:50kHz 0

7 RSEL PLL REF reference frequency selection 0:50kHz 0

6 ADCLK RSSIADC clock frequency changeover 0:800kHz 0

5 0:0ns 1:2ns DZSEL Dead zone adjustment 2:10ns 3:20ns 3 0:0 µA 2 *10 µA STEP CI ChargePump output current setting 15:150 µA Continued on next page. setting) l(lowerloca50kHz frequency 1stlfrequencyReceiver PCNT setting) l(upperloca50kHz frequency 1stlfrequencyReceiver PCNT

No.A1337-13/18 Continued from preceding page. * Register value : Decimal notation Register address Bit Name Functions Bit operation Default value 7 0:Fixing 0

6 PEVCO Power enable (VCO) 0:OFF 1:ON 1

5 BGRTEST BGR (RFAGC circuit) inspection mode

0:OFF 1:ON 0 4 0:Fixing 0 3 0:Softmute function OFF 2 1:-4dB µV *2dB STEP 1 15:24dB µV SMTREG Softmute star t point adjustment (As for value reference value)

7 RSSI detection sensitivity adjus tment 0:31mV/dB *1mV/dB STEP

6 *RSSI output gradient 7:38mV/dB RSSIGAIN (As for value reference value)

4 RSSI detection temperature characteristics

0:4dB *0.5dB STEP 3 *Front-end circuit temperature characteristics compensation 7:7.5dB RSSITMP (As for value reference value) 1 0:Fixing 7 0:Sensitivity low *1.1dB STEP WAGC W_AGC sensitivity adjustment 15:Sensitivity high 3 0:Sensitivity low *1.1dB STEP NAGC N_AGC sensitivity adjustment 15:Sensitivity high 7 0:-3dB µV 6 *2dB STEP 5 15:27dB µV KAGC Keyed-AGC judgment level adjustment (As for value reference value)

3 WAGCSW W_AGC_ON/OFF 0:OFF 1:ON 1

2 NAGCSW N_AGC_ON/OFF 0:OFF 1:ON 1

1 ATTAGCSW ATT_AGC_ON/OFF 0:OFF 1:ON 1

0 LNAAGCSW LNA_AGC_ON/OFF 0:OFF 1:ON 1

7 KAGCSW Keyed-AGC_ON/OFF 0:OFF 1:ON 0

6 WKAGCSW Keyed-W_AGC sensitivity changeover 0: No sensitivity change 1:- 10dB sensitivity change 0

5 0:17dB 1:19dB LNAG LNA gain adjustment 2:21dB 3:23dB 3 0:-0.2dB 1:2.8dB MIXG 1stMIX gain adjustment 2:4.5dB 3:5.4dB 1 0:7dB 1:10dB IFAG 1stIFA gain adjustment 2:13dB 3:16dB 0:Fixing 0 4 0:oscillation allowance, small XOSCADJ Crystal oscillation level adjustment 7:oscillation allowance, large 1 0:Fixing 0 0 0:Fixing 0 Continued on next page.

No.A1337-14/18 Continued from preceding page. * Register value : Decimal notation Register address Bit Name Functions Bit operation Default value 7 0:3.1dB 1:3.7dB 2:4.4dB 3:5.2dB RMXG Composite output level adjustment 4:6.0dB 5:6.9dB 6:8.0dB 9:9.1dB 4 0:106mVrm 1:119mVrms 2:151mVrms 3:167mVrms 3 4:212mVrm 5:230mVrms 6:276mVrms 7:297mVrms DEMODR Detection output level adjustment (As for value reference value)

1 PERF Power enable (RF block) 0:OFF 1:ON 1

0 PEIF Power enable (IF bl ock) 0:OFF 1:ON 1

7 PEDEM Power enable (LIM/DEMOD) 0:OFF 1:ON 1

6 PEAMP Power enable (audio amplifier) 0:OFF 1:ON 1

5 PEXOSC Power enable (XOSC) 0:OFF 1:ON 1

4 PELNA Power enable (LNA) 0:OFF 1:ON 1

3 PELO1 Power enable (LO block_VCOetc) 0:OFF 1:ON 1

2 PELO2 Power enable (LO block _LOBUFetc) 0:OFF 1:ON 1

1 PEREFCNT Power enable (REF counter) 0:OFF 1:ON 1

0 PERFAGC Power enable (RFAGC block) 0:OFF 1:ON 1

No.A1337-15/18 Register Map <reading> * Register value : Decimal notation Register address Bit Name Functions Bit operation Default value 6 0:RSTDET 1:SD 2:LDO 3:KAGC 5 4:IFCNT_CLK 5:RSSI_CLK SWSTD Selection of digital signal monitor pin output /reset detection output 6:PROCNTR 7:REFCNTR 3 0:Oscillation level small LOBIAS GM adjustment of the oscillation circuit core block 15:Oscillation level large 7 15:10dB µV 5 *1dB STEP 3 55:50dB µV SDREG LO/DX changeover (seek determination level adjustment) (As for value reference value) IFCOUT 2ndIF count value output 0:LSB 7 0:4ms 1:8ms GT 2ndIF count time selection 2:32ms 3:64ms 5 0:10.95MHz 1:11.25MHz 4 2:14.55MHz 3:14.75MHz CSEL PLL master clock signal selection 4:21.15MHz 5:21.45MHz FSEL PLL comparative frequency setting 0:50kHz 0 5 0:0ns 1:2ns DZSEL Dead zone adjustment 2:10ns 3:20ns 3 0:0 µA 2 *10 µA STEP CI ChargePump output current setting 15:150 µA Continued on next page. GT )valuecountndIF2(valueIFCOUTfrequencyndIF2 =

No.A1337-16/18 Continued from preceding page. * Register value : Decimal notation Register address Bit Name Functions Bit operation Default value 7 0:Fixing 0

5 BGRTEST BGR(RFAGC circuit) inspection mode

0:OFF 1:ON 0 4 0:Fixing 0 3 0:Softmute function OFF 2 1:-4dB µV *2dB STEP 1 15:24dB µV SMTREG Softmute star t point adjustment (As for value reference value) 6 *RSSI output gradient 7:38mV/dB RSSIGAIN (As for value reference value) 0:4dB *0.5dB STEP 3 *Front-end circuit temperature characteristics compensation 7:7.5dB RSSITMP (As for value reference value) 1 0:Fixing 7 0:Sensitivity low *1.1dB STEP WAGC W_AGC sensitivity adjustment 15:Sensitivity high 3 0:Sensitivity low *1.1dB STEP NAGC N_AGC sensitivity adjustment 15:Sensitivity high 7 0:-3dB µV 6 *2dB STEP 5 15:27dB µV KAGC Keyed-AGC judgment level adjustment (As for value reference value) 5 0:17dB 1:19dB LNAG LNA gain adjustment 2:21dB 3:23dB 3 0:0dB 1:2dB MIXG 1stMIX gain adjustment 2:4dB 3:6dB 1 0:7dB 1:10dB IFAG 1stIFA gain adjustment 2:13dB 3:16dB 0:Fixing 0 4 0:oscillation allowance, small XOSCADJ Crystal oscillation level adjustment 7: Oscillation allowance, larg 1 0:Fixing 0 0 0:Fixing 0 Continued on next page.

No.A1337-17/18 Continued from preceding page. * Register value : Decimal notation Register address Bit Name Functions Bit operation Default value 7 0:3.1dB 1:3.7dB 2:4.4dB 3:5.2dB RMXG Composite output level adjustment 4:6.0dB 5:6.9dB 6:8.0dB 9:9.1dB 4 0:106mVrm 1:119mVrms 2:151mVrms 3:167mVrms 3 4:212mVrm 5:230mVrms 6:276mVrms 7:297mVrms DEMODR Detection output level adjustment (As for value reference value) WAGCOUT W_AGC output 0:LSB SMTSWOUT Soft mute changeover control signal output 0:LSB RSSIOUT RSSI digital output 0:LSB

PS No.A1337-18/18 SANYO Semiconductor Co.,Ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. When designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. Such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. Information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equi pment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. In the event that any or all SANYO Semiconductor C o.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. This catalog provides information as of October, 2008. Specifications and information herein are subject to change without notice.