LB1928

LB1928_08 SANYO | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 11

Technical content

Features

• 3-phase bipolar drive (30V, 3.1A)
• Direct PWM drive technique
• Built-in diode for absorbing output lower-side kickback
• Speed discriminator and PLL speed control
• Speed lock detection output
• Built-in forward/reverse switching circuit
• Built-in protection circuitry includes current limiter, overheat protection, motor restraint protection, etc. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage V CC max 30 V Maximum output current I O max T ≤ 500ms 3.1 A Allowable power dissipation 1 Pd max 1 Independent IC 3 W Allowable power dissipation 2 Pd max 2 With an arbitrary large heat sink 20 W Operating temperature Topr -20 to +80 °C Storage temperature Tstg -55 to +150 °C Monolithic Digital IC For Office Automation Equipment 3-phase Brushless Motor Driver

No.6197-2/11 Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Ratings Unit Power supply voltage range 1 V CC 9.5 to 28 V Regulator voltage output current I REG -30 to 0 mA LD output current I LD 0 to 15 mA Electrical Characteristics at Ta = 25°C, VCC = VM = 24V Ratings Parameter Symbol Conditions min typ max Unit Power supply current 1 I CC1 23 30 mA Power supply current 2 I CC2 In STOP mode 3.5 5.0 mA Output Output saturation voltage 1 V Osat1 I O = 1.0A, VO (SINK) +VO (SOURCE) 2.0 2.5 V Output saturation voltage 2 V Osat2 I O = 2.0A, VO (SINK) +VO (SOURCE) 2.6 3.2 V Output leak current I Oleak 100 µA Lower-side diode forward voltage 1 V D1 ID = -1.0A 1.2 1.5 V Lower-side diode forward voltage 2 V D2 ID = -2.0A 1.5 2.0 V 5V regulator voltage output Output voltage V REG I O = -5mA 4.65 5.00 5.35 V Voltage fluctuation ∆VREG1 V CC = 9.5 to 28V 30 100 mV Load fluctuation ∆VREG2 I O = -5 to -20mA 20 100 mV Hall amplifier Input bias current I HB -2 -0.5 µA Common mode input voltage range VICM 1.5 V REG-1.5 V Hall input sensitivity 80 mVp-p Hysteresis width ∆VIN 15 24 42 mV Input voltage L→H VSLH 12 mV Input voltage H→L VSHL -12 mV PWM oscillator Output High level voltage V OH (PWM) 2.5 2.8 3.1 V Output Low level voltage V OL (PWM) 1.2 1.5 1.8 V Oscillator frequency F (PWM) C = 3900pF 18 kHz Amplitude V (PWM) 1.05 1.30 1.55 Vp-p CSD circuit Operating voltage V OH (CSD) 3.6 3.9 4.2 V External capacitance charge current ICHG -17 -12 -9 µA Operating time T (CSD) C = 10 µF Design target value 3.3 s Current limiter operation Limiter VRF V CC-VM 0.45 0.5 0.55 V Thermal shutdown operation Thermal shutdown operating temperature TSD Design target value (junction temperature) 150 180 °C Hysteresis width ∆TSD Design target value (junction temperature) 50 °C FG amplifier Input offset voltage V IO (FG) -10 +10 mV Input bias current I B (FG) -1 +1 µA Output High level voltage V OH (FG) IFGO = -0.2mA VREG-1.2 VREG-0.8 V Output Low level voltage V OL (FG) IFGO = 0.2mA 0.8 1.2 V FG input sensitivity GAIN 100 times 3 mV Next-stage Schmitt comparator width Design target value 100 180 250 mV Operation frequency range 2 kHz Open-loop gain f (FG) = 2kHz 45 51 dB Continued on next page.

No.6197-3/11 Continued from preceding page. Ratings Parameter Symbol Conditions min typ max Unit Speed discriminator Output High level voltage V OH (D) IDO = -0.1mA VREG-1.0 VREG-0.7 V Output Low level voltage V OL (D) IDO = 0.1mA 0.8 1.1 V Count number 512 PLL output Output High level voltage V OH (P) IPO = -0.1mA VREG-1.8 VREG-1.5 VREG-1.2 V Output Low level voltage V OL (P) IPO = 0.1mA 1.2 1.5 1.8 V Lock detection Output Low level voltage V OL (LD) ILD = 10mA 0.15 0.5 V Lock range 6.25 % Integrator Input bias current IB (INT) -0.4 +0.4 µA Output High level voltage V OH (INT) I INTO = -0.2mA VREG-1.2 VREG-0.8 V Output Low level voltage V OL (INT) I INTO = 0.2mA 0.8 1.2 V Open-loop gain f (INT) = 1kHZ 45 51 dB Gain bandwidth product Design target value 450 kHz Reference voltage Design target value -5% VREG/2 5% V Crystal oscillator Operating frequency range f OSC 3 10 MHz Low level pin voltage V OSCL I OSC = -0.5mA 1.65 V High level pin current I OSCH V OSC = VOSCL+0.3V 0.4 mA Start/stop pin High level input voltage range V IH (S/S) 3.5 VREG V Low level input voltage range V IL (S/S) 0 1.5 V Input open voltage V IO (S/S) VREG-0.5 VREG V Hysteresis width ∆VIN 0.35 0.50 0.65 V High level input current I IH (S/S) V (S/S) = VREG -10 0 10 µA Low level input current I IL (S/S) V (S/S) = 0V -280 -210 µA Forward/reverse pin High level input voltage range V IH (F/R) 3.5 VREG V Low level input voltage range V IL (F/R) 0 1.5 V Input open voltage V IO (F/R) VREG-0.5 VREG V Hysteresis width ∆VIN 0.35 0.50 0.65 V High level input current I IH (F/R) V (F/R) = VREG -10 0 +10 µA Low level input current I IL (F/R) V (F/R) = 0V -280 -210 µA

No.6197-4/11 Package Dimensions unit : mm (typ) 3147C Pin Assignment 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LB1928 OUT1 F/R IN3 -IN3+ IN2+ IN1+ IN1- GND1 S/S FG IN+ FGIN- FGOUT LDIN2- 123456789 1 0 1 1 1 2 1 3 1 4 OUT2 OUT3 V CCGND2 VM PWM CSD XI XO INT OUT INTIN POUT DOUTVREG Top view Relationship between crystal oscillator frequency fOSC and FG frequency fFG is as follows. fFG (servo) = fOSC/ (ECL divide-by-16×count number) = fOSC/8192 Truth Table Source F/R = “L” F/R = “H” Sink IN1 IN2 IN3 IN1 IN2 IN3

1 OUT2 →OUT1 H L H L H L

2 OUT3 →OUT1 H L L L H H

3 OUT3 →OUT2 H H L L L H

4 OUT1 →OUT2 L H L H L H

5 OUT1 →OUT3 L H H H L L

6 OUT2 →OUT3 L L H H H L

-20 0 20 40 60 80 100 Without heat sink Ambient temperature, Ta -- °C Pd max -- Ta Allowable power dissipation, Pd max -- W With an arbitrary large heat sink

No.6197-5/11 Block Diagram and Sample Application Circuit FG RST LOCK DET SPEED DISCRI ECL Xtal OSC CSD CIRCUIT CURR LIM PLL S/S F/R 5VREG LOGIC HALL HYS AMP DRIVER COMP TSD PWM OSC BGP VREF OUT1 OUT2 OUT3 VM Rf VCC VCC PWM CSDINTOUTINTINDOUTLD LD FGOUTFGIN- FGIN+ FG AMP GND1 XI XO S/S F/R VREG GND2 VREF VREG VREG/2 INT AMP IN3IN2IN1 POUT

No.6197-6/11 Pin Description Pin No. Pin name Pin function Equivalent circuit OUT1 OUT2 OUT3 Motor drive output pins. Connect a Schottky diode between these outputs and VCC. 3 GND2 Output ground pin. 5 VM Output block power supply and output current detection pin. Connect a resistor (Rf) between this pin and VCC to detect the output current as a voltage. The output current is limited according to the equation IOUT = VRF/Rf. 4 V CC Power supply pin (except for output block). 6 VREG Regulated power suppl y output pin (5V output). Connect a capacitor (approx. 0.1µF) between this pin and ground to stabilize the output. 7 PWM PWM frequency setting pin. Connect a capacitor between this pin and ground. C = 3900pF results in a frequency of about 18kHz. 8 CSD Lock protection circuit operation time setting pin. Connecting a capacitor of about 10µF between this pin and ground results in a protection circuit operation time of about 3.3 seconds. XI XO Crystal oscillator pins. Connect to quartz oscillator to generate the reference clock. When an external clock (of several MHz) is used, the clock signal should be input via a resistor of about 5.1kΩ connected in series with the XI pin. In this case, the XO pin must be left open. Continued on next page.

No.6197-7/11 Continued from preceding page. Pin No. Pin name Pin function Equivalent circuit 11 INT OUT Integrator output pin (speed control pin). 12 INT IN Integrator input pin. 13 P OUT PLL output pin. 14 D OUT Speed discriminator output pin. Acceleration : High, Deceleration : Low 15 LD Speed lock detection pin. When motor rotation is within lock range (±6.25%) : Low Withstand voltage : 30V max. Continued on next page.

No.6197-8/11 Continued from preceding page. Pin No. Pin name Pin function Equivalent circuit 16 FG OUT FG amplifier output pin. FGIN- FGIN+ FG amplifier input pin. By connecting a capacitor (approx. 0.1µF) between FGIN+ and ground, the logic circuitry is reset. 19 S/S Start/stop control pin. Start (Low) : 0V to 1.5V Stop (High) : 3.5V to VREG High when open. Hysteresis width : approx. 0.5V. 20 GND1 Ground pin (except for output block). IN1+ IN1- IN2+ IN2- IN3+ IN3- Hall input pins. High when IN+ > IN-, Low when IN+ < IN-. Hall signal should have an amplitude of at least 100mVp-p (differential operation). When Hall signal noise is a problem, connect a capacitor between IN+ and IN-. 27 F/R Forward/reverse control pin. Forward (Low) : 0V to 1.5V Reverse (High) : 3.5V to VREG High when open. Hysteresis width : approx. 0.5V.

No.6197-9/11 Description of the LB1928 1. Speed control circuit The IC performs speed control through combined use of a speed discrimination circuit and PLL circuit. The speed control circuit counts FG cycles and outputs a deviation signal every 2FG cycles. The PLL circuit outputs a phase deviation signal every FG cycle. The FG servo frequency is determined by the following equation. The motor rotation speed is set by the number of FG pulses and the crystal oscillator frequency. fFG (servo) = fOSC/8192 fOSC : Crystal oscillator frequency 2. Output drive circuit In order to reduce power loss at the output, the LB1927 uses the PWM drive technique. While ON, the output transistors are always saturated, and motor drive power is adjusted by varying the output ON duty ratio. Because output PWM switching is performed by the lower-side output transistor, a Schottky diode must be connected between OUT and VCC. (If the reverse recovery time of the diode is too long, a feedthrough current will flow at the instant when the lower-side transistor goes ON.) An internal diode is provided between OUT and GND. If large output current causes a problem (waveform distortion during lower-side kickback, etc.), an external rectifying diode or Schottky diode should be connected. The output diode is integrated only on the lower side. 3. Current limiting circuit The current limiting circuit limits the peak current to the value I = VRF/Rf (VRF = 0.5V typ., Rf : current detector resistance). Current limiting is achieved by reducing the ON duty ratio of the output, which reduces the current. 4. Power save circuit In order to reduce current drain in the STOP condition, the IC goes into power save mode. In this condition, bias current to most circuits is cut off, but the 5V regulator output remains active. 5. Reference clock The reference clock for speed control can be input using one of the following two methods. (1) Using a crystal oscillator When a crystal is used for oscillation, connect the crystal, capacitors, and a resistor as shown in the figure below. VREG XI XO (Reference values) Oscillator frequency (MHz) C1 ( µF) C2 (pF) C3 (pF) C4 (pF) R1 ( Ω) 3 to 5 0.1 15 47 10 330k 5 to 8 0.1 10 47 None 330k 8 to 10 0.1 10 22 None 330k The circuit configuration and values are for reference only. The crystal oscillator’s characteristics as well as the possibility of floating capacitance and noise due to layout factors must be taken into consideration when designing an actual application. C1, R1 : For stable oscillation C3 : For oscillator coupling C2 : For stabilization and to prevent oscillation at upper harmonic frequencies C4 : Prevents oscillation at upper harmonic frequencies

No.6197-10/11 [Precautions for wiring layout design] Since the crystal oscillator circuit operates at high frequencies, it is susceptible to the influence of floating capacitance from the circuit board. Wiring should be kept as short as possible and traces should be kept narrow. When designing the external circuitry, pay special attention to the wiring layout between the oscillator and C3 (C2), to minimize the influence of floating capacitance. The capacitor C4 is quite effective at reducing the negative resistance (gain) at high frequencies. However, care is required to avoid excessive reduction in the negative resistance at the fundamental frequency. (2) External clock input (equivalent to crystal oscillator, several MHz) When using an external signal source instead of a crystal oscillator, the clock signal should be input from the XI pin through a resistor of about 5.1kΩ connected to the pin in series. The XO pin should be left open. Signal input level Low : 0 to 0.8V High : 2.5 to 5.0V 6. Speed lock range The speed clock range is ±6.25% of the rated speed. When the motor rotation is within the lock range, the LD pin becomes Low (open collector output). When the motor rotation goes out of the lock range, the ON duty ratio of the motor drive output is varied according to the amount of deviation to bring the rotation back into the lock range. 7. PWM frequency The PWM frequency is determined by the capacitance connected to the PWM pin. f PWM ≈ 1/ (14400×C) PWM frequency in the range 15 to 25kHz is desirable. The ground side of the connected capacitor must be connected to the GND1 pin with a lead that is as short as possible. 8. Hall input signal The Hall input requires a signal with an amplitude of at least the hysteresis width (42mV max.). Taking possible noise influences into consideration, an amplitude of at least 100mV is desirable. If noise during output phase switching disrupts the output waveform, insert capacitors across the Hall signal inputs (between the + and - inputs), and position those capacitors as close as possible to the pins. 9. Forward/reverse switching Forward/reverse switching of motor rotation is carried out with the F/R pin. If this is performed while the motor is running, the following points must be observed :

• Feedthrough current during switching is hand led by proper circuit design. However, the VCC voltage rise during switching (caused by momentary return of motor current to power supply) must not exceed the rated voltage (30V). If problems occur, the capacitance between VCC and GND must be increased.
• If the motor current after switching exceeds the current lim iter value, the lower-side transistors go OFF but the upper-side transistors go into the short brake state, which causes a current flow. The magnitude of the current is determined by the motor counterelectromotive voltage and the coil resistance. This current may not exceed the rated current (3.1A). (Forward/reverse switching at high speed therefore is not safe.) 10. Motor restraint protection circuit To protect the IC and the motor itself when rotation is inhibited, a restraint protection circuit is provided. If the LD output is High (unlocked) for a certain interval in the start condition, the lower-side transistors are turned off. The length of the interval is determined by the capacitance at the CSD pin. A capacitance of 10µF results in a set interval of about 3.3 seconds. (Tolerance approx. ±30%) Set interval (s) ≈ 0.33×C (µF) If the capacitor arrangement is subject to leak current, possible adverse effects such as setting time tolerances must be taken into consideration. When the restraint protection circuit has been activated, the condition can only be canceled by setting the system to the stop condition or by turning the power off and on again (in the stop condition). When wishing not to use the restraint protection circuit, connect the CSD pin to ground. If the stop time when releasing the restraint protection is short, the capacitor charge will not be fully dissipated. This in turn will cause a shorter restraint protection activation time after the motor has been restarted. The stop time should therefore be designed to be sufficiently long, using the equation shown below (also when restarting in the motor start transient state). Stop time (ms) ≥ 15×C (µF)

PS No.6197-11/11 SANYO Semiconductor Co.,Ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. When designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. Such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. Information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equi pment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. In the event that any or all SANYO Semiconductor C o.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. 11. Power supply stabilization Because this IC provides a high output current and uses a switching drive technique, power supply line fluctuations can occur easily. Therefore, a capacitor of sufficient capacitance (several ten µF or higher) must be connected between the VCC pin and ground to assure stable operation. The ground connection of this capacitor must be connected to the GND2 pin, which is the power block ground, at a point as close as possible to the IC. If, due to problems associated with the heat sink, the (electrolytic) capacitor cannot be connected near the this pin, a ceramic capacitor of about 0.1µF must be connected near the pin. Since the likelihood of power line fluctuation increases if diodes are inserted in the power supply lines to prevent destruction of the IC if power is connected with reverse polarity, a larger capacitance will be required. 12. VREG stabilization A capacitor (about 0.1µF) must be connected to the VREG pin (the 5V regulator output), which functions as the control circuit power supply, for stabilization. The ground side of this capacitor must be connected to the GND1 pin with a lead that is as short as possible. 13. Integrating amplifier related component values The external components used in the integrating amplifier must be located as close as possible to the IC to minimize the circuit’s susceptibility to noise. These components must be located as far as possible from the motor. This catalog provides information as of December, 2008. Specifications and information herein are subject to change without notice.