L9310

L9310 AGERE | Alldatasheet

Document overview

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Technical content

Features

■ 5 V and battery operation ■ Optional automatic battery switch ■ 15 operational and test modes ■ Appropriate for 46 dB longitudinal balance applica- tions ■ Minimal external components required at all inter- faces ■ Ultralow power dissipation ■ Software/hardware adjustable dc parameters and supervision thresholds ■ Meter pulse compatible ■ Ground start/ground key compatible Solid-State Ring Relay ■ Low impulse noise ■ Current-limited switches/thermal protection Line Test Matrix ■ Single-ended or differential measurements ■ Current or voltage sense ■ ac or dc measurements ■ Dedicated analog input and output

Applications

■ Pair Gain ■ Digital Loop Carrier (DLC) ■ Central Office (CO) ■ Fiber-in-the-Loop (FITL)

Description

The L9310 electronic line interface and line access circuit (LILAC) provides all the functions that are nec- essary to interface a codec to the tip and ring of a subscriber loop, integrating the battery feed and ring- ing access relay and line test access in one low- power, low-cost package. The L9310 requires a 5 V and battery supply to oper- ate. Included is an automatic battery switch. The bat- tery feed offers forward and reverse battery, on-hook transmission, ground start, ground key, and meter pulse operational modes. It also has a low-power scan and a disconnect mode. In all operating states, this IC is designed for minimal power dissipation. This device is designed to mini- mize the number of external components required at all interfaces. The dc template, current limit, and overhead voltage and loop supervision threshold are programmable via an applied voltage source. The voltage source may be an external programmable voltage source or derived from the V REF SLIC output. The integrated solid-state switch offers power ringing access. Impulse noise is minimized, thus eliminating the need for external zero-cross switching circuitry. The L9310 provides line test capability. The differen- tial or single-ended ac and dc line voltage or current may be measured by the L9310.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 2 Agere Systems Inc. Table of Contents Contents Page Logic Inputs and Outputs, V Contents Page Battery Out of Range Detector: High Battery Out of Range Detector: Low First-Generation Codec ac Interface First-Generation Codec ac Interface Set Z Basic Loop Start Application Using T7504 Third-Generation Codec ac Interface

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 4 Agere Systems Inc. ■ SLIC, solid-state ring relay, and line test access, inte- grated into a single package ■ 5 V and battery operation ■ User-defined power control options: — Automatic battery switch — Power control resistor — Package thermal capabilities ■ Minimal external components required ■ Operating states: — Forward active — Reverse active (controlled rate of reversal) — Scan — Ground start (tip open) — All-off or disconnect — Ring — Periodic pulse metering (PPM) active modes — Line test modes (dc/ac line voltage/current) ■ Ultralow power: — Scan, 15 mW — Active states, on-hook, 75 mW — Ring mode, on-hook, 90 mW — Disconnect, 10 mW ■ Adjustable overhead voltage: — Default overhead adequate for 3.14 dB into 900 Ω overload — Controlled rate of overhead adjustment ■ Latched parallel input data interface with reset ■ Interrupt (unlatched) based loop status monitor ■ Adjustable current limiter: — 10 mA to 70 mA programming range ■ Adjustable loop closure detector with hysteresis: — 4 mA detect, 2.5 mA no detect minimum, upper limit of 15 mA detect — Hysteresis, typical 20% of programmed on-hook to off-hook threshold ■ Ring trip detector: — Single-pole filtering ■ Thermal shutdown protection with hysteresis ■ Line break switch will foldover into a low-current state under high-voltage fault conditions ■ Battery out-of-range monitor circuit: — All-off upon loss of battery (low battery condition) — All-off upon high battery (fault condition) ■ Longitudinal balance: — ETSI/ITU-T, GR-909 balance ■ Ground start: — Tip open state — Ring ground detector ■ Ground key: — Tip/ring ground detector ■ Meter pulse compatible: — Dedicated meter pulse signal input — On-hook transmission of PPM (up to 5 Vrms) — Provides convenient access for hybrid filtering of meter pulse ■ Line test: — Line test modes (ac or dc): 1. Voltage tip to ground 2. Voltage ring to ground 3. Voltage tip to ring 4. Current tip to ring 5. Current tip to ground 6. Current ring to ground — Inject test tones through codec interface or dedi- cated input pin — Analog output at dedicated output pin ■ RFI/EMC-EN 300 386-2 V1.1.3 (1997-12) ■ Integrated 2 Form C ring relay: — Low impulse noise — Current-limited switches — Break-before-make and make-before-break switching ■ Meets ITU-T K20, ITU-T K21, and Telcordia* GR1089 requirements with external protection device ■ 44-pin, surface-mount plastic package (PLCC) The L9310 electronic line interface and line access cir- cuit (LILAC) provides all the functions that are neces- sary to interface a codec to the tip and ring of a subscriber loop, integrating the battery feed and ringing access relay in one low-power, low-cost package. The physical construction of the device is two chips. The first chip is manufactured in Agere 90 V complemen- tary bipolar integrated circuit (CBIC-S) technology. This chip contains the SLIC functionality: ■ ac transmission path ■ dc feedback and functions ■ Active dc current limit ■ Active mode loop supervision ■ Thermal shutdown * Telcordia is a trademark of Bell Communications Research, Inc.

July 2001 Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit Agere Systems Inc. 5 Description (continued) The second chip is manufactured in Agere dielectrically isolated 320 V bipolar CMOS diffused metal oxide semiconductor (BCDMOS III) technology. This chip contains the following: ■ Ring access relay ■ Scan clamp circuitry ■ Logic control ■ Ring trip ■ Test ■ PPM ■ Thermal shutdown ■ Battery monitor circuit The LILAC family requires a +5 V and battery supply to operate. No –5 V supply is required. A battery switch is included that automatically, based on subscriber loop length, will apply either the primary higher-voltage bat- tery or an optional lower-voltage auxiliary battery. Use of this feature will minimize off-hook power dissipation. The switch point is a function of the user-programmed dc current limit and the magnitude of the auxiliary bat- tery. Switching from the high-voltage to low-voltage battery is quiet, without interruption of the dc loop cur- rent, thus preventing any impulse noise generation at the switch point. Design equations for the switch point and a graph showing loop/battery current versus loop resistance are given in the dc Characteristics section of this data sheet. If the user does not want to provide an auxiliary battery, the design of the L9310 battery switch allows use of a power control resistor at the auxiliary battery input. This scheme will not reduce short-loop, off-hook power dis- sipation, but it will control power dissipation on the SLIC by sharing power among the SLIC, power resis- tor, and dc loop. However, in most cases, without the auxiliary battery, the power dissipation capabilities of the 44-pin PLCC package are adequate so that the power control resistor will not be needed. Design equa- tions for power control options are given in the dc Char- acteristics section of this data sheet. The L9310 has two active transmission ready states, forward active and reverse active. Both on-hook and off-hook transmission are provided during the forward and reverse battery modes. Battery reversal is quiet, without breaking the ac path. Rate of battery reversal may be ramped to control switching time via optional external capacitors. Equations relating rate of battery reversal to these optional external capacitors are given in the dc Characteristics, Power Control section of this data sheet. A low-power scan mode is available to reduce idle mode on-hook power. This mode is realized by using a scan clamp circuit. In low-power scan mode: ■ The scan clamp circuitry is active. ■ Loop closure is active. ■ All ac transmission, dc feed, and other supervision circuits, including ring trip, are shut down. ■ PPM and test are powered down. ■ Thermal shutdown is active. ■ Low battery sense shutdown is on. ■ On-hook transmission is disabled. When the scan clamp circuitry is on, overhead voltage is fixed and not controlled by OVH. When the scan clamp is on, current limit is not controlled by V PROG ; rather, it is set by the internal capabilities of the scan clamp circuit. See the dc Loop Current Limit and Over- head Voltage sections of this data sheet for more details. A forward disconnect mode, where all circuits are turned off and power is denied to the loop, is also pro- vided. During this mode, the NSTAT supervision output will read on hook. In the ring mode, the line break switches are opened and the power ring access switches are closed. In this mode, the ring trip detector in the SLIC is active and all other detectors and the tip/ring drive amplifiers are turned off to conserve power. Make-before-break or break-before-make switching is achievable during ring cadence or ring trip. Toggling directly into or directly out of the ring mode table will give make-before-break switching. To achieve break- before-make switching, go to an intermediate all-off state (use forward disconnect state), before entering the ring mode or before leaving the ring mode. See the Switching Behavior section of this data sheet for more details on switching behavior. Voltage transients or impulse noise associated with ring cadence or ring trip are minimized or eliminated with the L9310, thus possibly eliminating the need for external zero-cross switching circuitry. A tip open switch configuration is also available for ground start applications. A common-mode current detector is included for ground start and ground key applications.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 6 Agere Systems Inc. Description (continued) Both the ring trip and loop closure supervision func- tions are included. Loop closure threshold is set by applying a voltage source to the LCTH input. The volt- age source may be an external voltage source or derived from the SLIC V REF output. A programmable external voltage source may be used to provide soft- ware control of the loop closure threshold. Design equations for the loop closure threshold are given in the Supervision section of this data sheet. Hysteresis is included. The ring trip detector requires only a single-pole filter at the input. This will minimize the required number of external components. To help minimize device power dissipation, the ring trip detector is active only during the power ring mode. Ring trip and loop supervision status outputs appear in a common output pin, NSTAT. NSTAT is an unlatched supervision output; thus, an interrupt-based control scheme may be used. The dc current limit is set in the active modes via an applied voltage source. The voltage source may be an external voltage source. The voltage may be derived via a resistor divider network from the V REF SLIC out- put. A programmable external voltage source may be used to provide software control of the loop closure threshold. Design equations for this feature are given in the dc Characteristics section of this data sheet. Programming range is 10 mA to 70 mA, with a maxi- mum 2.5 Vrms meter pulse at tip and ring. Program- ming range is 10 mA to 45 mA, with a maximum 5 Vrms meter pulse at tip and ring. Overhead is programmable in the active modes via an applied voltage source. The voltage source may be an external voltage source or derived via a resistor divider network from the V REF SLIC output. A programmable external voltage source may be used to provide software control of the overhead voltage. A potential application of this feature is to increase over- head during meter pulse injection and reduce overhead during periods of nonmeter pulse injection. The rate of change of the overhead voltage may be controlled by use of a single external capacitor at the C F1 node. If the rate of change is uncontrolled, there may be audible noise associated with this transition. Design equations for this feature are given in the dc Characteristics sec- tion of this data sheet. If the overhead is not programmed via a resistor, the device develops a default overhead adequate for a 3.14 dBm overload into 900 Ω . For the default over- head, OVH is connected to ground. Overhead is not changed when the PPM input is turned on. Sufficient overhead to pass meter pulse signals must be set at OVH input. The L9310 provides line test capability. In the test mode, a voltage proportional to the ac or dc tip to ground, ring to ground, tip to ring voltage or current may be presented at the SLIC TESTLEV output. An ac test tone may also be applied to a test input, TESTSIG, or through the codec RCVN/RCVP interface. TESTSIG input is active upon entering a test state and remains active after leaving the test mode. By varying the frequency of the applied test tone, parameters such as line capacitance may be measured. TESTSIG should be externally connected to the device’s V REF if it is not used during a test condition. This may be done by a high-impedance pull-up resis- tor. Additionally, TESTSIG should be ac coupled to the test signal generator. Test level outputs at TESTLEV are referenced to the internally generated reference voltage V REF . This refer- ence voltage may also be output at TESTLEV so the users can compensate test results at TESTLEV for the internal reference. Note that during nontest modes, TESTLEV is high impedance to conserve power. Input TESTSIG is turned off during any nontest mode and during the V REF test mode.

July 2001 Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit Agere Systems Inc. 7 Description (continued) The various test modes are achieved through a series of integrated analog switches that can reconfigure the SLIC to provide normal SLIC operation or the appropri- ate test function. Details are given in the Special Func- tions, Line Test section of this data sheet. Test modes are achieved through the device state table. When entering a test mode, the state of the SLIC is unchanged; thus, testing can be done with the SLIC in forward and reverse battery active modes. Addition- ally, via the line break switches associated with the ring relay, use of a tip open or ring open state is used to make single-ended voltage and current measurements. Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in when the LATCH control input goes low. While LATCH is low, the user cannot change the data control inputs. The data control inputs may only be changed when LATCH is high. Incorporation of data latches allows for data control information and loop supervision information to be passed to and from the SLIC via data buses rather than on a per-line basis, thus minimizing routing complexity and board routing area. A device RESET pin is included. When this pin is low, the logic inputs are overridden and the device will be reset into SLIC forward disconnect state and the switch into the all-off state. NSTAT is forced to the on-hook condition when RESET is low. The overall device protection is achieved through a combination of an external secondary protector, along with an integrated thermal shutdown feature, a battery voltage window comparator, the break switch foldback characteristic, and the dc/dynamic current-limit response of the break and tip return switches. For protection against long duration fault conditions, such as power cross and tip/ring shorts, a thermal shut- down mechanism is integrated into the device. Upon reaching the thermal shutdown temperature, the device will enter an all-off mode. Upon cooling, the device will re-enter the state it was in prior to thermal shutdown. Hysteresis is built in to prevent oscillation. During this mode, the NSTAT supervision output overrides the actual loop status and forces an off-hook. The line break switches and tip return switch are current-limited switches. The current-limit mechanism limits current through the switch to the specified dc cur- rent limit under low frequency or dc faults (power cross and/or tip/ring to ground short) and limits the current to the specified dynamic current-limit response under transient faults, such as lightning. A foldover characteristic is incorporated into the line break switches within their I-V curve. Under voltage conditions higher than the normal operating range, such as may be seen under an extreme lightning or power cross fault condition, the line break switch will foldover into a low-current state. This feature allows for more relaxed specifications on the ring side protector, thus allowing for higher-voltage ringing signals. (Tip side protector is limited by the requirements on the tip return switch.) This feature is part of the overall device protection scheme. This device uses a window comparator to force an all- off condition if the battery drops below, or rises above, a specified threshold. Upon loss of V BAT1 , the L9310 will automatically enter an all-off mode. The device will enter this mode if the magnitude of the battery drops below a nominal 15 V and will remain in this mode until the magnitude of the battery rises above a typical 20 V. During this mode, the NSTAT supervision output will override the actual hook status and force an off-hook or logic low. When the device is in the scan mode, because of the design of the scan clamp circuit, common-mode cur- rent can be forced into or out of the battery supply. Because of this, and depending upon power supply design, the magnitude of the battery may rise above the maximum operating condition during extended lon- gitudinal currents or during a power cross fault condi- tion. To prevent excess current from being forced into or out of the battery, if the magnitude of the battery rises typically above 75 V to 80 V, the device will enter an all-off state. The device will remain in the all-off state until the magnitude of the battery drops into the normal operating range. During this mode, the NSTAT supervi- sion output will override the actual hook status and force an off-hook or logic low. See the Protection section of this data sheet for more details on device protection. Please contact your Agere Account Representative for a recommended secondary protection device. Longitudinal balance is consistent with European ETSI and North American GR-909 requirements.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 8 Agere Systems Inc. Description (continued) The L9310 will support the PPM application. A low-volt- age PPM is injected at the PPMIN pin. PPMIN is a high-impedance input that controls the PPM differential voltage on tip and ring. The PPM signal may be present at this pin at all times; however, PPM will only be transmitted to tip and ring during a PPM active mode . Activating or deactivating the PPMIN input will not change the state of the SLIC device. The SLIC may change states while the PPMIN input is active. Design equations relating the magnitude of the PPM signal output at tip and ring to the PPM input signal at PPMIN and information on PPM cancellation are given in the Special Functions, Periodic Pulse Metering sec- tion of this data sheet. No PPM shaping is done by the L9310 device. It is assumed that a shaped PPM input is presented to PPMIN. Maximum allowed PPM and dc current limit are related by the overall drive capabilities of the tip and ring drive amplifiers. These amplifiers can support up to 70 mA dc current limit with a maximum 2.5 Vrms meter pulse signal at tip and ring. These amplifiers can support up to 45 mA dc current limit with a maximum 5 Vrms meter pulse signal at tip and ring. If on-hook transmission of PPM is required, sufficient overhead to accommodate on-hook transmission must be programmed by the user at the OVH input. Over- head is not increased during a PPM active mode. Overhead may be changed during PPM active and PPM not active modes by a change to the voltage pro- grammed at the OVH input. See the Overhead Voltage section of the dc Characteristics section for more detail. Filtering of the meter pulse signal in the transmit direc- tion may be necessary to prevent overload at the codec inputs. Note that PPMOUT is provided as a con- venient point to perform rejection of the meter pulse. Via a resistor from PPMOUT to node ITR, a portion of the PPM signal that is injected to tip and ring is phase inverted and fed back to the transmit path to provide a hybrid cancellation of the meter pulse signal in the transmit direction. This method of hybrid cancellation is adequate for 2.5 Vrms meter pulse. However, for higher-voltage meter pulse, such as 5 Vrms, additional filtering may be necessary. This may be done by a filter network at the TXN input. Transmit and receive gains have been chosen to mini- mize the number of external components required in the SLIC-codec ac interface, regardless of the choice of codec. The L9310 uses a voltage feed, current sense architec- ture; thus, the transmit gain is a transconductance. The L9310 transconductance is set via a single external resistor, and this device is designed for optimal perfor- mance with a transconductance set at 300 V/A. The L9310 offers an option for a single-ended to differ- ential receive gain of either 8 or 2. These options are mask programmable at the factory and are selected by choice of part number. A receive gain of 8 is more appropriate when choosing a first-generation type codec where termination imped- ance, hybrid balance, and overall gains are set by external analog filters. The higher gain is typically required for synthesization of complex termination impedance. A receive gain of 2 is more appropriate when choosing a third-generation type codec. Third-generation codecs will synthesize termination impedance, set hybrid bal- ance, and set overall gains. To accomplish these func- tions, third-generation codecs typically have both analog and digital gain filters. For optimal signal-to- noise performance, it is best to operate the codec at a higher gain level. If the SLIC then provides a high gain, the SLIC output may be saturated, causing clipping dis- tortion of the signal at tip and ring. To avoid this situa- tion with a higher-gain SLIC, external resistor dividers are used. These external components are not neces- sary with the lower gain offered by the L9310. The RCVP/RCVN SLIC inputs are floating inputs. If there is not feedback from RCVP/RCVN to VITR, RCVP/RCVN may be directly coupled to the codec out- put. If there is feedback, RCVP/RCVN must be ac-cou- pled to the codec output. This device is packaged in a 44-pin PLCC surface- mount package.

Figure 1. Architecture Diagram

Table 1. Pin Descriptions to this point to program the loop closure threshold. 3.14 dBm in to 900 Ω ). If the default overhead is desired, connect this pin to ground. ware control of the loop closure threshold. 5C F 2 — Filter Capacitor. Connect a 0.1 µF capacitor from this node to ground for filtering. loop closure filtering is not required, leave this node open. 10 BGND G Battery Ground. Ground return for the battery supply. 12 V BAT1 P Office Battery Supply. Negative high-voltage power supply. 13 V BAT1 P Office Battery Supply. Negative high-voltage power supply. 14 BGND G Battery Ground. Ground return for the battery supply. ational state is chosen. Connect this node to VREF if not used.

Table 1. Pin Descriptions (continued) ence voltage, dependent upon which operational state is selected. 19 RTS I Ring Trip Sense. Sense input for the ring trip detector. 20 RSW O Ring Lead Ringing Access Switch. Ringing relay connects this pin to pin RRING. Connect this pin to pin PR through a 400 Ω current-limiting resistor. overvoltage/current protection. the SLIC to the disconnect state and the switch to the all-off state. 31 LATCH I Latch Control Input. Edge-level sensitive control for data latches. DD P 5 V Digital Power Supply. 5 V supply for digital circuitry. 33 DGND G Digital Ground. Ground return for VDD current. connect a resistor to ground and connect a capacitor to AGND to filter 50 Hz/60 Hz. If unused, the pin is connected to ground. achieved with a network from this node to ITR.

COMBO I codec is also achieved with a network from this node to VTX. the ac differential voltage on tip and ring. differential voltage on tip and ring. 44 V CC P 5 V Analog Power Supply. 5 V supply for analog circuitry.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 14 Agere Systems Inc. Operating States Input State Coding State control is via a tiered logic system. The device must initially be set to a primary control state (B3 = 0). This will set the operational state of the SLIC and switch. The secondary control table (B3 = 1) is used to turn on the PPM amplifier or to turn on the test circuitry and enter a test state. The primary state of the device (the state of the SLIC and switch) will not change when entering a secondary control state. Within the primary control table, each state will set the SLIC and the switch to a specific mode. The exception is the tip-amp and ring-amp states. The tip-amp and ring-amp states will change the configuration of the switches, but leave the state of the SLIC unchanged from the previous primary control mode. Once a primary (device) control state is selected, the PPM or test circuitry can be activated via a secondary control state. Within the secondary control table, there are PPM active modes and test active modes. Upon entering a test active mode in the secondary control table, both TESTLEV output and TESTSIG input are active and the test switches set to the appropriate con- dition. (See Test Architecture Diagram, Figure 2.) An exception is the V REF test active mode. Upon entering VREF , only the TESTLEV output is active, and the inter- nal (2.35 V typical) reference voltage appears at TESTLEV. In the V REF mode, the TESTSIG input is deactivated. Once PPM is on, the user may reverse the battery in the primary state table without turning off PPM. With PPM, if the user goes to the scan, ring, or disconnect mode in the primary table, PPM will be turned off. Unlike PPM, the test feature, once on, will remain on if the user transitions to forward active, reverse active, scan, ring, or disconnect state in the primary state table. PPM or test is deactivated by selecting PPM/test off in the secondary control table. Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in when the LATCH control input goes low. Data must be set up 200 ns before LATCH goes low and held 50 ns after LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, B2, and B3. The data control inputs at B0, B1, B2, and B3 may only be changed when LATCH is high. NSTAT supervision output is not controlled by the LATCH control input.

Table 2. Primary Control States Table 3. Secondary Control States Table 4. Supervision Coding

00001 S c a n

00011 P o w e r u p , f o r w a r d b a t t e r y

00101 P o w e r u p , r e v e r s e b a t t e r y

00111 T i p and ring amp

01001 R i n g

01011 T i p a m p

01101 R i n g a m p

01111 D i s c onnect, break before make

1000 T e s t T E S T L E V , T E S T S I G T i p / r i n g v o l t a g e

1001 T e s t T E S T L E V , T E S T S I G T i p v o l t a g e

1010 T e s t T E S T L E V , T E S T S I G R i n g v o l t a g e

1011 T e s t T E S T L E V , T E S T S I G V T X —current

1100 T e s t T E S T L E V V

1101 T e s t T E S T L E V , T E S T S I G V I T R — c u r r e n t

1110 P P M P P M I N , P P M O U T P P M O n

1111 P P M P P M O f f P P M O f f / T E S T O f f

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 16 Agere Systems Inc. State Definitions Primary Control Modes Powerup, Forward Battery ■ Normal talk and battery feed state. ■ Pin PT is positive with respect to pin PR. ■ All ac transmission and dc feed circuits are powered up. ■ On-hook transmission is enabled. ■ Thermal shutdown is active. ■ Battery window comparator sense shutdown is on. ■ Switch break switches (SW1 and SW2) are closed, and ring access switches (SW3 and SW4) are open. ■ VBAT1 is applied to tip and ring during on-hook condi- tions. ■ Automatic battery switch selects VBAT1 or VBAT2 dur- ing off-hook conditions. ■ All supervision circuits except for ring trip detector are active. ■ Overhead is set via pin OVH. ■ TESTLEV output is in the high-impedance mode, and TESTSIG input is off unless this feature is selected via the secondary control table. ■ PPMOUT is in the high-impedance mode, and PPMIN input is off unless this feature is selected via the secondary control table. ■ NSTAT represents the loop closure detector status. Powerup, Reverse Battery ■ Normal talk and battery feed state. ■ Pin PR is positive with respect to pin PT. ■ All ac transmission and dc feed circuits are powered up. ■ On-hook transmission is enabled. ■ Thermal shutdown is active. ■ Battery window comparator sense shutdown is on. ■ Switch break switches (SW1 and SW2) are closed, and ring access switches (SW3 and SW4) are open. ■ VBAT1 is applied to tip and ring during on-hook condi- tions. ■ Automatic battery switch selects VBAT1 or VBAT2 under off-hook conditions. ■ All supervision circuits except for ring trip detector are active. ■ Overhead is set via pin OVH. ■ TESTLEV output is in the high-impedance mode, and TESTSIG input is off unless this feature is selected via the secondary control table. ■ PPMOUT is in the high-impedance mode, and PPMIN input is off unless this feature is selected via the secondary control table. ■ NSTAT represents the loop closure detector status. Scan ■ Scan clamp circuitry is active. ■ Loop closure is active. ■ All ac transmission, dc feed, and other supervision circuits, including ring trip, are shut down. ■ PPM is powered down. ■ Thermal shutdown is active. ■ Battery window comparator sense shutdown is on. ■ On-hook transmission is disabled. ■ Pin PT is positive with respect to PR, and VBAT1 is applied to tip/ring. ■ Switch break switches (SW1 and SW2) are closed, and ring access switches (SW3 and SW4) are open. ■ When the scan clamp circuitry is on, overhead volt- age is fixed and not controlled by OVH. Also the cur- rent limit is not the normal current limit set at V PROG . ■ NSTAT represents the loop closure detector status. Ground Start ■ Tip amplifier is on, tip break switch is open. ■ The device presents a high impedance (>100 kΩ ) to pin PT and a current-limited battery (VBAT2 ) to PR. ■ Common-mode current detector is on. ■ Ring trip detector is off. ■ Output TRGDET indicates current flowing in the ring lead. ■ This is not a defined state in the primary control mode table. It is achieved via the powerup and the ring amp states in the primary control mode table.

July 2001 Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit Agere Systems Inc. 17 State Definitions (continued) Primary Control Modes (continued) Ringing ■ Switch break switches (SW1 and SW2) are open, and ring access switches (SW3 and SW4) are closed. ■ Tip/ring drive amplifiers are powered down. ■ Ring trip circuit is active. ■ Loop supervision and common-mode current detec- tors are powered down. ■ NSTAT represents the ring trip detector status. Disconnect— Break Before Make ■ The tip and ring amplifiers are turned off to conserve power. ■ Break switches (SW1 and SW2) are open, and ring access switches (SW3 and SW4) are open. This mode is also used as a transitional mode to achieve break-before-make switching from the power ring to active or scan mode. ■ All supervision circuits are powered down; NSTAT overrides the actual loop condition and is forced high (on-hook). Tip Amp ■ Tip side break switch is closed, and ring side break switch and ring access switches are open. ■ SLIC mode is unaffected by reconfiguring the ring relay via this mode; thus, SLIC will remain in the mode it was in prior to selecting this mode. Ring Amp ■ Ring side break switch is closed; tip side break switch and ring access switches are open. ■ SLIC mode is unaffected by reconfiguring the ring relay via this mode; thus, SLIC will remain in the mode it was in prior to selecting this mode. Tip and Ring Amp ■ Tip and ring side break switches are open; ring access switches are open. ■ SLIC mode is unaffected by reconfiguring the break switches via this mode; thus, SLIC will remain in the mode it was in prior to selecting this mode. ■ This is the calibration mode for differential and sin- gle-ended tip/ring current measurements. Reset ■ Selection of device reset via the RESET pin will set the device into the disconnect break-before-make state. Secondary Control Mode States Voltage: Tip to Ground ■ A voltage proportional to the tip to ground voltage appears at the TESTLEV output. ■ TESTSIG input is on. ■ Customer applies ac test tone or VREF to TESTSIG to select an ac or dc measurement. Voltage: Ring to Ground ■ A voltage proportional to the ring to ground voltage appears at the TESTLEV output. ■ TESTSIG input is on. ■ Customer applies ac test tone or VREF to TESTSIG to select an ac or dc measurement. Voltage: Tip to Ring ■ A voltage proportional to the differential tip to ring voltage appears at the TESTLEV output. ■ TESTSIG input is on. ■ Customer applies ac test tone or VREF to TESTSIG to select an ac or dc measurement.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 18 Agere Systems Inc. State Definitions (continued) Secondary Control Mode States (continued) Current: Tip to Ring—VTX ■ A voltage proportional to the ac, plus dc tip to ring dif- ferential current, tip to ground current, or ring to ground current appears at the TESTLEV output. Use this state for dc measurements. ■ Choice is determined by primary control mode table. ■ Differential current is selected by choosing powerup forward or reverse from the primary control mode table. ■ Tip to ground or ring to ground current is selected by first choosing powerup forward or reverse from the primary mode table, and then choosing tip amp or ring amp from the primary mode table. ■ TESTSIG input is on. ■ Customer applies ac test tone or VREF to select an ac or dc measurement. Current: Tip to Ring—VITR ■ A voltage proportional to the ac tip to ring differential current, tip to ground current, or ring to ground cur- rents, appears at TESTLEV output. Use this state for ac measurements. ■ Choice is determined by primary control mode table. ■ Differential current is selected by choosing powerup forward or reverse from the primary control mode table. ■ Tip to ground or ring to ground current is selected by first choosing powerup forward or reverse from the primary mode table, and then choosing tip amp or ring amp from the primary mode table. ■ TESTSIG input is on. ■ Customer applies ac test tone or VREF to select an ac or dc measurement. Reference Voltage ■ A voltage proportional to the internal dc reference voltage VREF appears at the TESTLEV output. ■ TESTSIG input is off. ■ This is the calibration state for voltage measure- ments. PPM On ■ The PPMIN input is activated and the PPM signal at PPMIN is transmitted to tip and ring. ■ Device mode per primary control mode table. Once PPM is active, transition to the scan, disconnect, or ring modes in the primary state table will deactivate PPMIN. Transition to forward battery, reverse battery, ring amp, or tip amp state will not deactivate PPMIN. PPM Off/TEST Off ■ The PPMIN input is deactivated and the PPM signal at PPMIN does not appear at tip and ring. ■ PPMOUT is high impedance. ■ Device mode is per primary control mode table. ■ The TESTSIG input is deactivated. ■ TESTLEV output is high impedance. ■ Device mode is per primary control mode table. Special States Thermal Shutdown ■ Not controlled via truth table inputs. ■ This mode is caused by excessive heating of the device, such as may be encountered in an extended power cross situation. ■ Upon reaching the thermal shutdown temperature, the device will enter an all-off mode. ■ Upon cooling, the device will re-enter the state it was in prior to thermal shutdown. ■ Hysteresis is built in to prevent oscillation. In this mode, supervision output NSTAT is forced low (off-hook) regardless of loop status or if the discon- nect logic state is selected.

July 2001 Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit Agere System s Inc. 19 State Definitions (continued) Special States (continued) Battery O ut of R ange ■ N ot controlled via truth table inputs. ■ This mo de is caused by a battery out of range; that is, the battery voltage rising above or below a specified threshold. ■ U pon reaching the specified high or low battery voltage, the device will enter an all-off mode. ■ U pon the battery returning to the specified normal operating range, the device w ill re-enter the state it w as in prior to the low battery shutdow n. ■ Hysteresis is built in to prevent oscillation. In this m ode, supervision output NS TAT is forced low (off-hook) regardless of loop status or if the disconnect logic state is selected. Absolute M aximum Ratings (at TA = 25 °C) Stresses in excess of the absolute maximum ratings can cause perm anent dam age to the device. These are abso- lute stress ratings only. Functional operation of the device is not im plied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maxim um ratings for extended periods can adversely affect device reliability. N ote:The IC can be dam aged unless all ground connections are applied before, and remo ved after, all other connections. Furtherm ore, w hen pow ering the device, the user m ust guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. For exam ple, inductance in a supply lead could resonate w ith the supply filter capacitor to cause a destructive overvolt- age. Param eter Sym bol M in M ax U nit 5 V dc Supplies (VC C + VDD ) — –0.5 7.0 V High Office Battery Supply (VBAT1) — –75 0.5 V Auxiliary Office Battery Supply (V BAT2) — — VBAT1 to 0.5 V V Ringing Voltage — — 110 Vrm s Logic Input Voltage — –0.5 VCC + 0.5 V V Max imum Junction Tem perature — — 165 °C Storage Tem perature R ange — –40 125 °C Re lative Hum idity Ra nge — 5 95 % Sw itch 1, 2, 3; Pole to Pole — — 320 V Sw itch 4; Pole to Pole — — 465 V Sw itch Input to O utput — — 320 V

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 20 Agere Systems Inc.

Electrical Characteristics

In general, minimum and maximum values are testing requirements. However, some parameters may not be tested in production because they are guaranteed by design and device characterization. Typical values reflect the design center or nominal value of the parameter; they are for information only and are not a requirement. Minimum and maximum values apply across the entire temperature range (–40 °C to +85 °C) and entire battery range (–36 V to –70 V). Unless otherwise specified, typical is defined as 25 °C, V CC = VDD = 5.0, VBAT1 = –48 V VBAT2 = –25 V. Positive currents flow into the device. Table 5. Device Operating Conditions and Powering

• Not to exceed 26 grams of water per kilogram of dry air.

Table 6. Ring Trip Detector

1. The ringing source may be either of the following:

a.) The ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. b.) The ringing source consists of only the ac voltage (earth-backed ringing); the ringing return is the dc voltage.

1. NDET must also indicate ring trip when the ac ringing voltage is absent (<5 Vrms) from the ringing source.
2. Pretrip ringing must not be tripped by a 10 kΩ resistor in parallel with an 8 µF capacitor applied across tip and ring.

Table 7. PPM

1. PPM signal should be ac coupled into PPMIN.
2. This parameter is not tested in production, it is guaranteed by design and characterization.

Table 8. ac Test Source

1. ac test signal should be ac coupled into TESTSIG.
2. A pull-down resistor to VREF should be connected to TESTSIG.
3. This parameter is not tested in production, it is guaranteed by design and characterization.

Table 9. Test Sense

1. This is the voltage coefficient with respect to tip/ring voltage. See Table 21 TESTLEV Output Options (Tip-to-Ring, Tip-to-Ground, and Ring-

to-Ground equations) for application of this parameter.

1. This parameter is not tested in production, it is guaranteed by design and characterization.

Table 10. SLIC Two-Wire Port

Table 10. SLIC Two-Wire Port (continued)

• Guarantees 46 dB from 300 Hz to 3.4 kHz, with 50 Ω , 1% protection, resistors into a complex resistive termination impedance.

† IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

300 Hz to 600 Hz

200 Hz to 4000 Hz 40 — — dB

Table 11. Analog Pin Characteristics

• This parameter is not tested in production. It is guaranteed by design and device characterization.

Table 12. ac Feed Characteristics

1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between

150 Ω and 1400 Ω can be synthesized.

1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 6.34 kΩ , the recommended value. Positive cur-

rent is defined as the differential current flowing from PT to PR.

200 Hz—300 Hz

Table 13. Logic Inputs and Outputs Table 14. Timing Requirements LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, B2, and B3. put is not controlled by the LATCH control input. Figure 4. Timing Requirements

Table 15. Break Switches (SW1, 2)

1. At 25 °C, maximum voltage rating has a temperature coefficient of 0.167 V/°C.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.

Table 16. Ring Return Switch (SW3) 1.At 25 °C, maximum voltage rating has a temperature coefficient of 0.167 V/°C.

1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.

Table 17. Ringing Access Switch (SW4)

1. Choice of secondary protector and feed resistor should ensure these ratings are not exceeded. A minimum 400 Ω feed resistor is recom-
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.

Figure 5. On-State Switch I-V Characteristics

Figure 6. Basic Test Circuit

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 32 Agere Systems Inc. Under normal device operating conditions, thermal design must ensure that the device temperature does not rise above the thermal shutdown. Power dissipation is highest with higher battery voltages, with higher cur- rent limit, and under shorter dc loop conditions. Higher ambient temperature will reduce thermal margin. Power control may be done in several ways, by use of the integrated automatic battery switch and a lower- voltage auxiliary battery or by use of a power control resistor with single battery operation. The thermal capability of the 44-pin PLCC package is sufficient to allow for single battery operation without the power control resistor when the device is used under lower- power operating conditions. Power Derating Operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop length, and protection resistors’ values, number of PCB board lay- ers, and airflow, will influence the overall thermal per- formance. The still-air thermal resistance of the 44-pin PLCC package is typically 38 °C/W for a two-layer board with 0 LFPM airflow. The L9310 will enter thermal shutdown at a tempera- ture of 150 °C. The thermal design should ensure that the SLIC does not reach this temperature under normal operating conditions. For this example, assume a maximum ambient operat- ing temperature of 85 °C, a maximum current limit of 30 mA, and a maximum battery of –56 V. Further assume a (worst-case) minimum dc loop of 20 Ω for wire resistance, 50 Ω protection resistors, and 200 Ω for the handset. Include the effects of parameter toler- ance in these calculations. T TSD – TAMBIENT(max) = allowed thermal rise 150 °C – 85 °C = 65 °C Allowed thermal rise = package thermal impedance x SLIC power dissipation 65 °C = 38 °C/W x SLIC power dissipation Allowed SLIC power dissipation (P D ) = 1.71 W Thus, in this example, if the total power dissipated on the SLIC is less than 1.71 W, it will not enter thermal shutdown. Total SLIC power is calculated: Total P D = maximum battery x (maximum current limit) (current limit accuracy) + SLIC quiescent power. For the L9310, the worst-case SLIC on-hook active qui- escent power is 100 mW. Thus, Total off-hook power = (ILOOP )(1.05) x (VBATAPPLIED ) + SLIC quiescent power Total off-hook power = (0.030 A)(1.05) x (52) + 100 mW Total off-hook power = 1.864 W The power dissipated in the SLIC is the total power dis- sipation less the power that is dissipated in the loop. SLIC P D = total power – loop power Loop off-hook power = (ILOOP x 1.05)2 x (RLOOPdcmin + 2R P + RHANDSET ) Loop off-hook power = {(0.030 A)(1.05)}2 x (20 Ω + 100 Ω + 200 Ω ) Loop off-hook power = 317.5 mW SLIC off-hook power = total off-hook power – loop off- hook power SLIC off-hook power = 1.864 W – 0.3175 W SLIC off-hook power = 1.5465 W < 1.71 W Thus, under the operating conditions of this example, the thermal capability of the 44-pin PLCC package is adequate to ensure that the L9310 will not be driven into thermal shutdown and no additional power control measures are needed. If, however, for a given set of operating conditions, the thermal capabilities of the package are not adequate to ensure the SLIC is driven into thermal shutdown, then one of the power control techniques described below should be used. Addition- ally, even if the thermal capability of the 44-pin PLCC package is adequate to ensure that the L9310 will not be driven into thermal shutdown, the battery switch technique described below can be used to reduce total short-loop power dissipation.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 34 Agere Systems Inc. Applications (continued) dc Characteristics (continued) Power Control Resistor Device temperature rise may be controlled with use of a single battery voltage by use of a power control resis- tor. This technique will reduce power dissipation on the chip, by sharing the total power not dissipated in the loop between the L9310 and the power control resistor. It does not, however, reduce the total power con- sumed, as does use of the auxiliary battery. The power control resistor is connected from the primary battery to the V BAT2 /PWR node of the device. The magnitude of the power control resistor must be low enough to ensure that sufficient power is dissipated on the resistor to ensure the L9310 does not exceed its thermal shutdown temperature. At the same time, the more power that is dissipated by the power control resistor, the higher the resistor’s power rating must be, and thus, the more costly the resistor. The following equations are used to optimize the choice (magnitude and power rating) of the power control resistor. Again assume: T TSD – TAMBIENT(max) = allowed thermal rise 150 °C – 85 °C = 65 °C Allowed thermal rise = package thermal impedance x SLIC power dissipation 65 °C = 38 °C/W x SLIC power dissipation Allowed SLIC power dissipation (P D ) = 1.71 W This time, assume a maximum ambient operating tem- perature of 85 °C, a maximum current limit of 45 mA (including tolerance), and a maximum battery of –56 V. Again, assume a (worst-case) minimum dc loop of 0 Ω and that 50 Ω protection resistors are used. Assume the handset is 200 Ω : Total PD = (56 V x 45 mA) + 0.100 W Total PD = 2.34 W + 0.100 W Total PD = 2.4375 W Again, the power dissipated in the SLIC is the total power dissipation less the power that is dissipated in the loop. SLIC P D = total power – loop power Loop power = (ILIM)2 x (RLOOPdcmin + 2RP + RHANDSET ) Loop power = (45 mA)2 x (0 Ω + 100 Ω + 200 Ω ) Loop power = 0.6075 W SLIC power = 2.4375 W – 0.6075 W SLIC power = 1.83 W > 1.5 W Under these extreme conditions, thermal margin is increased via an external power control resistor. The power dissipated in the power control resistor is calculated by: PPRW = where in this example: PPRW is power in the resistor VBAT = –52 V VLOOP = ILIM * (RLOOP + RPROT ) VROH is the ring-side overhead voltage of the SLIC. Since this device is dc unbalanced, the tip side over- head will remain typically at –2 V and the ring side over- head will vary with the voltage at V OH . For the total tip/ ring default overhead of 5.5 V, the ring overhead is typi- cally 3.5 V. dc Loop Current Limit In the active modes, dc current limit is programmable via an applied voltage source at the device’s V PROG control input. The voltage source may be an external voltage source or derived via a resistor divider network from the VREF SLIC output or an external voltage source. A programmable external voltage source may be used to provide software control of the loop current limit. The loop current limit (I LIM) is related to the VPROG voltage by: ILIM (mA) = 50 x VPROG (V) V BAT V ROH– V LOOP–() 2 R PWR

accuracies are specified in Table 9 and Table 10. the active mode) upon an on- to off-hook transition. Table 18. Typical Active Mode On- to Off-Hook Tip/ clamp circuit versus the active tip/ring drive amplifiers. provide software control of the overhead voltage. achieved by shorting input pin OVH to analog ground. thought of as an internal saturation voltage. nal saturation voltage for signal swing.

Figure 14. L9310 Loop Current vs. Loop Voltage battery voltage less the overhead voltage of the device. plate has a high resistance (10 kΩ ). low-voltage battery (if auxiliary battery option is used). Table 19. FB1 and FB2 Values vs. Typical the Electrical Characteristics section of this data sheet. LCTH is ground or an external voltage source.

250 VREF V LCTH–()

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 38 Agere Systems Inc. Supervision (continued) Ring Trip Ring trip is set by the value of RS1. The ring trip threshold at the ring trip inputs is ±2.5 V minimum, ±3.5 V maximum. A resistor value of 400 Ω , as shown in Figure 4, will set the ring trip current threshold to ±7.5 mA typical. Ring trip is asserted upon entering the ringing mode until the second zero crossing of ringing. This is either a positive-going zero crossing (between –40 V and –30 V at –50 V VBAT ) or a negative-going zero crossing (between –10 V and –20 V at –50 V VBAT ). The different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 V. The act of turning on the switch may or may not produce a ringing zero crossing, therefore, there may be a delay of up to almost one cycle of ringing or 50 ms until NSTAT is high. Ring trip will not be asserted unless the ring trip thresh- old is exceeded for two zero crossings. This is either a positive-going zero crossing (between –40 V and –30 V at –50 V V BAT ) or a negative-going zero crossing (between –10 V and –20 V at –50 V VBAT ). The different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 V. Note that since the ringing voltage is monitored at RSW, one zero crossing can occur at switch turn-on depending on initial conditions. Ring trip is asserted immediately if the ring trip input is 15 V ± 3 V. Tip or Ring Ground Detector In the ground key or ground start applications, a com- mon-mode current detector is used to indicate that either a tip or ring ground has occurred (ground key) or an off-hook has occurred (ground start). The detection threshold is set by connecting a resistor from ICM to ground. 2350/R ICM (kΩ ) = ITH (mA) Additionally, a filter capacitor across RICM will set the time constant of the detector. No hysteresis is associ- ated with this detector. Switching Behavior The solid-state ring relay in the L9310 device is able to provide either make-before-break or break-before- make timing with respect to switching into and out of the ring mode. If switching is done directly into and out of the ring mode, the design of the L9310 will give make-before-break switching with respect to both the ring and tip side switches. To achieve break-before- make switching, the user should, via software control, enter an intermediate all-off mode when switching into and out of the ring mode. The all-off state should be held a minimum of 8 ms. Make-Before-Break Operation The break switches are constructed from DMOS tran- sistors. The tip side ring return is also a DMOS transis- tor. Because the on resistance of the break switches is less than the tip side ring return switch, the break switches are physically bigger. This implies a larger gate to source capacitance, with inherently slower switching speeds since it will take longer to charge or discharge the gate to source capacitance of the break switches (to change the state of the switch). The ring access switch is a pnpn type device. The pnpn device has inherently faster switching speeds than any of the DMOS type switches. Going from the active to ring mode, the smaller tip side ring return switch and the pnpn ring access switch will change states before the larger break switches. Thus, the ring contacts are made before the line break switches are broken: make-before-break operation. Going from the ring mode to active or scan, the natural tendency is for the smaller tip side ring return DMOS to break or open, before the larger DMOS can turn on. This would not be make-before-break operation on the tip side. Thus, circuitry is added to speed up charging of the tip break switch, to speed up the turn on of that switch to give make-before-break operation on the tip side. On the ring side, going from the ring mode to the active or scan mode, the pnpn will not turn off until the ring current drops below the hold current of the pnpn device (which is typically 500 µA); this is effectively zero cur- rent for zero current turn off. This can take up to one- half cycle of ringing to occur. With this inherent delay in switching by the pnpn ring access switch, the break switches will make contact before the ring access switch breaks contact; so again, make-before-break switching is achieved.

overall system or ring generator and battery design. sequence device switching as shown below. Table 20. Break-Before-Make Logic Control a recommended protection device. minimum 50 Ω is recommended in tip and ring.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 40 Agere Systems Inc. Protection (continued) External Protection (continued) The overall device protection is achieved through a combination of the external overvoltage and overcur- rent devices, along with the integrated thermal shut- down feature, the integrated window comparator, the break switch foldback characteristic, and the dc/dynamic current-limit response of the break and tip return switches. Active Mode Response at PT/PR The line break switches and tip return switch are cur- rent-limited switches. The current-limit mechanism lim- its current through the switch to the specified dc current limit under low frequency or dc faults (power cross and/or tip-ring to ground short) and limits the current to the specified dynamic current-limit response under transient faults, such as lightning. During a lightning fault (typical 1000 V 10 x 700 µs applied surge), the current-limited line break switches will pass typically 2.5 A for 0.5 µs before forcing the break switches off. Once in the off state, the external protection device must ensure that the off-state voltage rating of 320 V is not exceeded. Note that the maxi- mum differential voltage is the positive zener rating of the protection device less the battery voltage, which will appear on the line feed side of the switch. For a lower-voltage power cross, whose maximum peak voltage is below the foldback voltage breakpoint 1 (V1), the current-limited break switch will pass the cur- rent equal to the dc current limit. The current limit has a negative temperate coefficient, so as the device contin- ues to pass current, the current limit will reduce with increasing device temperature. Ultimately, the device will reach the thermal shutdown temperature and the thermal shutdown mechanism will force an all-off state, which will stop current flow and begin device cooling. In the all-off state, the external protection device ensures that the switch off-state voltage rating is not exceeded. Once the device cools significantly, the break switches will turn on, and current will begin to flow again, until temperature forces the all-off state. This will continue until the fault condition is gone. Sneak-under surge is a voltage surge that is just below the clamping threshold of the secondary protection device. For this type of surge, when the surge voltage is below the foldback voltage breakpoint 1, operation is as described above. When the surge voltage rises above the foldback voltage breakpoint 1 (V1), but is still less than the secondary protector clamping voltage, the line break switch will crowbar into the high-impedance region of its I-V characteristic and reduce current to the specified I LIMIT2 value. For surges whose magnitude range above the trigger of the external secondary protector, the device will operate as described above for the portion of the surge below the secondary protector trigger voltage. When the voltage rises above the external secondary protec- tor’s trigger voltage, the secondary protector will crow- bar on, shunting fault current to ground and reducing the tip/ring voltage seen at the device. In the active mode, the external secondary protector must ensure that the off-state voltage ratings of the ring access and ring return switch are not exceeded. Nor- mally, the ring return switch is connected to ground on the TRING side and to the protector on the PT side; thus, the protector on the tip side in the active mode must clamp at less than 320 V. As will be seen in the Ring Mode Response at PT/PR section, during the power ringing mode, this clamp voltage on the tip side is significantly less than 320 V. Normally, the ring access switch is connected to the ring generator on the RRING side and to the protector on the PR side; thus, on one side of the switch, there is the battery voltage and the peak negative ring signal, and on the PR side, the maximum turn-on voltage of the secondary protector. The ring access switch is of pnpn construction. Thus, if the off-state voltage rating of the ring access switch is exceeded, the device will crowbar into a low-impedance state. This will cause a surge into the ring generator and can cause the on- state current rating of the switch to be exceeded. The difference of the battery plus peak negative ring signal voltage less the maximum turn on of the second- ary protector must not exceed the off-state voltage rat- ing of the ring access switch. Additionally, as the secondary protector will see the power ring signal, the minimum turn-on rating of the secondary protector must be high enough to not clamp the ring signal and cause clipping distortion. The ring side will see the full power ring voltage, and the tip side switch will see the power ringing voltage that is attenuated by the ringing load, subscriber loop, feed resistor, and protection resistors; thus, the ring side secondary protector requires a higher clamping voltage than the tip side.

July 2001 Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit Agere Systems Inc. 41 Protection (continued) Ring Mode Response at PT/PR In this mode, the line break switches are off and the ring access and ring return switch is on. The secondary protectors must ensure that the minimum off-state volt- age rating of the line break switches is not exceeded. Note that the maximum differential voltage is the posi- tive zener rating of the protection device less the bat- tery voltage which will appear on the line feed side of the switch. The ring access switch is a pnpn type switch. This switch has no internal current limiting. Thus, through external current limit, the user must ensure that the surge ratings (both dynamic and dc for lightning and power cross faults) are not exceeded. A minimum 400 Ω ring feed resistor is recommended. This resistor also will set the ring trip threshold. See the Ring Trip section within the Supervision section of this data sheet. During a lightning fault (typical 1000 V 10 x 700 µs applied surge), the current-limited tip return switch will pass, typically 2.5 A for 0.5 µs before forcing the switch off. Once in the off state, the external protection device must ensure that the off-state voltage rating of 320 V is not exceeded. For power cross for lower-voltage faults, the tip side power ringing return switch will behave like the line break switches. However, this switch does not have the foldback clamping feature that is included in the line break switches; thus, in the on state, the voltage seen by the tip side power ringing return switch before dam- age is less than the line break switches. The on-state voltage of the line break switches can go up to the off- state voltage rating. The tip side power ringing return voltage should see less than 130 V in the on state. Thus, the secondary protector on the tip side should have a maximum crowbar voltage of 130 V. With typical protection device tolerance, this implies a minimum clamping voltage of 100 V. The users should ensure, based on minimum loop length, ringing load, and peak ring signal voltage, that the ring signal is not distorted by the (lower) voltage rating of the tip-side protector. Internal Tertiary Protection The external secondary protector and switch current limit protect the 320 V high-voltage switches from light- ning and power cross conditions. Integrated into the LILAC IC is an internal tertiary protection scheme that is meant to protect the 90 V SLIC portion of the device from residue fault current and voltages that may be passed through the switches to the actual SLIC inputs. This scheme includes an internal diode bridge voltage clamp and a battery out of range detector that forces an all-off condition if the battery voltage falls high or low out of the specified operating range. Diode Bridge The internal inputs of the actual SLIC chip are clamped to ground and to V BAT1 by an integrated diode bridge. Residual positive fault currents are clamped to ground and residual negative fault currents are clamped to bat- tery. This implies that the battery have some current- sinking capability. High common-mode currents, as may be seen under a fault condition, will be sensed and reduced to zero by the battery monitor circuit (see Battery Out of Range Detector: High [Magnitude] section). However, this detector will not prevent longitudinal current from flow- ing into battery. The battery supply must have the abil- ity to sink longitudinal currents as specified in the longitudinal current capability requirement in Table 10. Battery Out of Range Detector: High (Magnitude) This feature is useful in remote power applications where a dc-dc converter with limited ability to sink cur- rent is used as the primary battery supply. Under a fault condition, the diode bridge will want to sink current into the battery. As a function of the dc-dc converter input capacitance and design, this current may cause the magnitude of supply voltage to rise and ultimately cause damage to the supply. To prevent damage to the supply, the LILAC device will monitor the battery supply voltage. If the magnitude of the battery rises above the maximum specified operating battery, the battery out of range detector will force the line break switches and ring access switches into an all-off state, and will also force the SLIC into the disconnect state. This will stop the current flow into the battery, preventing damage to the battery fault conditions. NSTAT is forced low during this mode of operation. Battery Out of Range Detector: Low (Magnitude) The LILAC device will monitor the battery supply volt- age. If the magnitude of the battery drops below the minimum specified operating battery, the battery out of range detector will force the line break switches and ring access switches into an all-off state, and will also force the SLIC into the disconnect state. NSTAT is forced low during this mode of operation.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 42 Agere Systems Inc. Special Functions Periodic Pulse Metering (PPM) Periodic pulse metering (PPM), also referred to as TTX, is input to the PPMIN input of the L9310. Upon application of appropriate logic control, this signal is presented to the tip/ring subscriber loop. The state of the L9310 may be changed while applying PPM sig- nals. The L9310 assumes that a shaped PPM signal is applied to the PPMIN input. Sufficient drive current is available in the tip and ring drive amplifiers to support 2.5 Vrms PPM signals into a 200 Ω load with a 70 mA dc current limit, and a 5 Vrms PPM signal into a 200 Ω load with a 45 mA dc current limit. PPM input signals may be a maximum 1.25 V at PPMIN. The gain from PPMIN to tip/ring is 10. Thus, for 2.5 Vrms at tip and ring, apply a 0.25 Vrms signal at PPMIN. The PPM signal should be ac coupled to PPMIN through a 0.01 µF capacitor. When applied to tip and ring, the PPM signal will also be returned through the SLIC and will appear at the SLIC VITR output. The concern is that this high-voltage signal can overload the codec input and cause distor- tion of the (desired) ac signal. Therefore, some sort of PPM rejection scheme must be employed. Refer to Figure 1, Architecture Diagram. The L9310 outputs pin PPMOUT, which is the output of the PPM input ampli- fier. Connecting a resistor, R PPM, from PPMOUT to node ITR will provide a path for a hybrid reject of the returned meter pulse signal. The return path from tip and ring to VITR for the PPM signal is through the internal AX amplifier. ITR is the input to this amplifier. Through R PPM , by applying a PPM signal equal in mag- nitude, but 180 degrees out of phase to the returned PPM signal at ITR, the PPM signal is cancelled, pre- venting overload at the codec input. Even if the cancel- lation is not perfect, the idea is to reduce the PPM signal so as not to overload the codec. Codecs typi- cally have a low-pass filter at their input to reject any residual meter pulse signal. The value of R PPM is selected by: R PPM = [{(VPPMIN x 10)/(RPPMLOAD + Rdc + 2RP)}/324.5]–1 In the case of very high meter pulse signals, such as

5 Vrms, the cancellation provided by resistor R

not be sufficient to prevent overload at the codec input. In this case, additional filtering/rejection may be neces- sary. PPM injection can cause false loop closure indication. Connect a 0.01 µF capacitor from this node LCF to V CC to filter the loop closure detector. If loop closure filtering is not required, leave LCF open. Line Test The L9310 provides line test capability. Through a series of integrated analog switches, in the test mode, an analog voltage proportional to the dc tip to ground voltage, dc ring to ground voltage, the differential dc tip to ring voltage may be generated at the SLIC TESTLEV output. Additionally, an analog voltage pro- portional to the dc tip to ground current, dc ring to ground current, the differential dc tip to ring current may also be generated at the SLIC TESTLEV. Figure 2 shows the architecture of the integrated test switches. The test switches are configured via the logic input table to provide voltage measurements, tip to ground, ring to ground, and tip to ring. A voltage that is proportional to the ac tip/ring current appears at the VITR output; thus, for ac current measurements, the test switches apply the VITR output to the TESTLEV output. A voltage that is proportional to the ac plus dc tip/ring current appears at the VTX output; thus, for dc current measurements, the test switches apply the VTX output to the TESTLEV output, with TESTSIG input grounded. Differential tip to ring current is achieved via the logic truth table. Additionally, individual control of the line break switches allows tip to ground current measure- ments (tip break switch closed, ring break switch open, tip amp state) or ring to ground current measurements (tip break switch open, ring break switch closed, ring amp state). An analog ac test tone may also be applied to a test input TESTSIG. TESTSIG input is active upon entering a test state and remains active until leaving the test mode. Using this feature, a voltage proportional to ac tip to ground voltage, ac ring to ground voltage, the dif- ferential ac tip to ring, the ac tip to ground current, ac ring to ground current, the differential ac tip to ring cur- rent may also be generated at the SLIC TESTLEV. By varying the frequency of the applied test tone, parame- ters such as line capacitance may be measured. If the codec can accommodate self-test features, the L9310 can be configured to operate in this mode. Dur- ing the test modes, the L9310 receive path is active; thus, a test tone may be applied at the RCVN/RCVP inputs, through the codec, via a PCM input. In this mode of operation, couple TESTLEV, not VITR, to the codec.

VREF itself will appear at the TESTLEV output. VREF and subtract VREF from VTESTLEV . under on-hook (open-loop) conditions. device's VREF if it is not used during a test condition. ous line voltages and currents. Table 21. TESTLEV Output Options amp for single-ended current measurement calibration.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 44 Agere Systems Inc. ac Applications ac Parameters There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is done from the PCM highway to the transmit port. Transmit and receive gains may be specified in terms of an actual gain, or in terms of a transmission level point (TLP), that is, the actual ac transmission level in dBm. Finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. Codec Types At this point in the design, the codec needs to be selected. The interface network between the SLIC and codec can then be designed. Below is a brief codec feature summary. First-Generation Codecs. These perform the basic filtering, A/D (transmit), D/A (receive), and µ-law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid bal- ance (cancellation at the summing node). Depending on the type, some have differential analog input stages, differential analog output stages, +5 V only or ±5 V operation, and µ-law/A-law selectability. These are available in single and quad designs. This type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. An example of this type of codec is the Agere T7504 quad 5 V only codec. This type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. Further ac parameters are fixed by the external R/C network so software control of ac parameters is diffi- cult. Third-Generation Codecs. This class of devices includes all ac parameters set digitally under micropro- cessor control. Depending on the device, it may or may not have data control latches. Additional functionality sometimes offered includes tone plant generation and reception, PPM generation, test algorithms, and echo cancellation. Again, this type of codec may be +5 V only or ±5 V operation, single quad or 16-channel, and µ-law/A-law or 16-bit linear coding selectable. Exam- ples of this type of codec are the Agere T8536/7 (5 V only, quad, standard features), T8533/4 (5 V only, quad with echo cancellation), and T8531/36 (5 V only, 16- channel with self-test). ac Interface Network The ac interface network between the L9310 and the codec will vary depending on the codec selected. With a first-generation codec, the interface between the L9310 and codec actually sets the ac parameters. With a third-generation codec, all ac parameters are set dig- itally, internal to the codec; thus, the interface between the L9310 and this type of codec is designed to avoid overload at the codec input in the transmit direction, and to optimize signal to noise ratio (S/N) in the receive direction. Because the design requirements are very different with a first- or third-generation codec, the L9310 is offered with two different receive gains. Each receive gain was chosen to optimize, in terms of external com- ponents required, the ac interface between the L9310 and codec. With a first-generation codec, the termination imped- ance is set by providing gain shaping through a feed- back network from the SLIC VITR output to the SLIC RCVN/RCVP inputs. The L9310 provides a transcon- ductance from T/R to VITR in the transmit direction and a single-ended to differential gain in the receive direc- tion from either RCVN or RCVP to T/R. Assuming a short from VITR to RCVN or RCVP, the maximum impedance that is seen looking into the SLIC is the product of the SLIC transconductance times the SLIC receive gain, plus the protection resistors. The various specified termination impedance can range over the voiceband as low as 300 Ω up to over 1000 Ω . Thus, if the SLIC gains are too low, it will be impossible to syn- thesize the higher termination impedances. Further, the termination that is achieved will be far less than what is calculated by assuming a short for SLIC output to SLIC input. In the receive direction, in order to control echo, the gain is typically a loss, which requires a loss net- work at the SLIC RCVN/RCVP inputs, which will reduce the amount of gain that is available for termina- tion impedance. For this reason, a high-gain SLIC is required with a first-generation codec.

July 2001 Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit Agere Systems Inc. 45 ac Applications (continued) ac Interface Network (continued) With a third-generation codec, the line card designer has different concerns. To design the ac interface, the designer must first decide upon all termination imped- ance, hybrid balances, and TLP requirements that the line card must meet. In the transmit direction, the only concern is that the SLIC does not provide a signal that is too large and overloads the codec input. Thus, for the highest TLP that is being designed to, given the SLIC gain, the designer, as a function of voice band frequency, must ensure the codec is not overloaded. With a given TLP and a given SLIC gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resistor divider, between the SLIC output and codec input. In the receive direction, the issue is to optimize the S/N. Again, the designer must consider all the consid- ered TLPs. The idea, for all desired TLPs, is to run the codec at or as close as possible to its maximum output signal, to optimize the S/N. Remember, noise floor is constant, so the larger the signal from the codec, the better the S/N. The problem is if the codec is feeding a high-gain SLIC, either an external resistor divider is needed to knock the gain down to meet the TLP requirements, or the codec is not operated near maxi- mum signal levels, thus compromising the S/N. Thus, it appears the solution is to have a SLIC with a low gain, especially in the receive direction. This will allow the codec to operate near its maximum output signal (to optimize S/N), without an external resistor divider (to minimize cost). Note also that some third-generation codecs require the designer to provide an inherent resistive termina- tion via external networks. The codec will then provide gain shaping, as a function of frequency, to meet the return loss requirements. Further stability issues may add external components or excessive ground plane requirements to the design. To meet the unique requirements of both types of codecs, the L9310 offers two receive gain choices. These receive gains are mask programmable at the factory and are offered as two different code variations. For interface with a first-generation codec, the L9310 is offered with a receive gain of 8. For interface with a third-generation codec, the L9310 is offered with a receive gain of 2. In either case, the transconductance in the transmit direction, or the transmit gain, is 300 Ω . This selection of receive gain gives the designer the flexibility to maximize performance and minimize exter- nal components, regardless of the type of codec cho- sen. Design Tools The following examples illustrate the design tech- niques/equations followed to design the ac interface with a first- or third-generation codec for both a resis- tive and complex design. To aid the line circuit design, Agere has available Windows *-based spreadsheets to do the individual component calculations. Further, Agere has available PSPICE † models for circuit simula- tion and verification. Consult your Agere Account Rep- resentative to obtain these design tools. First-Generation Codec ac Interface Network Termination impedance may be specified as purely resistive or complex, that is, some combination of resistors and capacitors that causes the impedance to vary with frequency. The design for a pure resistive ter- mination, such as 600 Ω , does not vary with frequency, so it is somewhat more straightforward than a complex termination design. For this reason, the case of a resis- tive design and complex design will be shown sepa- rately. * Windows is a registered trademark of Microsoft Corporation. † PSPICE is a registered trademark of MicroSim Corporation.

voltage and no components for meter pulse rejection. match of input bias voltage at the RCVN/RCVP inputs. Figure 15. ac Equivalent Circuit

July 2001 Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit Agere Systems Inc. 47 ac Applications (continued) First-Generation Codec ac Interface Network: Resistive Termination (continued) Example 1, Real Termination The following design equations refer to the circuit in Figure 15. Use these to synthesize real termination imped- ance. Termination Impedance: ZT = Receive Gain: Transmit Gain: Hybrid Balance: hbal = 20 log hbal = 20 log To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0. The expression for ZHB becomes: V T/R ZT 76 Ω 2+ R P 2400

1 R T3

1 R RCV

 1 Z T Z T/R gtx V GSX V T/R gtx R X– R T6 ZT/R R X R HB1 V GSX V FR R HB kΩ() R X gtx grcv×

T ermination impedance = 600 Ω. Figure 16. Agere T7504 First-Generation Codec Resistive Termination, Nonmeter Pulse Application, Single

100 V—130 V

180 V—330 V

Table 22. L9310 Parts List for Agere T7504 First-Generation Codec Resistive Termination, Nonmeter Pulse

• See your Agere Account Representative for a recommended secondary protection device.

Protector* 180 V to 320 V — — Ring-side secondary protector. Protector* 100 V to 130 V — — Tip-side secondary protector. VBAT1 0.1 µF 20% 100 V Filter capacitor. C CC 0.1 µF 20% 10 V Filter capacitor. C DD 0.1 µF 20% 10 V Filter capacitor. C F2 0.015 µF 20% 100 V Filter capacitor. VPROG 33.2 kΩ 1% 1/16 W With R VREF fix dc current limit. R VREF 64.9 kΩ 1% 1/16 W With R VPROG fix dc current limit. RTF 0.1 µF 20% 100 V Ring trip filter capacitor. R RTF 1 MΩ 1% 1/16 W Ring trip filter resistor. R RS1 400 Ω 5% 2 W Sets ring trip threshold. R LCTH 59 kΩ 1% 1/16 W With R VREF , fix loop supervision threshold. R GX 6.34 kΩ 1% 1/16 W Sets T/R to VITR transconductance. C TX 0.15 µF 20% 10 V ac/dc separation. C C1 0.33 µF 20% 10 V dc blocking capacitor. C C2 0.1 µF 20% 10 V dc blocking capacitor. R T6 49.9 kΩ 1% 1/16 W With R X, sets transmit gain. R X 100 kΩ 1% 1/16 W With R T6, sets transmit gain. R HB 100 kΩ 1% 1/16 W With R X, sets hybrid balance. 28.3 kΩ 1% 1/16 W Optional. Compensates for input offset at RCVN/RCVP.

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 50 Agere Systems Inc. ac Applications (continued) First-Generation Codec ac Interface Net- work: Complex Termination The following reference circuit shows the complete SLIC schematic for interface to the Agere T7504 first- generation codec for the German complex termination impedance. For this example, the ac interface was designed for a 220 Ω + (820 Ω || 115 nF) complex ter- mination and hybrid balance with transmit gain and receive gain set to 0 dBm. For illustration purposes, 2.2 Vrms PPM injection was assumed in this example. This implies the overhead voltage is increased to 9.2 V and hybrid meter pulse rejection is used. Also, this example illustrates the device using the battery switch with multiple battery operation and fixed overhead, cur- rent limit, and loop closure threshold. Complex Termination Impedance Design Complex termination is specified in the form: 5-6396(F) To work with this application, convert termination to the form: 5-6398(F) where: R 1´ = R1 + R2 R 2´ = (R 1 + R2) C´ = C ac Interface Using First-Generation Codec R TGP /RTGS /CGS (ZTG ): these components give gain shaping to get good gain flatness. These components are a scaled version of the specified complex termina- tion impedance. Note that for pure (600 Ω ) resistive terminations, com- ponents R TGS and CGS are not used. Resistor RTGP is used and is still 6.34 kΩ . R X/RT6: with other components set, the transmit gain (for complex and resistive terminations) RX and RT6 are varied to give specified transmit gain. R T3/RRCV /RGP : for both complex and resistive termina- tions, the ratio of these resistors set the receive gain. For resistive terminations, the ratio of these resistors sets the return loss characteristic. For complex termi- nations, the ratio of these resistors set the low-fre- quency return loss characteristic. C N /RN1 /RN2 : for complex terminations, these compo- nents provide high-frequency compensation to the return loss characteristic. For resistive terminations, these components are not used and RCVN is connected to ground via a resistor. R HB : sets hybrid balance for all terminations. Set ZTG —Gain Shaping ZTG = RTGP || RTGS + CGS , which is a scaled version of ZT/R (the specified termination resistance), in the R TGP must be 6.34 kΩ to set SLIC transconductance to 300 V/A. R TGP = 6.34 kΩ At dc, CGS and C´ are open. R TGP = M x R1´ where M is the scale factor. M = It can be shown: R TGS = M x R2´ and C TGS = R 2 C R 1 R 1´ C´R 2´ R 1 R 2 R 2 R 1 R 2+  2 6340 R 1′ C ′ M

Figure 17. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown) at the midband frequency of 1000 Hz. loss/gain due to the impedance transformation. X (dB) = TX (specified[dB]).

July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit 52 Agere Systems Inc. ac Applications (continued) First-Generation Codec ac Interface Net- work: Complex Termination (continued) Receive Gain Ratios of RRCV , RT3, RGP will set both the low-frequency termination and receive gain for the complex case. In the complex case, additional high-frequency compen- sation, via C N , RN1 , and RN2 , is needed for the return loss characteristic. For resistive termination, CN , RN1 , and RN2 are not used and RCVN is tied to ground via a resistor. Determine the receive gain, gRCV , taking into account the impedance transformation in a manner similar to transmit gain. R X (dB) = RX (specified[dB]) + 20 log R X (dB) = 20 log gRCV Then: gRCV = and low-frequency termination ZTER(low) = + 2R P + 76 Ω ZTER(low) is the specified termination impedance assum- ing low frequency (C or C´ is open). R P is the series protection resistor. These two equations are best solved using a computer spreadsheet. Next, solve for the high-frequency return loss compen- sation circuit, CN , RN1 , and RN2 : C N R N2 = C G RTGP R N1 = RN2 There is an input offset voltage associated with nodes RCVN and RCVP . To minimize the effect of mismatch of this voltage at T/R, the equivalent resistance to ac ground at RCVN should be approximately equal to that at RCVP . Hybrid Balance Set the hybrid cancellation via R HB . R HB = R EQ 2R P 76 Ω+() 2400 R TGP  1– R X

Figure 18. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex

2.5 V and the SLIC to ground—with the ac coupling, a

higher to compensate for the low-frequency response. model for the L9310 is available.

T ermination impedance = 220 Ω + (820 Ω || 115 nF). Figure 19. Basic Loop Start Application Using T7504 Type Codec

0.7 Vrms for

2.2 Vrms at T/R

Table 23. L9310 Parts List for Agere T7504 First-Generation Codec Complex Termination, Meter Pulse

• See your Agere Account Representative for a recommended Secondary Protection Device.

Protector* 180 V to 320 V — — Ring-side secondary protector. Protector* 100 V to 130 V — — Tip-side secondary protector. Diode 1N4004 — — Reverse battery current. VBAT1 0.1 µF 20% 100 V Filter capacitor. C VBAT2 0.1 µF 20% 50 V Filter capacitor. C CC 0.1 µF 20% 10 V Filter capacitor. C DD 0.1 µF 20% 10 V Filter capacitor. C F2 0.01 µF 20% 100 V Filter capacitor. R VPROG 23.2 kΩ 1% 1/16 W With R VREF fix dc current limit. R OVH 16.9 kΩ 1% 1/16 W With R VREF fix overhead voltage. R VREF 69.8 kΩ 1% 1/16 W With R VPROG fix dc current limit. RTF 0.1 µF 20% 100 V Ring trip filter capacitor. R RTF 1 MΩ 1% 1/16 W Ring trip filter resistor. R RS1 400 Ω 5% 2 W Sets ring trip threshold. R LCTH 59 kΩ 1% 1/16 W With R VREF , fix loop supervision threshold. C PPM 0.01 µF 20% 5 V ac-couple PPM input. R PPM 17.4 kΩ 1% 1/16 W PPM hybrid rejection.

• See your Agere Account Representative for a recommended Secondary Protection Device.

1.74 kΩ 1% 1/16 W Gain shaping for complex termination. C GS 12 nF 5% 10 V Gain shaping for complex termination. C TX 0.1 µF 20% 10 V ac/dc separation. C C1 0.47 µF 20% 10 V dc blocking capacitor. C C2 0.1 µF 20% 10 V dc blocking capacitor. R T3 49.9 kΩ 1% 1/16 W With R GP and RRCV , sets termination impedance and receive gain. R T6 40.2 kΩ 1% 1/16 W With R X, sets transmit gain. R X 115 kΩ 1% 1/16 W With R T6, sets transmit gain. R HB 113 kΩ 1% 1/16 W With R X, sets hybrid balance. R RCV 59.0 kΩ 1% 1/16 W With R GP and RT3, sets termination impedance and receive gain. R GP 54.9 kΩ 1% 1/16 W With R RCV and RT3, sets termination impedance and receive gain. C N 120 pF 20% 10 V High-fr equency compensation. R N1 127 kΩ 1% 1/16 W High-frequency compensation. R N2 47.5 kΩ 1% 1/16 W High-frequency compensation, compensate for dc offset at RCVP/RCVN.

Figure 20. L9310 for Agere T8536 Third-Generation Codec Meter Pulse Application, Dual Battery

Table 24. L9310 Parts List for Agere T8536 Third-Generation Codec Meter Pulse Application, Dual Battery

• See your Agere Account Representative for a recommended secondary protection device.

Protector* 180 V to 320 V — — Ring-side secondary protector. Protector* 100 V to 130 V — — Tip-side secondary protector. Diode 1N4004 — — Reverse battery current. VBAT1 0.1 µF 20% 100 V Filter capacitor. C VBAT2 0.1 µF 20% 50 V Filter capacitor. C CC 0.1 µF 20% 10 V Filter capacitor. C DD 0.1 µF 20% 10 V Filter capacitor. C F2 0.015 µF 20% 100 V Filter capacitor. C RTF 0.1 µF 20% 100 V Ring trip filter capacitor. R RTF 1 MΩ 1% 1/16 W Ring trip filter resistor. R RS1 400 Ω 5% 2 W Sets ring trip threshold. C PPM 0.01 µF 20% 5 V ac couple PPM input. R PPM 17.4 kΩ 1% 1/16 W PPM hybrid rejection. R GX 6.34 kΩ 1% 1/16 W Sets T/R to VITR transconductance. C TX 0.15 µF 20% 10 V ac/dc separation. C C1 0.33 µF 20% 10 V dc blocking capacitor.

July 2001 Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access Circuit Agere Systems Inc. 59 Outline Diagram 44-Pin PLCC 5-2506F 4.57 MAX 1.27 TYP 0.53 MAX 0.10 SEATING PLANE

0.51 MIN

PIN #1 IDENTIFIER ZONE

16.66 MAX

17.65 MAX

16.66 MAX 17.65 MAX

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assum ed as a result of their use or application. Cop yright © 2001 Agere System s Inc. All R ights Re served July 2001 DS 01-190ALC (Replaces DS01-168ALC) For additional inform ation, contact your Agere Systems Account M anager or the following: IN TE R N ET: http://w w w .agere.com E-MA IL: docmas ter@ m icro.lucent.com N . AM ER IC A: Agere Systems Inc., 555 Union B oulevard, Room 30L-15P-B A, A llentow n, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CAN AD A: 1-800-553-2448, FAX 610-712-4106) AS IA PAC IFIC :Agere Systems Singapore Pte. Ltd., 77 Science Park D rive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 C H IN A: Agere Systems (Shanghai) Co ., Ltd., 33/F Jin M ao Towe r, 88 Cen tury Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN : Agere Systems Japan Ltd., 7-18, Higashi-G otanda 2-chom e, Shinagaw a-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUR O PE: D ata R equests: D ATA LIN E: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:G ER M A N Y: (49) 89 95086 0 (Munich), UNITED KIN G D O M : (44) 1344 865 900 (Ascot), FR ANC E: (33) 1 40 83 68 00 (Paris), SW ED EN : (46) 8 594 607 00 (Stockholm), FIN LAN D : (358) 9 3507670 (Helsinki), ITA LY: (39) 02 6608131 (M ilan), S PA IN : (34) 1 807 1441 (Madrid) Da ta Sheet July 2001Full-Feature SLIC, Ringing Relay, and Test Access Device L9310 Line Interface and Line Access C ircuit

Ordering Information

Device Part Nu m ber Packa ge Comc ode LUC L9310AP-D 44-Pin PLCC, D ry-bagged 108326729 LUCL931 0AP-DT 44-Pin PLCC, Dry-bagged, Tape and Reel 108326737 LUCL9 310GP-D 44-Pin PLCC, D ry-bagged 108417866 LUC L9310G P-DT 44-Pin PLCC, Dry-bagged, Tape and Reel 108417874