L9214A

L9214A AGERE | Alldatasheet

Document overview

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Technical content

Features

I Onboard ringing generation with software adjust- able crest factor switching I Flexible VCC options: — 3.3 V or 5 V VCC — No –5 V required I Power control options: — Power control resistor — Automatic battery switch to minimize off-hook power I Eight operating states: — Scan mode for minimal power dissipation — Forward and reverse battery active — On-hook transmission states — Ring mode — Disconnect mode I Low on-hook power: — 25 mW scan mode — 165 mW active mode I Two SLIC gain options to minimize external com- ponents in codec interface I Loop start, ring trip, and ground key detectors I Programmable current limit I On-hook and scan mode line voltage clamp I Thermal protection I 48-pin MLCC, 32-pin PLCC, and 28-pin SOG (Please contact your Agere Sales Representative for availability) packages

Applications

I Voice over Internet Protocol (VoIP) I Cable Modems I Terminal Adapters (TA) I Wireless Local Loop (WLL) I Telcordia Technologies™ GR-909 Access I Network Termination (NT) I PBX I Key Systems

Description

This device is optimized to provide battery feed, ring- ing, and supervision on short- and medium-loop plain old telephone service (POTS) loops. Supported round trip loop length is up to 1000 Ω . This device provides power ring to the subscriber by the use of line reversal to create either a sine wave ringing signal with a PWM input or a trapezoidal ring- ing signal with a selectable crest factor from a square wave input. It provides forward and reverse battery feed states, on-hook transmission, a low-power scan state, and a forward disconnect state. The device requires a V CC and line feed battery to operate. VCC may be either a 3.3 V or a 5 V supply. The ringing signal is derived from the high-voltage battery. An automatic battery switch is included to allow for use of a second lower voltage battery in the off-hook mode, thus minimizing short-loop off-hook power consumption and dissipation. If the user desires single battery operation, a power resistor is required to reduce the power dissipation in the SLIC. Loop closure, ring trip, and ground key detectors are available. The loop closure detector has a fixed threshold with hysteresis. The ring trip detector and ground key detector threshold and time constants are externally set. The dc current limit is programmed by an external resistor, the maximum current limit determined by the Vcc supply. The overhead voltage for this device is fixed and the device is capable of supporting 3.17 dB into a 600 Ω load with minimal overhead. The device is offered with two gain options. This allows for an optimized codec interface, with minimal external components regardless of whether a first- generation or a programmable third-generation codec is used.

October 2001Low-Cost Ringing SLIC L9214A/G 2 Agere Systems Inc. Table of Contents Contents Page Contents Page First-Generation Codec ac Interface First-Generation Codec ac Interface Complex Termination Impedance Design Third-Generation Codec ac Interface

October 2001Low-Cost Ringing SLIC L9214A/G 4 Agere Systems Inc. I Onboard balanced trapezoidal ringing generation, 40 Vrms, 1.2 crest factor: — 3 REN ring load (2330 Ω + 24 µF), 600 Ω loop — 2 REN ring load (3500 Ω + 16 µF), 1000 Ω loop — 2 REN ring load (3500 Ω + 1.8 µF), 500 Ω loop — No ring relay — No bulk ring generator required — 15 Hz to 70 Hz ring frequency supported I Power supplies requirements: — VCC talk battery and ringing battery required — No –5 V supply required — No high-voltage positive supply required I Flexible Vcc options: — 3.3 V or 5 V VCC operation — 3.3 V or 5 V VCC interchangeable and transparent to users I Power control options: — Automatic battery switch — Power control resistor I Minimal external components required I Ten operating states: — Forward active, fast polarity reversal — Reverse active, fast polarity reversal — Forward active, slow polarity reversal — Reverse active, slow polarity reversal — Scan — Disconnect — Ringing, line forward with high slope — Ringing, line reverse with high slope — Ringing, line forward with low slope — Ringing, line reverse with low slope I Unlatched parallel data control interface I Low SLIC power: — Scan 24 mW (VCC = 5.0 V) — Forward/reverse active 148 mW (VCC = 5.0 V) — Scan 17 mW (VCC = 3.3 V) — Forward/reverse on-hook 135 mW (VCC = 3.3 V) I Supervision: — Loop start, fixed threshold with hysteresis — Ring trip filtering, fixed threshold not a function of battery voltage, user adjustable with an external resistor — Common-mode current for ground key applica- tions, user-adjustable threshold I Adjustable current limit: — 10 mA to 45 mA programming range at 5 V Vcc — 10 mA to 35 mA programming range at 3.3 V Vcc I Overhead voltage: — Automatically adjusted in active mode — Clamped <56.5 V in scan and on-hook modes I Thermal shutdown protection with hysteresis I Longitudinal balance: — ETSI/ITU-T balance — GR-909 I Meter pulse compatible I ac interface: — Two SLIC gain options to minimize external com- ponents required for interface to first- or third-gen- eration codecs — Sufficient dynamic range for direct coupling to codec output I 28-pin SOG, 32-pin PLCC, and 48-pin MLCC pack- age options I 90 V CBIC-S technology The L9214 is designed to provide battery feed, ringing, and supervision functions on short and medium plain old telephone service (POTS) loops. Supported round- trip loop length is up to 1000 Ω of wiring resistance plus handset or ringing load. This device is designed to min- imize power in all operating states. The L9214 offers eight operating states. The device assumes use of a lower-voltage talk battery, a higher- voltage ringing battery and a single V CC supply. The L9214 requires only a positive VCC supply. No –5 V supply is needed. The L9214 can operate with a VCC of either 5.0 V or 3.3 V, allowing for greater user flexibility. The choice of VCC voltage is transparent to the user; the device will function with either supply volt- age connected. Two batteries may be used: 1. A high-voltage ring battery (V BAT1 ). VBAT1 is a maxi- mum –70 V and is used for power ringing, scan, and on-hook transmission modes. This supply is current limited to the maximum power ringing current of approximately 90 mApeak. 2. A lower-voltage talk battery (V BAT2 ). VBAT2 is nor- mally used for active mode powering. Alternatively, operation may be from a single high-volt- age battery supply with a power control resistor to reduce the power dissipation in the SLIC.

October 2001 Low-Cost Ringing SLIC L9214A/G Agere Systems Inc. 5 Description (continued) Forward and reverse battery active modes are used for off-hook conditions. Since this device is designed for short- and medium-loop applications, the lower-voltage V BAT2 is normally applied during the forward and reverse active states. Battery reversal is quiet, without breaking the ac path. The rate of battery reversal may be ramped to control switching time. The magnitude of the overhead voltage in the forward and reverse active modes allows for an undistorted sig- nal of 3.17 dBm into 600 Ω . The ring trip detector is turned off during active modes to conserve power. On-hook transmission is not permitted in the scan mode. In this mode, the tip ring voltage is derived from the higher V BAT1 rather than VBAT2 . In the scan and active modes, the overhead voltage is set such that the tip/ring open loop voltage is 42.5 V minimum for a primary battery of 63 V to 70 V for com- patibility with maintenance termination units (MTUs). Also, the maximum voltage with respect to ground (tip or ring to ground) is 56.5 V to comply with UL 1950/60950 ANNEX M.2 method B and IEC® 60950 (quiet interval of ringing). If the primary battery is below –63 V, the magnitude of the tip/ring open circuit voltage is approximately 17 V less than the battery. To minimize on-hook power, a low-power scan mode is available. In this mode, all functions except off-hook supervision are turned off to conserve power. On-hook transmission is not allowed in the scan mode. A forward disconnect mode is provided, where all cir- cuits are turned off and power is denied to the loop. The device offers a ring mode, in which a power ring signal is provided to the tip/ring pair. During the ring mode, the user, by use of the input states, performs line reversals at the required frequency, which gener- ates the power ringing signal. This signal may be applied continuously but is normally cadenced to meet country-specific requirements. The input states are normally set to an active state when power ringing is halted to enable on-hook transmission. The ring trip detector and common-mode current detector are active during the ring mode. The user may adjust the crest factor of the ring signal by selecting one of the two slew rates. The two rates, high or low, allow the designer to chose one set of external capacitors to meet the crest factor range of 1.2 to 1.6 over a 3:1 frequency range by software control alone. For increased power efficiency, the crest factor should be kept as low as possible. With maximum V BAT1 , the L9214 has sufficient power to ring a 3 REN (2310 Ω + 24 µF) ringing load into 600 Ω of physical wiring resistance. With maximum VBAT1 , the L9214 has sufficient power to ring a 2 REN (3500 Ω + 16 µF) ringing load into <1000 Ω of physical wiring resistance. Loop ranges may be expanded by applying a lower crest factor trapezoidal input waveform. This feature eliminates the need for a separate external ring relay, associated external circuitry, and a bulk ring- ing generator. See the Applications section of this data sheet for more information. Where PPM is required, it is injected into the audio receive pins (ac-coupled). PPM shaping must be done externally and the PPM level must be within the 1.12 Vrms (3.17 dBm, 600 Ω ) level set by the amplifier overhead in the active state. Both the ring trip and loop closure supervision func- tions are included. The loop closure has a fixed typical 10 mA on- to off-hook threshold in the active and scan mode. In either case, there is a 2 mA hysteresis. The ring trip detector requires a simple filter at the input. The ring trip threshold internally at a given battery volt- age is fixed, but the threshold can be adjusted through an external voltage divider. Typical ring trip threshold is 20.1 mA for a –65 V V BAT1 . A common-mode current detector for tip or ring ground detection is included for ground key applications. The threshold is user programmable via external resistors. See the Applications section of this data sheet for more information on supervision functions.

October 2001Low-Cost Ringing SLIC L9214A/G 6 Agere Systems Inc. Description (continued) Longitudinal balance is consistent with European ETSI and North American GR-909 requirements. Specifica- tions are given in Table 10. Data control is via a parallel unlatched control scheme. The dc current limit is programmable in the active modes by use of an external resistor connected between DCOUT and I PROG . Design equations for this feature are given in the dc Loop Current Limit section within the Applications section of this data sheet. Programming range is 15 mA to 45 mA with V CC = 5.0 V and 15 mA to 35 mA with VCC = 3.3 V. Program- ming accuracy is ±10% over this current range. Circuitry is added to the L9214 to minimize the inrush of current from the VCC supply and to the battery supply during an on- to off-hook transition, thus saving in power supply design cost. See the Applications section of this data sheet for more information. Transmit and receive gains have been chosen to mini- mize the number of external components required in the SLIC-codec ac interface, regardless of the choice of codec. The L9214 uses a voltage feed-current sense architec- ture; thus, the transmit gain is a transconductance. The L9214 transconductance is set via a single external resistor, and this device is designed for optimal perfor- mance with a transconductance set at 300 V/A. The L9214 offers an option for a single-ended to differ- ential receive gain of either 8 or 2. These options are mask programmable at the factory and are selected by choice of product code. A receive gain of 8 is more appropriate when choosing a first-generation type codec where termination imped- ance, hybrid balance, and overall gains are set by external analog filters. The higher gain is typically required for synthesization of complex termination impedance. A receive gain of 2 is more appropriate when choosing a third-generation type codec. Third-generation codecs will synthesize termination impedance and set hybrid balance and overall gains. To accomplish these func- tions, third-generation codecs typically have both ana- log and digital gain filters. For optimal signal to noise performance, it is best to operate the codec at a higher gain level. If the SLIC then provides a high gain, the SLIC output may be saturated causing clipping distor- tion of the signal at tip and ring. To avoid this situation, with a higher gain SLIC, external resistor dividers are used. These external components are not necessary with the lower gain offered by the L9214. See the Appli- cations section of this data sheet for more information. The L9214 is internally referenced to 1.5 V. The SLIC output VITR is referenced to AGND; therefore, it must be ac-coupled to the codec input. However, the SLIC inputs RCVP/RCVN are floating inputs. If there is not feedback from RCVP/RCVN to VITR, RCVP/RCVN may be directly coupled to the codec output. If there is feedback from RCVP/RCVN to VITR, RCVP/RCVN must be ac coupled to the codec output. The L9214 is thermally protected to guard against faults. Upon reaching the thermal shutdown tempera- ture, the device will enter an all-off mode. Upon cool- ing, the device will re-enter the state it was in prior to thermal shutdown. Hysteresis is built in to prevent oscillation. The L9214 is packaged in the 28-pin SOG, 32-pin PLCC and 48-pin MLCC surface-mount packages. The L9214A is set for gain of eight applications, and the L9214G is set for gain of two applications.

Figure 1. Architecture Diagram

Figure 2. 28-Pin SOG Diagram Figure 3. 32-Pin PLCC Diagram

26 ITR

27 VTX

28 TXI

18 FB2

17 ICM

16 TRGDET

15 BGND

Figure 4. 48-Pin MLCC Diagram

Table 1. Pin Descriptions hook condition exists or ringing is tripped. NC — No Connection. May be used as a tie point. NC — No Connection. May not be used as a tie point. tional to the differential ac tip/ring current. and ring. This node is a floating input. ring. This node is a floating input. and the ring trip threshold. ring trip circuit to prevent spurious responses. 11 15 15 AGND GND Analog Signal Ground. 13 17 19 V BAT1 PWR Battery Supply 1. High-voltage battery. 15 19 22 BGND GND Battery Ground. Ground return for the battery supplies.

Table 1. Pin Descriptions (continued) key or common-mode fault detection applications. the pin is connected to ground. overvoltage and overcurrent protection. overvoltage and overcurrent protection. 22 26 33 B3 I State Control Input. 23 27 34 B2 I State Control Input. 24 28 35 B1 I State Control Input. 25 29 36 B0 I State Control Input. achieved with a network from this node to VTX. 27 31 40 VTX O ac/dc Output Voltage. Output of internal AX amplifier. µF capacitor from this pin to VTX.

Table 2. Control States tip/ring, and the tip to ring voltage will be equivalent to the scan state.

0110 S c a n

1110 S c a n

I Pin PT is positive with respect to PR. BAT1 through a power control resistor. I Loop closure and common-mode detect are active. I Ring trip detector is turned off to conserve power. I Pin PT is positive with respect to PR. –42.5 V and –56.5 V with a primary battery of –65 V. I Loop closure and common-mode detect are active. I Ring trip detector is turned off to conserve power. I On-hook transmission is enabled. transmission of 0 dBm into 600 Ω . state, but with slower polarity reversal. state, but with slower polarity reversal.

October 2001 Low-Cost Ringing SLIC L9214A/G Agere Systems Inc. 13 State Definitions (continued) Reverse Active (Fast Polarity Reversal) Off-hook I Pin PR is positive with respect to PT. I VBAT2 is applied to tip/ring drive amplifiers via the soft battery switch for the majority of loop lengths. This may also be derived from V BAT1 through a power control resistor. I Loop closure and common-mode detect are active. I Ring trip detector is turned off to conserve power. I Overhead is set to nominal 4.0 V for undistorted transmission of 0 dBm into 600 Ω and may be increased automatically for larger signal levels. On-hook I Pin PR is positive with respect to PT. I VBAT1 is applied to tip/ring drive amplifiers. The tip to ring on-hook differential voltage will be between –42.5 V and –56.5 V with a primary battery of –65 V. I Loop closure and common-mode detect are active. I Ring trip detector is turned off to conserve power. I On-hook transmission is enabled. I Overhead is set to nominal 17.0 V for undistorted transmission of 0 dBm into 600 Ω . Reverse Active (Slow Polarity Reversal) Off-hook I Same as the reverse active (fast polarity reversal) state, but with slower polarity reversal. On-hook I Same as the reverse active (fast polarity reversal) state, but with slower polarity reversal. Scan I Except for loop closure, all circuits (including ring trip and common-mode detector) are powered down. I On-hook transmission is disabled. I Pin PT is positive with respect to PR, and VBAT1 is applied to tip/ring. I The tip to ring on-hook differential voltage will be between –42.5 V and –56.5 V with a –65 V primary battery. Disconnect I The tip/ring amplifiers and all supervision are turned off. I The SLIC goes into a high-impedance state. I NSTAT is forced high (on-hook). Ring I Ringing controlled digitally or by a PWM input signal I Power ring signal is applied to tip and ring. I Software-selectable slew rate, fast or slow. I Ring trip supervision and common-mode current supervision are active; loop closure is inactive. I Overhead voltage is reduced to typically 2.5 V and current limit set at I PROG is disabled. I Current is limited by saturation current of the amplifi- ers themselves, typically 72 mA peak at 125 °C. Thermal Shutdown I Not controlled via truth table inputs. I This mode is caused by excessive heating of the device, such as may be encountered in an extended power-cross situation.

periods can adversely affect device reliability. device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage. Table 3. Typical Operating Characteristics Table 4. Thermal Characteristics

1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Airflow, PCB board layers, and other factors can greatly affect this parameter.

October 2001 Low-Cost Ringing SLIC L9214A/G Agere Systems Inc. 15

Electrical Characteristics

Table 5. Environmental Characteristics

1. Not to exceed 26 grams of water per kilogram of dry air.

Table 6. 5.0 V Supply Currents Table 7. 5.0 V Powering Note: Refer to the power control description in the Applications section to calculate power dissipation in the forward/reverse off-hook state.

Table 8. 3.3 V Supply Currents Table 9. 3.3 V Powering Note: Refer to the power control description in the Applications section to calculate power dissipation in the forward/reverse off-hook state.

Table 10. Two-Wire Port

• Values guaranteed by design, not subject to production test.

† Corresponds to 55 dB minimum with 1%, 30 Ω resistors per Q552 (11/96) Section 2.1.2 and IEEE® 455.

300 Hz to 600 Hz

200 Hz to 1000 Hz

100 Hz to 4000 Hz

Table 11. Analog Pin Characteristics

Table 12. ac Feed Characteristics

1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between

150 Ω and 1400 Ω can be synthesized.

1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750 Ω , the recommended value. Positive cur-

rent is defined as the differential current flowing from PT to PR.

1. Tested per Figure 9. The gain reading is adjusted by the ratio of 696/660 to account for the 36 Ω nominal ac feed resistance.

200 Hz— 300 Hz

Table 13. Logic Inputs and Outputs (VCC = 5.0 V) Table 14. Logic Inputs and Outputs (VCC = 3.3 V) Table 15. Ringing Specifications

1. Voltage is measured across both resistive and capacitive elements of the ringer load.
2. Voltage is measured only across the resistive element of the ringer load.

5 REN 1386 Ω , 40 µF Load, 200 Ω Loop

3 REN 2330 Ω , 24 µF Load, 600 Ω Loop

2 REN 3500 Ω , 16 µF Load, 1000 Ω Loop

Table 16. Ring Trip (3 REN Configuration) I 100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz. I 10 kΩ resistor in parallel with a 4 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz. Table 17. Ring Trip (5 REN Configuration) I 100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz. I 10 kΩ resistor in parallel with a 6 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz. Note:Refer to the application section for further description of the 3 REN configuration vs. 5 REN configuration.

Figure 5. Basic Test Circuit, VCC = 3.3 V (3 REN Configuration)

October 2001Low-Cost Ringing SLIC L9214A/G 24 Agere Systems Inc. Under normal device operating conditions, power dissi- pation must be controlled to prevent the device temper- ature from rising too close to the thermal shutdown point. Power dissipation is highest with higher battery voltages, higher current limit, and under shorter dc loop conditions. Additionally, higher ambient temperature will reduce thermal margin. Increasing the number of PC board layers and increasing airflow around the device are typical ways of improving thermal margin. The maximum recommended junction temperature for the L9214 is 150 °C. The junction temperature is: Tj = TAMBIENT + θJA * PSLIC The thermal impedance of this device depends on the package type as well as number of PCB layers and air- flow. The thermal impedance of the 28-pin SOG pack- age is somewhat higher than the 32-pin PLCC package. The 28-pin SOG package in still air with a single-sided PCB is rated at 70 °C/W. The 32-pin PLCC package thermal impedance with no airflow on a four-layer PCB is estimated at 37 °C/W. The power handling capability of the package is: PSLIC = (150 °C – TAMBIENT )/θJA which is a minimum of 0.93 W for the 28-pin SOG package with a single-sided PCB and no airflow and as much as 2.15 W for the 32-pin PLCC package with a multilayer PCB. This device is intended to operate with a high-voltage primary battery of –63 V to –70 V. Under short-loop conditions, an internal soft battery switch shunts most (all but IBIAS = 3.5 mA) of the loop current to an auxiliary battery of lower absolute voltage (typically –21 V). Where single battery operation is required, an external power control resistor can be connected from the VBAT2 pin to VBAT1 and all but 3.5 mA of the loop current will flow through the power control resistor. The power dissipated in the device is best illustrated by an example. Assume VBAT1 is –65 V, VBAT2 is –21 V, and the current limit is is ILOOP . Let IQ1 and IQ2 be the quiescent currents drawn from VBAT1 and VBAT2 respectively (the current drawn from the battery when the phone is on-hook). Let IBIAS be the additional current drawn from VBAT1 when the phone is off-hook. IBIAS = IVBAT1(off-hook) – IQ1 Typically IBIAS is 3.5 mA. This additional VBAT1 current contributes to the loop current and the remaining loop current is supplied by VBAT2 , so that IVBAT2 = IQ2 + ILOOP – IBIAS IVCC is the current drawn from VCC and is relatively con- stant as the phone goes off hook. The total power from the power supplies is: PTOTAL = {[(IQ1 + IBIAS) * VBAT1 ] + [(IQ2 + ILOOP – IBIAS) * VBAT2 ] + [(IVCC ) * VCC ]} The maximum values of IQ1 and IQ2 are 1.95 mA and 1.20 mA respectively from Table 4. If the current limit is set to 25 mA, given the current limit tolerance of 10%, the maximum current limit is 27.5 mA. Also, assume 20 Ω of wire resistance, 30 Ω of protection resistance, and 200 Ω for the handset = 913.45 mW The power delivered to the loop and the protection resistors (PLOOP ) is: PLOOP = {(ILOOP )2 * [(2 * RPROTECTION ) + (RWIRE ) + 200 Ω )]} = 212 mW Thus, the total power dissipated by the SLIC is: PD of SLIC = Total power (PTOTAL ) – power delivered to loop and protection resistors (PLOOP ). PD = 913.45 mW – 212 mW = 701.45 mW for this example. Since the minimum power handling capability of the 28-pin SOG package is 0.93 W, in this case either package type is acceptable even with a single-sided PCB. At higher battery voltages, higher ambient tem- perature, and higher current limit, the required thermal impedance drops and the 32-pin PLCC package, more PCB layers, or some airflow might be required. Another case to consider is the case of the power con- trol resistor. In this case, the effective VBAT2 voltage is: VBAT2 = VBAT1 – RPWR * (ILOOP – IBIAS + IQ2 ) For the case of the 27.5 mA maximum current limit, choosing RPWR = 1.75 kΩ would give VBAT2 = –21 V and the same SLIC power as above. The power in the resistor would be: PRPWR = (ILOOP – IBIAS + IQ2 )2 * RPWR = 1.11 W Choosing a larger RPWR would result in lower VBAT2 and lower SLIC power, but more power in the resistor. Simi- larly, choosing a smaller RPWR results in higher VBAT2 , higher SLIC power, and less power in the resistor.

limit response is given in Table 18. Table 18. Typical Active Mode On- to Off-Hook Tip/ The overhead is preprogrammed in the active mode. = 1.12 V and Vpeak = 1.58 V are supported.

63 V, the magnitude of the open-loop tip to ring voltage

of the ring to ground voltage will be less than 56.5 V.

R L = loop resistance, not including protection resistors. R P = protection resistor value. Rdc = SLIC internal dc feed resistance. BAT1 | and |VBAT2 | = battery voltage magnitude. power conservation and SLIC thermal considerations. power will be taken from VBAT1 . Table 19. FB1/FB2 Values vs. Typical Ramp Time at

The ring signal will appear balanced on tip and ring. on ring. This operation is shown in Figure 12 below. tolerance can affect this calculation. Figure 12. Ring Operation

October 2001 Low-Cost Ringing SLIC L9214A/G Agere Systems Inc. 29 Periodic Pulse Metering (PPM) Periodic pulse metering (PPM), also referred to as tele- tax (TTX), is applied to the audio input of the L9214. When in the active state, this signal is presented to the tip/ring subscriber loop along with the audio signal. The L9214 assumes that a shaped PPM signal is applied to the audio input. ac Applications ac Parameters There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is done from the PCM highway to the transmit port. Transmit and receive gains may be specified in terms of an actual gain, or in terms of a transmission level point (TLP), that is the actual ac transmission level in dBm. Finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. Codec Types At this point in the design, the codec needs to be selected. The interface network between the SLIC and codec can then be designed. Below is a brief codec feature summary. First-Generation Codecs These perform the basic filtering, A/D (transmit), D/A (receive), and µ-law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending on the type, some have differential analog input and output stages, +5 V only or ±5 V operation, and µ-law/A-law selectability. These are available in single and quad designs. This type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. An example of this type of codec is the Agere T7504 quad 5 V only codec. This type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. The ac parameters are fixed by the external R/C net- work so software control of ac parameters is difficult. Third-Generation Codecs This class of devices includes all ac parameters set digitally under microprocessor control. Depending on the device, it may or may not have data control latches. Additional functionality sometimes offered includes tone plant generation and reception, PPM generation, test algorithms, and echo cancellation. Again, this type of codec may be 3.3 V, 5 V only, or ±5 V operation, sin- gle-, quad-, or 16-channel, and µ-law/A-law or 16-bit linear coding selectable. Examples of this type of codec are the Agere T8535/6 (5 V only, quad, standard features), T8537/8 (3.3 V only, quad, standard fea- tures), T8533/4 (5 V only, quad with echo cancellation), and the T8531/32 (5 V only, eight- or 16-channel). ac Interface Network The ac interface network between the L9214 and the codec will vary depending on the codec selected. With a first-generation codec, the interface between the L9214 and codec actually sets the ac parameters. With a third-generation codec, all ac parameters are set dig- itally, internal to the codec; thus, the interface between the L9214 and this type of codec is designed to avoid overload at the codec input in the transmit direction and to optimize signal to noise ratio (S/N) in the receive direction. Because the design requirements are very different with a first- or third-generation codec, the L9214 is offered with two different receive gains. Each receive gain was chosen to optimize, in terms of external com- ponents required, the ac interface between the L9214 and codec. With a first-generation codec, the termination imped- ance is set by providing gain shaping through a feed- back network from the SLIC VITR output to the SLIC RCVN/RCVP inputs. The L9214 provides a transcon- ductance from T/R to VITR in the transmit direction and a single-ended to differential gain from either RCVN or RCVP to T/R in the receive direction. Assuming a short from VITR to RCVN or RCVP , the maximum imped- ance that is seen looking into the SLIC is the product of the SLIC transconductance times the SLIC receive gain, plus the protection resistors. The various speci- fied termination impedance can range over the voice- band as low as 300 Ω up to over 1000 Ω . Thus, if the SLIC gains are too low, it will be impossible to synthe- size the higher termination impedances. Further, the termination that is achieved will be far less than what is calculated by assuming a short for SLIC output to SLIC input.

October 2001Low-Cost Ringing SLIC L9214A/G 30 Agere Systems Inc. ac Applications (continued) ac Interface Network (continued) In the receive direction, in order to control echo, the gain is typically a loss, which requires a loss network at the SLIC RCVN/RCVP inputs, which will reduce the amount of gain that is available for termination imped- ance. For this reason, a high-gain SLIC is required with a first-generation codec. With a third-generation codec, the line card designer has different concerns. To design the ac interface, the designer must first decide upon all termination imped- ance, hybrid balances, and transmission level point (TLP) requirements that the line card must meet. In the transmit direction, the only concern is that the SLIC does not provide a signal that is too hot and overloads the codec input. Thus, for the highest TLP that is being designed to, given the SLIC gain, the designer, as a function of voiceband frequency, must ensure the codec is not overloaded. With a given TLP and a given SLIC gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resis- tor divider, between the SLIC output and codec input. Note also that some third-generation codecs require the designer to provide an inherent resistive termina- tion via external networks. The codec will then provide gain shaping, as a function of frequency, to meet the return loss requirements. This feedback will increase the signal at the codec input and increase the likeli- hood that a resistor divider is needed in the transmit direction. Further stability issues may add external components or excessive ground plane requirements to the design. In the receive direction, the issue is to optimize the S/N. Again, the designer must consider all the TLPs. The idea is, for all desired TLPs, to run the codec at or as close as possible to its maximum output signal, to optimize the S/N. Remember noise floor is constant, so the hotter the signal from the codec, the better the S/N. The problem is if the codec is feeding a high-gain SLIC, either an external resistor divider is needed to knock the gain down to meet the TLP requirements, or the codec is not operated near maximum signal levels, thus compromising the S/N. Thus, it appears that the solution is to have a SLIC with a low gain, especially in the receive direction. This will allow the codec to operate near its maximum output signal (to optimize S/N), without an external resistor divider (to minimize cost). To meet the unique requirements of both type of codecs, the L9214 offers two receive gain choices. These receive gains are mask programmable at the factory and are offered as two different code variations. For interface with a first-generation codec, the L9214 is offered with a receive gain of 8. For interface with a third-generation codec, the L9214 is offered with a receive gain of 2. In either case, the transconductance in the transmit direction or the transmit gain is 300 Ω , (300 V/A). This selection of receive gain gives the designer the flexibility to maximize performance and minimize exter- nal components, regardless of the type of codec cho- sen. Design Examples First-Generation Codec ac Interface Network— Resistive Termination The following reference circuit shows the complete SLIC schematic for interface to the Agere T7504 first- generation codec for a resistive termination imped- ance. For this example, the ac interface was designed for a 600 Ω resistive termination and hybrid balance with transmit gain and receive gain set to 0 dBm. For illustration purposes, no PPM injection was assumed in this example. This is a lower feature application example and uses single battery operation, fixed overhead, current limit, and loop closure threshold. Resistor R GN is optional. It compensates for any mis- match of input bias voltage at the RCVN/RCVP inputs. If it is not used, there may be a slight offset at tip and ring due to mismatch of input bias voltage at the RCVN/RCVP inputs. It is very common to simply tie RCVN directly to ground in this particular mode of oper- ation. If used, to calculate RGN, the impedance from RCVN to ac ground should equal the impedance from RCVP to ac ground.

Figure 13. Use these to synthesize real termination

1 R T1

1 R RCV

1. The expression for ZHB becomes the following:

Figure 13. ac Equivalent Circuit

Figure 14. Agere T7504 First-Generation Codec; Resistive Termination (5 REN Configuration)

Table 20. L9214 Parts List for Agere T7504 First-Generation Codec; Resistive Termination Note: TX = 0 dBm, RX = 0 dBm, termination impedance = 600 Ω, hybrid balance = 600 Ω. R PT 30 Ω 1% Fusible or PTC Protection resistor. R PR 30 Ω 1% Fusible or PTC Protection resistor. C VBAT1 0.1 µF 20% 100 V VBAT filter capacitor. C VBAT2 0.1 µF 20% 50 V VBAT filter capacitor. |VBAT2 | < |VBAT1 |. D BAT1 1N4004 — — Reverse current. C CC 0.1 µF 20% 10 V VCC filter capacitor. C F1 0.22 µF 20% 100 V Filter capacitor. C F2 0.1 µF 20% 100 V Filter capacitor. R IPROG 5.76 kΩ 1% 1/16 W With RIREF, fixes dc current limit. R IREF 28.7 kΩ 1% 1/16 W With RIPROG , fixes dc current limit. C RT 1.0 µF 20% 10 V Ring trip filter capacitor. R RT1 100 kΩ 1% 1/16 W Ring trip filter resistor. R RT2 150 kΩ 1% 1/16 W Ring trip filter resistor. of balanced power ring signal. of balanced power ring signal. R GX 4750 Ω 1% 1/16 W Sets T/R to VITR transconductance. R CR 5 kΩ 5% 1/16 W Compensation resistor. C CC1 150 pF 20% 10 V Compensation capacitor. C TX 0.1 µF 20% 10 V ac/dc separation. C C1 0.1 µF 20% 10 V dc blocking capacitor. C C2 0.1 µF 20% 10 V dc blocking capacitor. R T6 49.9 kΩ 1% 1/16 W With RX, sets transmit gain. R X 100 kΩ 1% 1/16 W With RT6, sets transmit gain. R HB1 100 kΩ 1% 1/16 W With RX, sets hybrid balance. R GN Optional 17.6 kΩ 1% 1/16 W Optional. Compensates for input offset at RCVN/RCVP.

October 2001Low-Cost Ringing SLIC L9214A/G 34 Agere Systems Inc. ac Applications (continued) Design Examples (continued) First-Generation Codec ac Interface Network— Complex Termination The following reference circuit shows the complete SLIC schematic for interface to the Agere T7504 first- generation codec for the German complex termination impedance. For this example, the ac interface was designed for a 220 Ω + (820 Ω || 115 nF) complex ter- mination and hybrid balance with transmit gain and receive gain set to 0 dBm. Complex Termination Impedance Design Example The gain shaping necessary for a complex termination impedance may be done by shaping across the Ax amplifier at nodes ITR and VTX. Complex termination is specified in the form: 5-6396(F) To work with this application, convert termination to the form: 5-6398(F) where: R 1´ = R1 + R2 R 2´ = ( R 1 + R2) C ´ = C ac Interface Using First-Generation Codec R GX /RTGS /CGS (ZTG ): These components give gain shaping to get good gain flatness. These components are a scaled version of the specified complex termina- tion impedance. Note for pure (600 Ω ) resistive terminations, compo- nents RTGS and CGS are not used. Resistor RGX is used and is still 4750 Ω . R X/RT6: With other components set, the transmit gain (for complex and resistive terminations) RX and RT6 are varied to give specified transmit gain. R T3/RRCV /RGP : For both complex and resistive termina- tions, the ratio of these resistors sets the receive gain. For resistive terminations, the ratio of these resistors sets the return loss characteristic. For complex termi- nations, the ratio of these resistors sets the low-fre- quency return loss characteristic. C N /RN1 /RN2 : For complex terminations, these compo- nents provide high-frequency compensation to the return loss characteristic. For resistive terminations, these components are not used and RCVN is connected to ground via a resistor. R HB : Sets hybrid balance for all terminations. Set ZTG — gain shaping: ZTG = RGX || RTGS + CGS which is a scaled version of ZT/R (the specified termination resistance) in the R GX must be 4750 Ω to set SLIC transconductance to 300 V/A. R GX = 4750 Ω At dc, CGS and C´ are open. R GX = M x R1´ where M is the scale factor. M = It can be shown: R TGS = M x R2´ and C TGS = R 2 C R 1 R 1´ C ´R 2´ R 1 R 2 R 2  2 4750 C ′

Figure 15. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown) at the midband frequency of 1000 Hz. loss/gain due to the impedance transformation. X (dB) = TX (specified[dB]).

October 2001Low-Cost Ringing SLIC L9214A/G 36 Agere Systems Inc. ac Applications (continued) Design Examples (continued) ac Interface Using First-Generation Codec (contin- ued) Receive Gain Ratios of R RCV , RT3, RGP will set both the low-frequency termination and receive gain for the complex case. In the complex case, additional high-frequency compen- sation, via C N , RN1 , and RN2 , is needed for the return loss characteristic. For resistive termination, CN , RN1 , and RN2 are not used and RCVN is tied to ground via a resistor. Determine the receive gain, grcv, taking into account the impedance transformation in a manner similar to trans- mit gain. R X (dB) = RX (specified[dB]) + 20log R X (dB) = 20log grcv Then: grcv = and low-frequency termination ZTER(low) = + 2R P + 36 Ω ZTER(low) is the specified termination impedance assum- ing low frequency (C or C´ is open). R P is the series protection resistor. 36 Ω is the typical internal feed resistance. These two equations are best solved using a computer spreadsheet. Next, solve for the high-frequency return loss compen- sation circuit, CN , RN1 , and RN2 : C N R N2 = C G RTGP R N1 = RN2 There is an input offset voltage associated with nodes RCVN and RCVP. To minimize the effect of mismatch of this voltage at T/R, the equivalent resistance to ac ground at RCVN should be approximately equal to that at RCVP. Refer to Figure 16 (with dc blocking capaci- tors). To meet this requirement, R N2 = RGP || RT3. Hybrid Balance Set the hybrid cancellation via RHB . R HB = If a 5 V only codec such as the Agere T7504 is used, dc blocking capacitors must be added as shown in Fig- ure 16. This is because the codec is referenced to

2.5 V and the SLIC to ground— with the ac coupling, a

dc bias at T/R is eliminated and power associated with this bias is not consumed. Typically, values of 0.1 µF to 0.47 µF capacitors are used for dc blocking. The addition of blocking capaci- tors will cause a shift in the return loss and hybrid bal- ance frequency response toward higher frequencies, degrading the lower-frequency response. The lower the value of the blocking capacitor, the more pro- nounced the effect is, but the cost of the capacitor is lower. It may be necessary to scale resistor values higher to compensate for the low-frequency response. This effect is best evaluated via simulation. A PSPICE model for the L9214 is available. Design equation calculations seldom yield standard component values. Conversion from the calculated value to standard value may have an effect on the ac parameters. This effect should be evaluated and opti- mized via simulation. R EQ

1 R T3

 1– R X

Figure 16. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex

Figure 17. Agere T7504 First-Generation Codec; Complex Termination with Power Control Resistor (3 REN Table 21. L9214 Parts List for Agere T7504 First-Generation Codec; Complex Termination with Power

Table 21. L9214 Parts List for Agere T7504 First-Generation Codec; Complex Termination with Power Con- C VBAT1 0.1 µF 20% 100 V VBAT filter capacitor. C VBAT2 0.1 µF 20% 50 V VBAT filter capacitor. |VBAT2 | < |VBAT1 |. D BAT1 1N4004 — — Reverse current. C CC 0.1 µF 20% 10 V VCC filter capacitor. C F1 0.22 µF 20% 100 V Filter capacitor. C F2 0.1 µF 20% 100 V Filter capacitor. R PWR 2.0 kΩ 5% 2 W Power control resistor, provides single battery supply operation. R IPROG 5.76 kΩ 1% 1/16 W With RIREF, fixes dc current limit. R IREF 28.7 kΩ 1% 1/16 W With RIPROG , fixes dc current limit. C RING 1.0 µF 20% 10 V Ring trip filter capacitor. R RT1 133 kΩ 1% 1/16 W Ring trip filter resistor. R RT2 75 kΩ 1% 1/16 W Ring trip filter resistor. R GX 4750 Ω 1% 1/16 W Sets T/R to VITR transconductance. R TGS 1.74 kΩ 1% 1/16 W Gain shaping for complex termination. C GS 12 nF 5% 10 V Gain shaping for complex termination. C TX 0.1 µF 20% 10 V ac/dc separation. C C1 0.1 µF 20% 10 V dc blocking capacitor. C C2 0.1 µF 20% 10 V dc blocking capacitor. R T3 49.9 kΩ 1% 1/16 W With RGP and RRCV , sets termination impedance and receive gain. R T6 40.2 kΩ 1% 1/16 W With RX, sets transmit gain. R X 115 kΩ 1% 1/16 W With RT6, sets transmit gain. R HB1 113 kΩ 1% 1/16 W With RX, sets hybrid balance. R RCV 59.0 kΩ 1% 1/16 W With RGP and RT3, sets termination impedance and receive gain. R GP 54.9 kΩ 1% 1/16 W With RRCV and RT3, sets termination impedance and receive gain. C N 120 pF 20% 10 V High frequency compensation. R N1 127 kΩ 1% 1/16 W High frequency compensation.

T8535/6 data sheet for information on coefficient programming. Figure 18. Third-Generation Codec ac Interface Network; Complex Termination (3 REN Configuration)

Table 22. L9214 Parts List for Agere T8536 Third-Generation Codec Meter Pulse Application ac and dc

• For loop stability, increase to 50 Ω minimum if synthesizing 900 Ω or 900 Ω + 2.16 µF termination impedance.

R PT 30 Ω 1% Fusible or PTC Protection resistor*. R PR 30 Ω 1% Fusible or PTC Protection resistor*. Protector Agere L7591 — — Secondary protection. C VBAT1 0.1 µF 20% 100 V VBAT filter capacitor. C VBAT2 0.1 µF 20% 50 V VBAT filter capacitor. |VBAT2 | < |VBAT1 |. D BAT1 1N4004 — — Reverse current. C CC 0.1 µF 20% 10 V VCC filter capacitor. C F1 0.22 µF 20% 100 V Filter capacitor. C F2 0.1 µF 20% 100 V Filter capacitor. R IPROG 5.76 kΩ 1% 1/16 W With RIREF, fixes dc current limit. R IREF 28.7 kΩ 1% 1/16 W With RIPROG , fixes dc current limit. C RT 1.0 µF 20% 10 V Ring trip filter capacitor. R RT1 133 kΩ 1% 1/16 W Ring trip filter resistor. R RT2 75 kΩ 1% 1/16 W Ring trip filter resistor. tor of balanced power ring signal. tor of balanced power ring signal. R GX 4750 Ω 1% 1/16 W Sets T/R to VITR transconductance. R CR 10 kΩ 5% 1/16 W Compensation resistor. C CC1 270 pF 20% 10 V Compensation capacitor. C TX 0.1 µF 20% 10 V ac/dc separation. C C1 0.1 µF 20% 10 V dc blocking capacitor.

October 2001Low-Cost Ringing SLIC L9214A/G 42 Agere Systems Inc. Outline Diagrams 28-Pin SOG Note: The dimensions in these outline diagrams are intended for informational purposes only. For detailed draw- ings to assist your design efforts, please contact your Agere Sales Representative. 5-4414 Package Dimensions Package N Maximum Length L Maximum Width Without Leads B Maximum Width Including Leads W Maximum Height Above Board H SOG (small outline gull-wing) 28 18.11 7.62 10.64 2.67 W

0.610.51 MAX

H

0.28 MAX

0.10 SEATING PLANE

1.27 TYP

N L B PIN #1 IDENTIFIER ZONE

October 2001 Low-Cost Ringing SLIC L9214A/G Agere Systems Inc. 43 Outline Diagrams (continued) 32-Pin PLCC Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Agere Sales Representative. 5-3813r2 (F) 0.10 SEATING PLANE

0.38 MIN

TYP1.27 TYP 0.330/0.533 143 0 13 21 14 20 12.446 ± 0.127 11.430 ± 0.076 PIN #1 IDENTIFIER ZONE 14.986 ± 0.127 13.970 ± 0.076 3.175/3.556

October 2001Low-Cost Ringing SLIC L9214A/G 44 Agere Systems Inc. Outline Diagrams (continued) 48-Pin MLCC Dimensions are in millimeters. Notes:The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Agere Sales Representative. The exposed pad on the bottom of the package will be at VBAT1 potential. 0195 PIN #1 IDENTIFIER ZONE 7.00 6.75 SEATING PLANE 0.08 0.65/0.80

0.20 REF

7.00 5.10 ± 0.15 3.50 3.375 6.75 0.00/0.05 SECTION C –C

11 SPACES @

0.50 = 5.50

0.50 BSC

0.13/0.230.18/0.30 0.30/0.45 0.01/0.05

1.00 MAX

12° 0.18/0.30 0.24/0.60 0.24/0.60 0.20/0.45 VIEW FOR EVEN TERMINAL/SIDE C L EXPOSED PAD

October 2001 Low-Cost Ringing SLIC L9214A/G Agere Systems Inc. 45 Outline Diagrams (continued) 48-Pin MLCC, JEDEC MO-220 VKKD-2 Dimensions are in millimeters. Notes:The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Agere Sales Representative. The exposed pad on the bottom of the package will be at VBAT1 potential. 0195 INDEX AREA 7.00 3.50 SEATING PLANE

0.080.20 REF

7.00 5.00/5.25 3.50 0.50 = 5.50 0.18/0.30 0.02/0.05 1.00 MAX 0.23 0.30/0.50 (7.00/2 x 7.00/2) PIN #1 IDENTIFIER ZONE TOP VIEW SIDE VIEW DETAIL B 0.23 0.18 0.18 BOTTOM VIEW 2.50/2.625 EXPOSED PAD DETAIL B VIEW FOR EVEN TERMINAL/SIDE C L

October 2001Low-Cost Ringing SLIC L9214A/G Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2001 Agere Systems Inc. All Rights Reserved October 2001 DS01-144ALC (Replaces DS00-342ALC) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045

Ordering Information

• Please contact your Agere Sales Representative for availability. UL is a trademark of Underwriters Laboratories, Inc. IEC is a registered trademark of the International Electrotechnical Commission. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. PSPICE is a registered trademark of MicroSim Corporation. Telcordia Technologies is a trademark of Bell Communications Research, Inc. Device Part No. Description Package Comcode LUCL9214AAJ-D SLIC Gain = 8 28-Pin SOG*, Dry-bagged 108553892 LUCL9214AAJ-DT SLIC Gain = 8 28-Pin SOG*, Dry-bagged, Tape and Reel 108553900 LUCL9214AAU-D SLIC Gain = 8 32-Pin PLCC, Dry-bagged 108697905 LUCL9214AAU-DT SLIC Gain = 8 32-Pin PLCC, Dry-bagged, Tape and Reel 108697913 LUCL9214ARG-D SLIC Gain = 8 48-Pin MLCC, Dry-bagged 109058636 LUCL9214ARG-DT SLIC Gain = 8 48-Pin MLCC, Dry-bagged, Tape and Reel 109058644 LUCL9214GAJ-D SLIC Gain = 2 28-Pin SOG*, Dry-bagged 108560723 LUCL9214GAJ-DT SLIC Gain = 2 28-Pin SOG*, Dry-bagged, Tape and Reel 108560731 LUCL9214GAU-D SLIC Gain = 2 32-Pin PLCC, Dry-bagged 108698309 LUCL9214GAU-DT SLIC Gain = 2 32-Pin PLCC, Dry-bagged, Tape and Reel 108698317 LUCL9214GRG-D SLIC Gain = 2 48-Pin MLCC, Dry-bagged 109058651 LUCL9214GRG-DT SLIC Gain = 2 48-Pin MLCC, Dry-bagged, Tape and Reel 109058669