L8567 AGERE | Alldatasheet
Document overview
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Technical content
Features
■ Low active power (typical 149 mW during on-hook transmission) ■ Sleep state for low idle power (47 mW typical) ■ Quiet tip/ring polarity reversal ■ Distortion-free on-hook transmission ■ –35 V to –65 V battery operation ■ Convenient operating states: — Forward active — Polarity reversal active — Sleep — Forward disconnect ■ Supervision functions: — Fixed threshold off-hook detector with longitudinal rejection and hysteresis — Ring trip detector — Thermal shutdown indication ■ Adjustable loop current limit ■ Three driver outputs for relay driver ■ LED driver output to indicate off-hook ■ Latched parallel data interface ■ Battery and +5 V required: — Optional auxiliary lower voltage battery to reduce short loop power ■ –40 °C to +85 °C operational temperature range ■ User-selectable power management techniques ■ Thermal protection ■ 32-pin PLCC or 44-pin PLCC packaging
Description
This electronic subscriber loop interface circuit (SLIC) is optimized for low cost and low power con- sumption while providing a full-feature set. Included in the feature set is quiet reverse battery. Quiet polarity reversal is possible because the ac path is uninterrupted during transmission. The dc loop current limit is user-adjustable via a single exter- nal resistor. The maximum battery voltage is speci- fied as –65 V for long loop applications. The L8567 supports on-hook transmission. The total short loop off-hook power may be reduced by use of a lower-voltage auxiliary battery supply. If, when using the 32-pin PLCC, the user does not wish to supply an auxiliary battery, the component of the total short loop off-hook power that is dissipated on the L8567 SLIC is controlled by use of an external power resistor. With the 44-pin PLCC, a power resis- tor is not necessary. Included are both the loop closure and ring trip supervision functions. The loop closure threshold is fixed internally, which eliminates the need for an external precision resistor to set the threshold. T o minimize noise at the supervision output, hysteresis is included on the loop closure function. The loop clo- sure and ring trip outputs are multiplexed into a sin- gle NST A T output. Also included is a thermal shutdown mechanism. If device temperature exceeds 165 °C, as may be the case under an extended power cross fault, the SLIC will shut down (i.e., enter a high-impedance state) to provide protection against the fault. A logic output will indicate the SLIC is in thermal shutdown.
Table 16. 200 Ω + 680 Ω
44 Lucent Technologies Inc. Data Sheet August 1999People’s Republic of China Applications L8567 SLIC for Description (continued) General (continued) This device uses a latched parallel data input interface and a gated parallel output data interface. Level-sensi- tive data latches are used for state control inputs, and level-sensitive control gates are used for supervision outputs. Latch and gate control are through an ENABLE pin. When the ENABLE pin is high, input data is latched and the SLIC will not respond to changes at its logic input. When ENABLE is low, input control data will flow through the latch. Valid supervision data will appear at the NSTA T and NTSD outputs only when ENABLE is low. In this manner, the data input and data output of multiple SLICs can be serviced by a single control input or output. The L8567 is designed to be controlled/supervised using control/supervision outputs and inputs from the T7507 codec. Three relay drivers are also included. These drivers are meant to drive electromechanical relays (EMRs). State control of the relay drivers is via latched parallel data inputs. Like the B0/B1 and supervision data, control leads from the T7507 codec drive these inputs. The T7507 relay driver control outputs are meant to control the associated control input on all four of the L8567 SLICs associated with the T7507 codec. If an L7583 solid-state switch is used (instead of EMRs), the data control outputs from the T7507 codec will drive the latched state control inputs of the L7583 directly. Again, one data control output from the T7507 will drive the corresponding data input on four channels of the L7583. In the case of using the L7583, tie RD1I, RD2I, and RD3I relay driver control inputs of the L8567 to ground. Included are two supervision outputs. Both supervision outputs are the wire-OR of the loop closure and ring trip detectors. One (NSTA T) is used as a data control output and is gated via the EN input. The other (NLED) can be used to drive an LED to indicate loop states. The NLED driver is an open collector output, so multi- ple outputs may be used to drive a single LED. NLED is not gated, so valid supervision data appears at NLED regardless of the state of EN. NLED can be used as an alternative, nongated, data control output. The L8567 is available in a 32-pin PLCC or 44-pin PLCC package. Application for People’s Republic of China This SLIC may be used with any commercially avail- able codec; however, when used with the Lucent T ech- nologies Microelectronics Group T7507, the two devices form a complete line circuit optimized for requirements in the People’s Republic of China. The ac interface between the two components is extremely simple, requiring only a single capacitor in the transmit direction and a short-circuit connection, using no exter- nal components, in the receive direction. The complex 200 Ω + 680 Ω || 100 nF termination and hybrid balance is digitally synthesized by the T7507 codec. Additionally, the tip/ring to PCM (transmit) gain is fixed and set digitally by the T7507 codec at 0 dB. The PCM to tip/ring (receive) gain is also digitally set by the T7507 codec and is programmable via a bit in the codec serial data control stream to either –3.5 dB or –7.0 dB. The control interfaces of the L8567 and T7507 are designed for compatibility with each other. Both the T7507 codec and L8567 SLIC require only battery and +5 V to operate. When both devices are used, no –5 V supply is required.
are routed directly to L7583 control inputs, and SLIC pins RD1I, RD2I, and RD3I are grounded. Figure 1. Functional Diagram
Table 1. Pin Descriptions 6 4 RD3O O Relay Driver 3 Output. Output to drive an EMR, controlled by RD3I. 7 5 RD2O O Relay Driver 2 Output. Output to drive an EMR, controlled by RD2I. 8 6 RD1O O Relay Driver 1 Output. Output to drive an EMR, controlled by RD1I. open-collector output, so multiple outputs may be used to drive a single LED. gardless of the state of EN. 10 8 DGND PWR Digital Ground. 11 9 VDD PWR +5 V Digital Power Supply. 13 10 VCC PWR +5 V Analog Power Supply. the absolute value of the differential tip/ring current. ringer series through a high-value resistor. through a high-value resistor.
Table 1. Pin Descriptions (continued) circuitry. Connect to loop through overcurrent series resistance. cuitry. Connect to loop through overcurrent series resistance. 23 17 VBAT1 PWR Battery Supply. Most negative primary high-voltage power supply. 24 18 BGND PWR Battery Ground. Ground return for battery supply. the primary high-voltage battery side. this data sheet for more information. 29 21 CF1 — Filter Capacitor 1. Connect a 0.47 µ F capacitor from this pin to CF2. 30 22 CF2 — Filter Capacitor 2. Connect a 0.1 µ F capacitor from this pin to AGND. 34 25 AGND PWR Analog Signal Ground. ential voltage on tip and ring. differential voltage on tip and ring. and control signals will flow through the data latch to the SLIC control logic. NSTAT and NTSD supervision outputs are valid only when EN is low. appear at NTSD. The actual thermal shutdown is not affected by EN. EN needs to be low for valid data to appear at NSTAT.
T able 2 shows the input state coding. Table 2. Input State Coding
- All logic inputs are latched. The data latch is controlled by pin EN. The EN latch control is level sensitive.
state of the SLIC and drivers. used. If the relay drivers are not used, force them into the lowest power (not active) state by connecting RD1I, RD2I, and RD3I to ground. trip and loop closure detectors are active. trip and loop closure detectors are active. before applying power ringing to the loop. supply current to the coil of an EMR, thus deactivating the EMR. supply current to the coil of an EMR, thus deactivating the EMR. supply current to the coil of an EMR, thus deactivating the EMR.
T able 3 gives the output coding. Table 3. Supervision Coding thermal shutdown condition, respectively, exists) and pin EN must be low.
0 The SLIC die temperature has exceeded the thermal shutdown temperature threshold, and the
shutdown until the die temperature drops below the hysteresis threshold. This is a latched output. EN must be low for data on this output to be valid.
1 The SLIC die temperature has not exceeded the thermal shutdown temperature threshold, and
1 Identical to the on-hook or not ring trip state of the pin NST A T.
Lucent Technologies Inc. 11 Data Sheet August 1999 People’s Republic of China Applications L8567 SLIC for Absolute Maximum Ratings (TA = 25 °C) Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. * Use of an auxiliary battery, VBA T2, whose magnitude is equal to the primary battery VBAT1 but does not exceed the absolute maximum rating, will not damage the chip. However, in a 32-pin PLCC, it will drive the L8567 into thermal shutdown under short-loop conditions. Use a power resistor to node PWR. Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. Some of the known examples of conditions that cause such potentials during powerup are 1) an inductor connected to tip and ring can force an overvoltage on VBA T through the protection devices if the VBA T connection chatters, and 2) inductance in the VBA T lead could resonate with the VBA T filter capacitor to cause a destructive overvoltage. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit +5 V Power Supply VCC — — 7.0 V +5 V Digital Supply VDD — — 7.0 V Battery (talking) Supplies* VBAT1, VBAT2 — — –70 V Logic Input Voltage — –0.5 — 7.0 V Analog Input Voltage — –7.0 — 7.0 V Maximum Junction Temperature TJ — — 165 °C Storage Temperature Range Tstg –40 — 125 °C Relative Humidity Range R H 5 — 95 % Ground Potential Difference (BGND to AGND) — — — ± 3 V Parameter Min Typ Max Unit Ambient Temperature –40 — 85 °C VCC Supply Voltage 4.75 5.0 5.25 V VDD Supply Voltage 4.75 5.0 5.25 V VBAT1 Supply Voltage –65 –48 –35 V VBAT2 Auxiliary Battery Supply Voltage –35 –24 –15 V dc Loop Current-limit Programming Range 15 40 45 mA On- and Off-hook 2-wire Signal Level — 3.17 — dBm
12 Lucent Technologies Inc. Data Sheet August 1999People’s Republic of China Applications L8567 SLIC for
Electrical Characteristics
Minimum and maximum values are testing requirements in the temperature range of 25 °C to 85 °C and battery range of –35 V to –65 V . These minimum and maximum values are guaranteed to –40 °C based on component simulations and design verification of samples, but devices are not tested to –40 °C in production. The test circuit shown in Figure 6 is used unless otherwise noted. Positive currents flow into the device. T ypical values are characteristics of the device design at 25 °C based on engineering evaluations and are not part of the test requirements. Supply values used for typical characterization are V CC = VDD = 5.0 V , VBA T1 = –48 V, VBA T2 = –25.5 V . Table 4. Power Supply
- This parameter is not tested in production. It is guaranteed by design and device characterization.
- This is the total power drawn from the power supplies. If a power resistor is not used, the total power is dissipated by the SLIC through the
package. If a power resistor is used, the power is shared by the resistor and the SLIC.
Table 5. 2-Wire Port
- This parameter is not tested in production. It is guaranteed by design and device characterization.
- The longitudinal current is independent of dc loop current.
- Current-limit ILIM is programmed by a resistor, RPROG , from pin IPROG to AGND. RPROG (kΩ ) = 1.59 ILIM (mA).
4.IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
- Longitudinal balance of circuit card will depend on loop series resistance matching.
Table 6. Analog Pin Characteristics
50 Hz to 300 Hz
300 Hz to 600 Hz
600 Hz to 3400 Hz
T ransmit direction is tip/ring to 4-wire. Receive direction is 4-wire to tip/ring. Table 7. ac Feed Characteristics
- This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 8. Logic Inputs (B0, B1, EN, RD1I, RD2I, and RD3I) and Outputs (NSTAT and NTSD)
- Unless otherwise specified, all logic voltages are referenced to DGND.
- This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 9. Drivers (RD1O, RD2O, and RD3O)1
- The relay drivers operate using the VDD supply. When VDD is first applied to the device, the relay drivers will power up and remain in the off
state until the SLIC is configured via the data interface.
- Unless otherwise specified, all logic voltages are referenced to DGND.
- This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 10. LED Driver (NLED)1
- NLED is an open collector output, so multiple NLED outputs may be used to drive a common LED.
- Unless otherwise specified, all logic voltages are referenced to DGND.
- This parameter is not tested in production. It is guaranteed by design and device characterization.
Figure 6. Basic Test Circuit
that no RFI LP filter is used at tip and ring.
- HP is a registered trademark of Hewlett-Packard Company.
Figure 12. RFI Rejection Test Circuit
Lucent Technologies Inc. 21 Data Sheet August 1999 People’s Republic of China Applications L8567 SLIC for Functional Description General The L8567 is a full-feature subscriber loop interface cir- cuit (SLIC) designed to provide the battery feed and supervision functions to the tip/ring pair. The device uses a current sense/voltage feed architecture. That is, the device senses tip/ring current and supplies a pre- cise voltage that is proportional to the tip/ring current at the VTX output. The overall transconductance (tip/ring current to VTX voltage gain) is set by a single external resistor, R TG . The voltage at VTX is fed to the codec. The device feeds a precise differential voltage to tip and ring as a function of the signal voltages at the RCVN and RCVP inputs. The codec output is con- nected to the RCVN/RCVP SLIC inputs. Use with T7507 Codec for Use in People’s Republic of China The L8567 SLIC and Lucent T7507 codec together form a matched device set designed to meet the spe- cific MPT (Ministry of Post and T elecom) requirements for telephony in the People’s Republic of China. The ac interface between the L8567 and the T7507 codec is extremely simple, requiring only a single dc blocking capacitor in the transmit direction, and a short-circuit connection between the codec and SLIC inputs RCVN and RCVP . The T7507 codec has a fixed digital transmit gain stage and two digital gain stages in the receive direction. The choice of gain in the receive direction is user-selectable via a bit in the serial logic input bit stream. The transmit gain of the T7507 codec is such that when the tip/ring to VTX transconductance of the L8567 SLIC is set to
39.75 V/A (R
TG = 7.87 kΩ ), the overall tip/ring to PCM transmit gain is 0 dB into 813 Ω . (Note that 813 Ω is the equivalent resistance of the PRC complex impedance network of 200 Ω + 680 Ω || 100 nF at 1000 Hz.) The receive gains of the T7507 codec are such that the overall PCM to tip/ring receive gain is user-selectable to either –3.5 dB or –7.0 dB into 813 Ω . Note also that the T7507 codec will digitally synthesize a termination impedance of 200 Ω + 680 Ω || 100 nF . In order to do this, the codec will assume use of 50 Ω series protection resistors, plus the resistance of the L758X Lucent solid-state switch on both tip and ring. If the L758X switch is not used, the return loss perfor- mance will degrade slightly; however, it will still meet MPT standards. Gain flatness will not be affected; how- ever, gain levels will shift less than 0.2 dB. T o compen- sate (if desired), the resistance of the series protection resistor should be increased approximately 20 Ω , to account for the resistance of the switch. Hybrid cancellation is also done digitally by the T7507 codec, assuming a complex hybrid balance network of 200 Ω + 680 Ω || 100 nF . The T7507 codec operates off of a single 5 V power supply. Thus, a line card using the L8567 SLIC and T7507 codec does not require a –5 V supply. Since the T7507 is a 5 V only device, the analog input and output of the T7507 is referenced to 2.5 V . However, the dynamic input range of the L8567 SLIC is high enough to accommodate ac signals referenced to 2.5 V , thus eliminating the need for an external dc blocking capaci- tor in the receive direction. The basic loop start sche- matic, using an L8567 SLIC, T7507 codec, and L7583 switch, for PRC termination, is shown in Figure 20. The control logic interface of the L8567 SLIC is matched to the control logic of the T7507. The latched control inputs of the L8567 are designed to be driven by the T7507 control data outputs. The gated supervi- sion outputs of the L8567 SLIC are designed to feed data inputs to the T7507 codec. The T7507 codec sup- plies the required EN pulses to the L8567 SLIC. Con- trol data to the L8567 and supervision from the L8567 is received from, and passed to, the microcontroller at the serial data interface in the T7507 codec. See the T7507 data sheet for additional details.
2222 Lucent Technologies Inc. Figure 15. Termination Impedance dent loss relative to gain at 3400 Hz is shown below. tection resistors (200 Ω + 680 Ω || 0.1 µ F termination). Figure 16. Transmit and Receive Direction Table 14. Gain Flatness—Out of Band—Low resistors (200 Ω + 680 Ω || 0.1 µ F termination). Table 12. Gain
1020 Hz Min Typ Max Unit
Table 13. Gain Flatness—In Band
24 Lucent Technologies Inc. Data Sheet August 1999People’s Republic of China Applications L8567 SLIC for
Applications
12-3366a (F) Figure 20. Basic Loop Start Application Using T7507 Codec and L7583 Switch for 200 Ω + (680 Ω || 100 nF)
Table 15. Parts List for Loop Start Application SLIC L8567 Subscriber loop interface circuit (SLIC).
- Contact your Lucent T echnologies account representative for protector recommendations. Choice of this (and all) component(s) should be
component should be based solely on customer evaluation. Ringing and T est Access L7583B Switches ringing signals and test buses. balance, D/A, A/D, and filtering. PT 50 Ω Protection resistor. PTC or fusible. R PR 50 Ω Protection resistor. PTC or fusible. BAT1/CBA T2 0.1 µ F , 20%, 100 V V BA T filter capacitors. C F1 0.47 µ F , 20%, 100 V With CF2, improves idle-channel noise. C F2 0.1 µ F , 20%, 100 V With CF1, improves idle-channel noise. PROG 63.4 kΩ , 1%, 1/16 W Sets dc loop current limit. B2 0.1 µ F , 20%, 100 V ac/dc separation capacitor. R TG 7.87 kΩ , 1%, 1/16 W Sets SLIC transconductance. TS1 402 Ω , 5%, 2 W Ringing source series resistor. C RTS1 0.022 µ F , 20%, 5 V With RTSN , RTSP, forms second 2 Hz filter pole. C RTS2 0.27 µ F , 20%, 100 V With RTS2 , forms first 2 Hz filter pole. R TSN 2 MΩ , 1%, 1/16 W With C RTS1 , RTSP, forms second 2 Hz filter pole. R TSP 2 MΩ , 1%, 1/16 W With C RTS1 , RTSN , forms second 2 Hz filter pole.
to program these values are also shown. Table 16. 200 ΩΩΩΩ + 680 ΩΩΩΩ || 0.1 µµµµ F Design Parameters
2828 Lucent Technologies Inc. is actually dissipated on the SLIC. Figure 25. Power Derating the power is simply the SLIC quiescent power. tance) plus any protection or other series resistance. be controlled using several user-selectable techniques. power drawn from the talk battery. essary with the 32-pin PLCC package option. should be made to assess design margin. Table 17. Power Connections
44 PLCC
32 PLCC with auxil-
32 PLCC with high-
44 PLCC with high-
Lucent Technologies Inc. 29 Data Sheet August 1999 People’s Republic of China Applications L8567 SLIC for Applications (continued) Power Control—Auxiliary Battery With the auxiliary battery technique under long loops, the entire L8567 draws power from the higher-voltage battery. As the loop length decreases and the loop current increases or limits, the final output drive stage of the L8567 SLIC will draw power from the lower- voltage auxiliary battery. Thus, for a given loop, with a given loop current requirement, the minimum battery voltage is used by the L8567 SLIC, which minimizes the total power consumed. During on-hook or open- circuit conditions, the high battery is seen at tip and ring. All circuits on the L8567, other than the final output drive stage, are powered by the higher-voltage battery regardless of dc loop length. Thus, SLIC quiescent power will be determined solely by the high-voltage battery and will not be reduced under short dc loops. Tip/ring voltage varies as a function of loop length, decreasing with decreasing loop length. The battery transition will occur when the tip/ring voltage is less than V BAT2 by a diode drop and a VCE(SA T), or about 1 V . Thus, the transition point from VBA T1 to VBA T2 may be controlled by the choice of VBA T2. The relationship is given below: VBA T2 = TOH + RDC(TIP) * ILOOP + 2 * RPROT * ILOOP + R LOOP * ILIM + RDC(RING) * ILIM + (VDIODE + VCE(SA T)) where: VBAT2 = magnitude of auxiliary battery. TOH = overhead voltage tip to ground, typically 2.5 V. R DC(TIP) = dc feed resistance on tip, typically 55 Ω . ILOOP = loop current. VBAT2 will switch under short-loop conditions where it is likely that the SLIC will be current limiting; thus, ILOOP = ILIM. R PROT = series protection resistance plus L758X resis- tance, nominal 68 Ω . R LOOP = loop resistance for transition from VBAT1 to VBAT2 . ILIM = SLIC current limit set per resistor RLIM. R DC(RING) = dc feed resistance on ring, typically 55 Ω . (VDIODE + VCE(SA T)) = internal voltage drop associated with battery switch circuit, typically 1 V . Thus, the equation may be rewritten: V BAT2 = 2.5 V + 55 ILIM + 132 ILIM + RLOOP ILIM + 55 ILIM + 1 V R LOOP = – 242 Ω Thus, for example, for a nominal loop transition at 700 Ω , with a 25 mA current limit, VBA T2 should be nom- inal 27 V . Power Control—32-Pin PLCC with Power Control Resistor This section is applicable if the user chooses to use a single high-voltage battery with an external power con- trol resistor. The power resistor is used in conjunction with the 32-pin PLCC package. Resistor R PWR is connected from pin PWR to the bat- tery supply. This resistor limits the power that is dissi- pated on the SLIC. dc loop current is shared between the SLIC and R PWR , thus controlling the actual power that is dissipated on the SLIC. The value and power rat- ing of R PWR is determined by the thermal capabilities of the L8567’s 32-pin PLCC package. The value and power rating of R PWR is calculated as shown below. The relationship for the power dissipated in the SLIC is given by: PSLIC = PTOTAL + PQ – PPROT – PPWR – PLOOP (1) Where: P SLIC = the power dissipated in the SLIC. PTOTAL = the total off-hook power dissipation. PQ = the SLIC quiescent or on-hook power dissipation. PPROT = the power dissipated in the protection resistors (and L758X switch). P PWR = the power dissipated in RPWR . PLOOP = the power dissipated in the subscriber loop. The relationships for the individual power dissipation components are: PTOTAL = ILOOP • |VBA T|( 2 ) PQ is the active state open loop power dissipation of the L8567 SLIC and is specified in T able 4 on page 12. PPROT = (ILOOP )2 • 2RP (3) PPWR = (4) PLOOP = VLOOP • ILOOP (5) Where: I LOOP is the maximum dc loop current which is the dc loop current limit that is set by resistor RPROG . R P is the value of the protection resistor plus the resis- tance of the L758X switch. BA T| is the magnitude of the maximum battery volt- age. V ROH is the overhead voltage associated with the ring lead. V LOOP is the ring/tip loop voltage. This voltage is a func- tion of the dc loop length or resistance. It will decrease with decreasing loop resistance. R PWR is the resistance of the external resistor RPWR . V BAT2 3.5– ILIM V BAT V ROH– V LOOP–() 2
3030 Lucent Technologies Inc. Data Sheet August 1999People’s Republic of China Applications L8567 SLIC for Applications (continued) Power Control—32-Pin PLCC with Power Control Resistor (continued) The maximum power that may be dissipated in the SLIC, PSLIC(MAX) is given by TTSD – TA = TRISE (6) (7) Where: TTSD is the thermal protection shutdown temperature and is specified in T able 4. TA is the maximum ambient operating temperature. TRISE is the maximum allowed SLIC temperature rise to avoid driving the SLIC into thermal shutdown. PSLIC(MAX) is the maximum allowed power that is dissi- pated on the SLIC to avoid driving the SLIC into ther- mal shutdown. is the thermal resistance, junction to ambient of the 32-pin PLCC package; it is specified in T able 4 on page 12. The approach to choosing the value and rating of R PWR follows. First use equations 6 and 7 to determine the maximum allowed power that may be dissipated on the SLIC without driving the SLIC into thermal shutdown. Next consider equations 1 and 4. In both equation 1 and 4, pick a value of R PWR and for this value, or RPWR , vary VLOOP from the open-circuit (on-hook) state volt- age to the voltage seen at the minimum expected dc loop length (100 Ω ). The idea is to use the SLIC power dissipation value from equation 1, P SLIC, to ensure that the maximum SLIC power dissipation value from equa- tion 7, P SLIC(MAX), is not exceeded for any value of loop length. At the same time, using equation 4, try to mini- mize the power dissipated in R PWR so as to choose the minimum power rating of the resistor to minimize cost associated with this resistor. This technique is illus- trated in the following design example. Power Considerations R PWR Design Example: Assume ILOOP = 45 mA. This assumes that a 40 mA current limit is programmed by resistor RPROG set at 63.4 kΩ , plus a worst-case 15% tolerance that is speci- fied in Table 5. |VBA T| = 56 V . 2R P = 136 Ω . This assumes use of 50 Ω PTC in both the tip and ring lead associated with the L7583 ON resistance. VROH = 4 V (typical). PQ = 165 mW as nominally specified in T able 4. TTSD = 165 °C per Table 4. TA = 85 °C. = 60 °C/W per T able 4. VLOOP is varied from the open-circuit voltage of approx- imately 50 V to the voltage at a 100 Ω loop length, approximately 5 V . First, using equations 6 and 7, calculate the maximum allowed power dissipation in the SLIC. TTSD – TA = TRISE (6) 165 °C – 85 °C = 80 °C (7) PSLIC(MAX) = = 1.33 W Given the choice of RPWR chosen, the value of PSLIC in equation 8 must be less than 1.33 W for all loop lengths (all values of VLOOP in equation 1). At the same time, R PWR should be chosen to minimize PPRW from equa- tion 4. Inserting values into equation 1: PSLIC ≤ PTOTAL + PQ – PPROT – PPWR – PLOOP (8) From equation 2, 3, 4, 5 PSLIC ≤ ILOOP • |VBA T| + PQ – (ILOOP )2 • 2R P – – V LOOP • ILOOP Inserting values: 2(50 + 18)] – – LOOP )(0.045 mA) (9) P SLIC MAX() TRISE Θ JA Θ JA Θ JA P SLIC MAX() TRISE Θ JA 80 °C V BAT V ROH– V LOOP–() 2 R PWR 56 4– V LOOP–() 2 R PWR
50 V to the very short loop (~100 Ω ) value of 5 V in
L8567 SLIC is not driven into thermal shutdown. will tell what the power rating of RPWR needs to be. to use a computer-based spreadsheet program. PWR was further reduced to 1800 Ω . gest that a 5% tolerance is adequate for RPWR . Table 18. RPWR = 2600 Ω Table 19. RPWR = 2200 Ω Table 20. RPWR = 1800 Ω
3232 Lucent Technologies Inc. Table 21. RPWR = 4400 Ω Table 22. RPWR = 2310 Ω (RPWR = 2200 Ω + 5%) Table 23. RPWR = 2090 Ω (RPWR = 2200 Ω – 5%) ural airflow as seen in a typical switch cabinet. 165 °C under normal operating conditions. resistors are used at both tip and ring.
- TTSD – TA(max) = allowed thermal rise.
- Allowed thermal rise = package thermal
impedance • SLIC power dissipation. than 1.9 W, it will not enter the thermal shutdown state. current limit + SLIC quiescent power. sipation less the power that is dissipated in the loop. the SLIC will not enter the thermal shutdown state.
Figure 26. Tip/Ring Voltage Decrease characteristic in the current-limit region. |VBAT | = battery voltage magnitude. R L = loop resistance, not including protection resistors. R P = protection resistor value. R dc = SLIC internal dc feed resistance. The design begins by drawing the desired dc template. Refer to Figures 23, 24, and 26. the dc template has a high resistance (10 kΩ ). operation. This is shown in Figure 24.
3434 Lucent Technologies Inc. |VBAT | = magnitude of battery voltage. VOH = SLIC overhead voltage. solid-state switch (if used). R dc = SLIC dc feed resistance. tion resistor with worst-case 10% tolerance of 55 Ω . Figure 27. SLIC 2-Wire Output Stage
Lucent Technologies Inc. 35 Data Sheet August 1999 People’s Republic of China Applications L8567 SLIC for dc Applications (continued) On-Hook Transmission (continued) In addition to the required peak signal level, the SLIC needs about 2 V from each power supply to bias the amplifier circuitry. It can be thought of as an internal saturation voltage. Combining the saturation voltage and the peak signal level, the required overhead can be expressed as: where V SA T is the combined internal saturation voltage between the tip/ring amplifiers and VBA T (4.0 V typical). R P (Ω ) is the protection resistor value. ZT/R (Ω ) is the ac loop impedance. Example: Determine the required overhead to transmit on-hook (ILOOP = 0) a 3.17 dBm ac signal into a 900 Ω ac lead. Assume use of 50 Ω protection resistors with a 10% tolerance or 55 Ω and an L7583 solid-state switch. The worst-case resistance of the switch is 28 Ω . Note the minimum overhead voltage of the L8567 is 6.4 V . VON = 4.0 + 3.17 dBm = 20log Vrms = 1.296 V VON = 4.0 + Vrms = 1.296 V VON = 4.0 + VOH = 6.17 V < 6.4 V Thus, an overhead of 6.17 V is needed for on-hook transmission of a 3.17 dBm signal into a 900 Ω ac load. The L8567 has a minimum overhead of 6.4 V . Supervision Both the loop closure and ring trip supervision func- tions are included on the L8567 SLIC. The outputs of these two supervision functions are internally wired- ORed together to form a single output NST A T . The wired-OR connection of the loop supervision and ring trip detector is also available on pin NLED. This pin has sufficient drive capability to drive an LED. This pin is an open-collector output, so multiple pins can be used to drive a common LED. Also included is a SLIC thermal shutdown indicator, NTSD. Note that the ring trip detector is not active in the low- power scan state. The ring trip detector must be active prior to applying power ringing to the subscriber loop. Activate the ring trip detector by putting the L8567 SLIC into the powerup mode before applying power ringing to the subscriber loop. Loop Closure The on-hook to off-hook loop closure threshold is inter- nally set to a nominal 11 mA at V BA T = –48 V . There is a nominal 2 mA hysteresis. This means that the off-hook to on-hook threshold will be a nominal 2 mA less than the on-hook to off-hook threshold. The loop closure threshold will track with battery voltage, increasing as the battery gets more negative. The loop closure com- parator has built-in longitudinal rejection, eliminating the need for an external 50 Hz/60 Hz filter. The loop closure detector is valid during scan, forward, and reverse active states. V OH V SAT 1 2R P ZT/R vT/R+= Λ 1 25 5 2 8+[]× 2V rms() V rms[] 2 1 25 5 2 8+[]× 2V rms() 1 25 5 2 8+[] 2() 1.296()
circuit is shown in Figure 28, along with its use in an application using unbalanced, battery-backed ringing. Figure 28. Ring Trip Equivalent Circuit and Equivalent Application pole at 2 Hz was implemented to prevent false ring trip. pin may be connected to an external monitoring device.
enable (EN) pin associated with this control scheme. SLIC. The T7507 also provides the EN control signal. state of EN pin associated with the individual SLIC. This is shown in Figure 29 below. the state of the SLIC and drivers. Logic outputs NSTA T and NTSD are also latched. Figure 29. Simplified Control Scheme
3838 Lucent Technologies Inc. Table 24. Valid Data at NSTAT and NTSD Figure 30. Logic Output Latches to NST A T for control logic. done from the PCM highway to the transmit port. gains, termination impedance, and hybrid balance. hybrid balance are set internally. requires virtually no external components. extremely cost-effective solution.
0 Off-hook—loop closure or ring trip 0
0 On-hook 1
0 Device in thermal shutdown 0
0 Normal operation—device state deter-
Lucent Technologies Inc. 39 Data Sheet August 1999 People’s Republic of China Applications L8567 SLIC for Outline Diagrams 32-Pin PLCC Dimensions shown are metric. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Lucent Technologies Sales Representative. 5-3813 (F)r01 0.10 SEATING PLANE
0.38 MIN
TYP1.27 TYP 0.330/0.533 143 0 13 21 14 20 12.446 ± 0.127 11.430 ± 0.076 PIN #1 IDENTIFIER ZONE 14.986 ± 0.127 13.970 ± 0.076 3.175/3.556
40 Lucent Technologies Inc. Data Sheet August 1999People’s Republic of China Applications L8567 SLIC for Outline Diagrams (continued) 44-Pin PLCC Dimensions shown are metric. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Lucent T echnologies Sales Representative. 5-2506 (F) r07 4.57 MAX 1.27 TYP 0.53 MAX 0.10 SEATING PLANE
0.51 MIN
PIN #1 IDENTIFIER ZONE
16.66 MAX
17.65 MAX
16.66 MAX 17.65 MAX
Lucent Technologies Inc. 41 Data Sheet August 1999 People’s Republic of China Applications L8567 SLIC for
Ordering Information
Device Part No. Description Package Comcode LUCL8567AAU-D PRC SLIC 32-Pin PLCC (Dry-bagged, Tube) 107891236 LUCL8567AAU-DT PRC SLIC 32-Pin PLCC (Dry-bagged, Tape and Reel) 107891244 LUCL8567AP-D PRC SLIC 44-Pin PLCC (Dry-bagged, Tube) 107957706 LUCL8567AP-DT PRC SLIC 44-Pin PLCC (Dry-bagged, Tape and Reel) 107957714
Lucent Technologies Inc. reserves the right to ma ke changes to the product(s) or inform ation contained herein without notice. No liability is assum ed as a result of their use or application. No rights under any patent accompa ny the sale of any such product(s) or inform ation. Co pyright © 1999 Lucent Technologies Inc. All Rights Reserved August 1999 DS99 -100ALC (Replaces D S98-001ALC) For additional information, contact your M icroelectronics Group Account M anager or the following: IN TERNE T: http://www .lucent.com/micro E-M AIL: docm aster@mi cro.lucent.com N. AM ERICA : Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown , PA 18103 1-800-372-2447, FAX 610-712-4106 (In C AN ADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC : Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 C HIN A: M icroelectronics Group, Lucent Technologies (C hina) C o., Ltd., A-F2, 23/F, Zao Fong U niverse Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. C hina Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: M icroelectronics Group, Lucent Technologies Japan Ltd., 7-18, H igashi-G otanda 2-chom e, Shinagaw a-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R O PE : D ata Requests: M ICR O ELEC TR O N ICS GR OU P DATALIN E: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GE R MA N Y: (49) 89 95086 0 (Munich), U N ITED KIN GDO M : (44) 1344 865 900 (Ascot), FR AN CE : (33) 1 40 83 68 00 (Paris), SWE D EN : (46) 8 594 607 00 (Stockholm), FIN LAND : (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid)