L8560

L8560 AGERE | Alldatasheet

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Technical content

Features

■ Full-feature set for central office applications ■ Also ideal for ISDN terminal adapters, pair gain, and cable telephony applications ■ Auxiliary input for second battery, and internal switch to enable its use to save power in short tele- phone loops ■ 5 V only operation or optional ±5 V operation for reduced power consumption ■ Low active power (85 mW typical) and scan power (61 mW typical) with 5 V only operation ■ Low active power (68 mW typical with auxiliary bat- tery) and scan power (45 mW typical) with ±5 V operation ■ Quiet tip/ring polarity reversal ■ Per-line ringing available for short loops ■ Reduced overhead and increased current limit dur- ing ring mode for lower-battery operation or increased ring loop length ■ Supports meter pulse injection ■ Distortion-free full duplex from 0 mA dc loop cur- rent on-hook transmission ■ Convenient operating states: — Forward powerup — Polarity reversal powerup — Forward sleep — Ground start — Disconnect ■ Adjustable supervision functions: — Off-hook detector with longitudinal rejection — Ground key detector with longitudinal rejection — Ring trip detector ■ Independent, adjustable dc and ac parameters: — dc feed resistance (44-pin PLCC version) — Loop current limit — Termination impedance ■ Thermal protection

Description

The L8560 full-feature, low-power subscriber line interface circuit (SLIC) is optimized for low power consumption while providing an extensive set of fea- tures. This part is ideal for ISDN terminal adapter applications and short-loop, power-sensitive applica- tions such as pair gain and cable telephony. This part is also designed for PBX, DLC, or CO applications. The SLIC includes an auxiliary battery input and a battery switch. In short-loop applications, SLICs can be used in high battery to present a high on-hook voltage, and then switched to low battery to reduce off-hook power. To help minimize the required auxiliary battery volt- age, the dc feed resistance and overhead voltage are set at 55 Ω and 6.7 V, respectively. This allows an undistorted on-hook transmission of a 3.14 dBm sig- nal into a 900 Ω loop impedance. The device offers the reverse battery function. Using the reverse battery, the device can provide a bal- anced power ring signal to tip and ring. In this mode of operation, the battery switch is used to apply a high-voltage battery during ringing and a lower-voltage battery during the talk and idle states. Also included in the L8560 is a dc current-limit switch, which increases the dc current limit during power ringing. In addition, dc overhead voltage is reduced during the ring state. With the battery and current-limit switches, and overhead reduction, the L8560 can provide sufficient power to ring a true North American 5 REN load of 1386 Ω + 40 µF. The device offers ring trip and loop closure supervi- sion with 0.3 V and 2 mA hysteresis, respectively. It also includes the ground start state and ring ground detection. A summing node for meter pulse injection to 2.2 Vrms is also included. The 44-pin PLCC ver- sion also has a spare uncommitted op amp, which may be used for ac gain setting or meter pulse filter- ing.

April 2000L8560 Low-Power SLIC with Ringing 2 Lucent Technologies Inc. Table of Contents Contents Page Adjusting Overhead Voltage and dc Feed V Ringing SLIC Balanced Ring Signal Contents Page Reference Designs for ISDN TA Applications ... 31 Example 3, Complex Termination Without Complex Termination Impedance Design Example Using L8560 Without Spare

sumption is greatly reduced. allows for low on-hook power dissipation. allows for low on-hook power dissipation. Table 1. L8560 Product Family Feature Summary

• More information is provided in the Applications section of this document.

5 V Operation X X NA X X X X

Figure 1. Functional Diagram

Table 2. Pin Descriptions absolute value of the differential tip/ring current. 11 3 CF2 — Filter Capacitor 2. Connect a 0.1 µF capacitor from this pin to AGND. 12 4 CF1 — Filter Capacitor 1. Connect a 0.47 µF capacitor from this pin to pin CF2. — 5 SN I Summing Node. The inverting input of the uncommitted operational amplifier. A resistor or network to XMT sets the gain (44-pin PLCC only). amplifier (44-pin PLCC only). through a high-value resistor. series resistor through a high-value resistor. — 9 NC — No Connection. May be used as a tie point. 15 10 AGND — Analog Signal Ground. — 11 NC — No Connection. May be used as a tie point. 16 12 VCC — 5 V Power Supply. 17 13 VBAT1 — Battery Supply. Negative high-voltage battery, higher in magnitude than VBAT2 . than VBAT1 , used to reduce power dissipation on short loops. 19 15 BGND — Battery Ground. Ground return for the battery supply. ence of a ring ground. To use, connect a 100 kΩ resistor to VCC . unused, the pin should be connected to ground. 22 18 BS2 — Battery Switch Slowdown. Connect a 0.22 µF capacitor to pin BS1. — 20 NC — No Connection. May be used as a tie point. — 21 NC — No Connection. May be used as a tie point. 24 22 PT I/O Protected Tip. The output of the tip driver amplifier and input to loop sensing. Connect to loop through overvoltage protection. ing circuitry. Connect to loop through overvoltage protection.

Table 2. Pin Descriptions (continued) — 24 NC — No Connection. May be used as a tie point. 26 25 B2 I State Control Input. B0, B1, B2, and BR determine the state of the SLIC. See Table 3. Pin B2 has a 40 kΩ pull-up. 27 26 B1 I State Control Input. B0, B1, B2, and BR determine the state of the SLIC. See Table 3. Pin B1 has a 40 kΩ pull-up. 28 27 B0 I State Control Input. B0, B1, B2, and BR determine the state of the SLIC. See Table 3. Pin B0 has a 40 kΩ pull-up. 29 28 BR I State Control Input. B0, B1, B2, and BR determine the state of the SLIC. See Table 3. Pin BR has a 40 kΩ pull-up. — 29 NC — No Connection. May be used as a tie point. — 30 NC-NTP — No Connection. May not be used as a tie point. — 31 NC — No Connection. May be used as a tie point. 30 32 TG — Transmit Gain. Connect a 4.32 kΩ resistor from this pin to VTX. 31 33 VTX O The voltage at this pin is directly proportional to the differential tip/ring current. 32 34 TXI — ac/dc Separation. Connect a 0.1 µF capacitor from this pin to VTX. off-hook condition exists or that ringing has been tripped. 2 — VEE — –5 V Power Supply L8560C. 2 — NC — No Connection L8560A/D/F. May be used as a tie point. — 36 NC — No Connection. May be used as a tie point. differential ac tip/ring current. trols the ac differential voltage on tip and ring. ac differential voltage on tip and ring. — 40 NC — No Connection. May be used as a tie point. 6 41 FB2 — Polarity Reversal Slowdown. Connect a capacitor to ground. 7 42 FB1 — Polarity Reversal Slowdown. Connect a capacitor to ground. DCOUT to ground with the trip at DCR (44-pin PLCC only).

Table 3. Input State Coding Table 4. Supervision Coding off-hook condition or a ring trip causes output NSTAT to go low. off-hook condition or a ring trip causes output NSTAT to go low. off-hook condition or a ring trip causes output NSTAT to go low. off-hook condition or a ring trip causes output NSTAT to go low. cates current flowing in the ring lead. drive amplifiers. Pin PT is positive with respect to pin PR. On-hook transmission is disabled. high-impedance state (>100 kΩ ). VBAT2 is applied to the SLIC. 5 V square wave to input pin B1. Ringing frequency is the frequency of the input wave at B1.

April 2000L8560 Low-Power SLIC with Ringing 10 Lucent Technologies Inc. Absolute Maximum Ratings (TA = 25 °C) Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. Some of the known examples of conditions that cause such potentials during powerup are 1) an inductor connected to tip and ring can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters, and 2) inductance in the VBAT lead could resonate with the VBAT filter capacitor to cause a destructive overvoltage. Parameter Symbol Value Unit 5 V Power Supply VCC 7.0 V –5 V Power Supply (L8560C) VEE –7.0 V Battery (talking) Supplies VBAT1, VBAT2 –75 V VBAT2 Magnitude IVBAT2 I IVBAT1 I + 0.4 V Logic Input Voltage — –0.5 to +7.0 V Analog Input Voltage — –7.0 to +7.0 V Maximum Junction Temperature TJ 165 °C Storage Temperature Range Tstg –40 to +125 °C Relative Humidity Range R H 5 to 95 % Ground Potential Difference (BGND to AGND) — ±3 V PT or PR Fault Voltage (dc) VPT , VPR (VBAT1 – 5) to +3 V PT or PR Fault Voltage (10 x 1000 µs) VPT , VPR (VBAT1 – 15) to +15 V Current into Ring Trip Inputs IRTSP , IRTSN ±240 µA

Lucent Technologies Inc. 11 Data Sheet April 2000 L8560 Low-Power SLIC with Ringing Recommended Operating Conditions

Electrical Characteristics

Minimum and maximum values are testing requirements in the temperature range of 25 °C to 85 °C and battery range of –24 V to –70 V. These minimum and maximum values are guaranteed to –40 °C based on component simulations and design verification of samples, but devices are not tested to –40 °C in production. The test circuit shown in Figure 5 is used, unless otherwise noted. Positive currents flow into the device. Typical values are characteristics of the device design at 25 °C based on engineering evaluations and are not part of the test requirements. Supply values used for typical characterization are VCC = 5.0 V, VEE = –5.0 V, VBAT1 = –48 V, VBAT2 = –25.5 V, unless otherwise noted. Parameter Min Typ Max Unit Ambient Temperature –40 — 85 °C Loop Closure Threshold-detection Programming Range 5 10 ILIM mA dc Loop Current-limit Programming Range 5 40 50 mA On- and Off-hook 2-wire Signal Level (@ ZLOOP = 200 Ω ) — — 2.2 Vrms ac Termination Impedance Programming Range 150 600 1300 Ω VBAT1 –24 –48 –70 V VBAT2 –16 — VBAT1 V VCC 4.5 5.0 5.5 V dc Feed Resistance Programming Range (excl. RP) 55 55 760 Ω

Table 5. Power Supply VCC = 5.0 V, VEE = –5.0 V, VBAT1 = –48 V, VBAT2 = –19 V, unless otherwise noted.

1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. VEE used for L8560C version only.

Table 6. 2-Wire Port

1. The longitudinal current is independent of dc loop current.
2. Current-limit ILIM is programmed by a resistor, RPROG , from pin IPROG to DCOUT. ILIM is specified at the loop resistance where current limiting

will be increased by a factor of 2.8.

1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Specification is reduced to |V

BAT1 + 10.5 V| minimum when VBAT1 = –70 V at 85 °C. 5.IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

1. Longitudinal balance of circuit card will depend on loop series protection resistor matching and magnitude.
2. Tested at 1000 Hz only. Full frequency specifications guaranteed by design and device characterization.

200 Hz to 2999 Hz Forward/Reverse Battery

3000 Hz to 3400 Hz Forward/Reverse Battery

200 Hz to 2999 Hz Forward Battery

3000 Hz to 3400 Hz Forward Battery

200 Hz to 2999 Hz Reverse Battery

3000 Hz to 3400 Hz Reverse Battery

200 Hz to 4 kHz 46 — — dB

Table 7. Analog Pin Characteristics

1. Loop closure threshold is programmed by resistor RLCTH from pin LCTH to pin DCOUT.
2. Ring ground threshold is programmed by resistor RICM2 from pin ICM to VCC .
3. This parameter is not tested in production. It is guaranteed by design and device characterization.

N is the sourcing current at RTSN. Guaranteed if IN is within 5 µA to 30 µA. Table 8. Uncommitted Op Amp Characteristics (44-Pin PLCC Only)

Table 9. ac Feed Characteristics

1. Set by external components. Any complex impedance R1 + R2 || C between 150 Ω and 1300 Ω can be synthesized.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. Return loss and transhybrid loss are functions of device gain accuracies and the external hybrid circuit. Guaranteed performance assumes

1% tolerance external components. Not tested in production.

200 Hz to 300 Hz

200 Hz to 500 Hz

500 Hz to 3400 Hz

Table 10. Logic Inputs and Outputs — Voltage, minimum 35 Vrms, maximum 100 Vrms. — Frequency, 17 Hz to 23 Hz. — The circuits in Figure 4 will not cause ringing trip. Figure 4. Ring Trip Circuits

2222 Lucent Technologies Inc. Data Sheet April 2000L8560 Low-Power SLIC with Ringing Applications (continued) dc Applications (continued) Starting from the on-hook condition and going through to a short circuit, the curve passes through two regions: Region 1: On-hook and low loop currents. In this region, the slope corresponds to the dc resistance of the SLIC, R dc1 (default is 55 Ω typical). The open circuit voltage is the battery voltage less the overhead voltage of the device, VOH (default is 6.7 V typical). These values are suitable for most applications but can be adjusted if needed. For more information, see the sections titled Adjusting dc Feed Resistance or Adjusting Overhead Voltage. Region 2: Current limit. The dc current is limited to a starting value determined by external resistor R PROG , an internal current source, and the gain from tip/ring to pin DCOUT. Current limit is set by the equation: IPROG x RPROG = ILIM x BDCOUT Where: IPROG = the current from an internal current source R PROG = the external resistor used to set the current limit BDCOUT = the transconductance from tip/ring to DCOUT, which is nominally 41.67 V/A During nonringing modes, the internal current source is set at 75 µA, thus: IPROG x RPROG = ILIM x BDCOUT R PROG = ILIM x BDCOUT /IPROG R PROG (K) = ILIM (mA) x 0.04167 (V/mA)/75e–3 (mA) R PROG (K) = 0.556 x ILIM (mA) Testing data shows that: R PROG (K) = 0.616 x ILIM (mA) This equation is a first-order estimation of the loop cur- rent at current-limit range. For more precise loop current at current-limit range, the loop current is also determined by loop length, protec- tion resistance, and battery voltage. It can be shown through calculations as follows: Current-limit onset (I Lonset): ILonset (mA) = Loop resistance where current-limit onsets (RLonset): R Lonset (Ω ) = x 1000 – 2R P – Rdc Tip/ring voltage where current-limit onsets (VT/Ronset): VT/Ronset = Tip/ring voltage when loop resistance is Rloop (VT/Rloop): VT/Rloop (V) = Iloop (mA) x RLOOP (Ω )/1000 Loop current is now given by: I loop (mA) = ILonset (mA) + (VT/Ronset – VT/Rloop) (V)/12.5 (kΩ ) or I loop (mA) = Current limit is not sensitive to temperature variation. Overhead Voltage In order to drive an on-hook ac signal, the SLIC must set up the tip and ring voltage to a value less than the bat- tery voltage. The amount that the open loop voltage is decreased relative to the battery is referred to as the overhead voltage and is expressed as: V OH = |VBAT | – (VPT – VPR ) Without this buffer voltage, amplifier saturation will occur and the signal will be clipped. The L8560 is auto- matically set at the factory to allow undistorted on-hook transmission of a 3.17 dBm signal into a 900 Ω loop impedance. The drive amplifiers are capable of 4 Vrms minimum AMP ). So, the maximum signal the device can guaran- tee is: VT/R = 4 V For applications where higher signal levels are needed, e.g., periodic pulse metering, the 2-wire port of the SLIC can be programmed with pin DCR (pin DCR is not available in the 32-pin PLCC package). The first step is to determine the amount of overhead voltage needed. The peak voltage at output of tip and ring amplifiers is related to the peak signal voltage by: R PROG K() V BAT V OH–() V() V BAT V OH–() R Lonset× ILonset mA() V T Ronset⁄ V()+ 12.5 kΩ()⁄ ZT/R V AMP = VT/R 1 2R P ZT/R  Λ Λ

Lucent Technologies Inc. 25 Data Sheet April 2000 L8560 Low-Power SLIC with Ringing Applications (continued) dc Applications (continued) Ring Ground Detection Pin ICM sinks a current proportional to the longitudinal loop current. It is also connected to an internal compar- ator whose output is pin RGDET. In a ground start application where tip is open, the ring ground current is half differential and half common mode. In this case, to set the ring ground current threshold, connect a resis- tor R ICM from pin ICM to VCC . Select the resistor according to the following relation: R ICM (kΩ ) = The above equation is shown graphically in Figure 17. It applies for the case of tip open. The more general equation can be used in ground key applications to detect a common-mode current ICM: R ICM (kΩ ) = Longitudinal Balance The SLICs are graded with different codes to represent different longitudinal balance specifications. The num- bers are guaranteed by testing (Figures 5 and 8). How- ever, for specific applications, the longitudinal balance may also be determined by termination impedance, protection resistance, and especially by the mismatch between protection resistors at tip and ring. This can be illustrated by: LB = 20 x log where: LB: longitudinal balance RP: protection resistor value in Ω ZT: magnitude of the termination impedance in Ω : protection resistor mismatch in Ω Δ: SLIC internal tip/ring sensing mismatch The Δ can be calculated using the above equation with these exceptions: = 0, ZT = 600 Ω, RP = 100 Ω , and the longitudinal balance specification on a specific code. Now with Δ available, the equation will predict the actual longitudinal balance for RP, ZT, and . Be aware that ZT may vary with frequency for complex impedance applications. Power Derating Thermal considerations can affect the choice of a 32-pin PLCC or a 44-pin PLCC package. Operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop, and protection resis- tor values will influence the overall thermal perfor- mance. This section shows the relevant design equations and considerations in evaluating the SLIC thermal performance. First, consider the L8560 SLIC in a 44-pin PLCC pack- age. The still-air thermal resistance is 47 °C/W; how- ever, this number implies zero airflow as if the L8560 were totally enclosed in a box. A more realistic number would be 43 °C/W. This is an experimental number that represents a thermal impedance with no forced airflow (i.e., from a muffin fan) but from the natural airflow as seen in a typical switch cabinet. The SLIC will enter the thermal shutdown state at typi- cally 165 °C. The thermal shutdown design should ensure that the SLIC temperature does not reach 165 °C under normal operating conditions. Assume a maximum ambient operating temperature of 85 °C, a maximum current limit of 45 mA, and a maxi- mum battery of –52 V. Further, assume a (worst case) minimum dc loop of 100 Ω and that 100 Ω protection resistors are used at both tip and ring. 1. T TSD – TAMBIENT(max) = allowed thermal rise. 165 °C – 85 °C = 80 °C 2. Allowed thermal rise = package thermal impedance • SLIC power dissipation. 80 °C = 43 °C/W • SLIC power dissipation SLIC power dissipation (PD ) = 1.9 W Thus, if the total power dissipated in the SLIC is less than 1.9 W, it will not enter the thermal shutdown state. Total SLIC power is calculated as: Total P D = maximum battery • maximum current limit + SLIC quiescent power. For the L8560, SLIC quiescent power (PQ ) is approxi- mated at 0.167 W. Thus, Total PD = (–52 V • 45 mA) + 0.167 W Total PD = 2.34 W + 0.167 W Total PD = 2.507 W V CC 120× V CC 60×

368 RP+() 368 ZT RP–+()×

ε ε ε

2626 Lucent Technologies Inc. Data Sheet April 2000L8560 Low-Power SLIC with Ringing Applications (continued) Power Derating (continued) The power dissipated in the SLIC is the total power dis- sipation less the power that is dissipated in the loop. SLIC PD = Total power – Loop power Loop power = (ILIM)2 • (RLOOP(dc) min + 2RP) Loop power = (45 mA)2 • (100 Ω + 200 Ω ) Loop power = 0.61 W SLIC power = 2.507 W – 0.61 W SLIC power = 1.897 W < 1.9 W Thus, in this example, the thermal design ensures that the SLIC will not enter the thermal shutdown state. The next example uses the 32-pin PLCC package and demonstrates the technique used to determine the maximum allowed current. In this example, assume a 0 °C to 70 °C operating range. Thus, T TSD – TAMBIENT (max) = allowed thermal rise 165 °C – 70 °C = 95 °C To estimate the open-air thermal impedance, use the 43 °C/W parameter from the 44-pin PLCC and ratio the lead count. Thermal impedance (32-pin PLCC) = 48 °C/W = 59 °C/W Again: Allowed thermal rise = thermal impedance • SLIC power dissipation 95 °C = 59 °C/W

• SLIC power dissipation SLIC PD = 1.6 W In this example, again assume the dc loop + 2 • protec- tion resistors = 300 Ω , then: (ILIM)(VBAT max) + PQ – (ILIM)2 (Rdc + 2 RP) = 1.6 W I • 52 + 0.167 – I2 300 = 1.6 W 300 I2 – 52 I + 1.433 = 0 This is a quadratic equation whose solution is in the form: X = ILIM = ILIM = Ignore the “+” term: ILIM = Thus, 34 mA is the maximum allowable current limit in the 32-pin PLCC package under the conditions given in this example. This type of analysis should be performed under the conditions of the user’s particular application to ensure adequate thermal design. Battery Switch The L8560 SLIC provides an input for an auxiliary bat- tery. Called V BAT2 , this power supply should be lower in magnitude than the primary battery VBAT1 . Under an acceptable loop condition, VBAT2 can be switched to provide the loop power through the amplifiers of the SLIC. The dc template, described in previous sections, is determined by the battery that is active—either V BAT1 or VBAT2 . There are several important applications where use of a lower-voltage battery in the off-hook state is desired to provide dc current to the loop, yet a higher-voltage battery is desired in on-hook or ringing modes. These applications are typically short-loop applications, such as an ISDN terminal adapter, fiber-in-the-loop applica- tions, or a cable telephony interface. Typically, in these applications, the maximum dc loop resistance (which includes the off-hook telephone handset plus twisted-cable pair) is relatively low. For example, Bellcore TA-909, Generic Requirements and Objectives for Fiber in the Loop Systems, specifies that in the off-hook state, 20 mA must be provided into a 430 Ω dc loop. To meet these requirements, a lower battery in the off-hook condition is important to mini- mize off-hook power consumption. Power conservation is important from a cost of energy point of view and is vital in remotely powered POTS interface applications. While use of a low-voltage battery in off-hook short dc loops is important, certain on-hook applications, such as providing a balanced power ring signal or maintain- ing compatibility with certain CPE such as answering machines, may require a higher magnitude battery. With the logic-controlled battery switch, the L8560 is able to provide a higher-voltage battery to meet on- hook battery voltage requirements. At the same time, the L8560 can accept a lower-voltage auxiliary battery during short-loop, off-hook applications. If a dc/dc con- verter with two fixed voltage outputs is used, tie the battery voltage that is higher in magnitude to V BAT1 and the voltage that is lower in magnitude to VBAT2 . If it is –b b2 4ac–± 52 31.4± 52 – 31.4

Lucent Technologies Inc. 27 Data Sheet April 2000 L8560 Low-Power SLIC with Ringing Applications (continued) Battery Switch (continued) desired to use a single battery supply or a dc/dc con- verter with a single programmable voltage output, tie V BAT1 to VBAT2 and connect the battery to this node. Note that VBAT1 is forced during the balanced ringing state. VCC /VEE Supplies The L8560A/D/E/F SLICs are designed to operate using battery and only a 5 V power supply. In this mode of operation, power for the tip/ring drive amplifiers, dc feedback loop, internal amplifiers, logic, ac, and refer- ence circuits is drawn from the negative battery (and 5 V supply). While the L8560A/D/E/F type devices offer very low power dissipation in both the sleep and active states, further reduction in power dissipation is possible by use of battery and +5 V and –5 V power supplies. The L8560C operates using battery, +5 V, and –5 V power supplies. When the –5 V is used, the internal amplifi- ers, logic, ac, and reference circuits draw power from the negative –5 V supply, not the negative battery. Since the magnitude of the –5 V supply is less than the battery, power consumption is reduced. With the L8560C, the tip/ring drive amplifiers and dc feedback loop still draw power from the battery. Power Ringing The L8560 ringing SLIC is designed with the capability of generating balanced power ring signal to tip and ring. Because the SLIC itself generates the power ring- ing signal, no ring relay is needed in this mode of oper- ation. Alternatively, the L8560 SLIC can also be used in the more standard battery-backed, unbalanced ringing application. In this case, the ring signal is generated by a central ring generator and is bused to individual tip/ ring pairs. A ringing relay is used during ringing to dis- connect the SLIC from, and apply the ring generator to, the tip and ring pair. This section discusses in detail the use of the L8560 ringing SLIC in either mode of application. Ringing SLIC Balanced Ring Signal Generation The internal dc current source drives current into or pulls current out from C FB1 and CFB2 depending on whether the SLIC is operating at battery forward or at battery reversal. The voltage at PT then will be positive with respect to PR or vice versa. If a square wave sig- nal is added to B1, the SLIC will be operating consecu- tively at battery forward, and then battery reversal. The differential output at PT and PR can be a balanced power ringing signal. Its frequency is equal to that of the square wave at B1. Its slew rate is determined by the size of the capacitors C FB1 and CFB2 . If a sinusoidally modulated pulse-width-modulation (PWM) signal is applied to B1, the differential output at PT and PR will be sinusoidal. Theoretically, it provides power ringing in a sinusoidal format. For more informa- tion, please refer to the L8560 Sinusoidal Ringing Gen- eration Using a PWM Input to B1 Application Note. POTS for ISDN Terminal Adapters The L8560 ringing SLIC is designed to provide a bal- anced power ring signal to tip and ring. This mode of operation is suited for short-loop, plain old telephone service (POTS) applications, such as ISDN terminal adapters (TA). When ISDN was first visualized, it was thought that we would all exchange our existing telephones for new, full-feature ISDN phones. Digital technology would drive these sets to very low costs. While this may hap- pen in the future, the current demand is for the ISDN TA to service a standard analog telephone. The chal- lenges of this application are discussed here along with a suggested solution. Until recently, POTS has been the exclusive domain of the service provider. Over its 100-year history, any architectural change was always required to be com- patible with the existing installed local loop plant and all telephone sets. If this is the expectation of the TA, it would be capable of being connected into the residence phone wiring to drive every phone in the house. It would also be designed with enough backup battery to provide unin- terrupted service during electrical power interruptions. In this case, adherence to a standard, such as Bellcore’s TA-909, is recommended. For the case where a TA is only going to provide limited service, the design can be made less costly by limiting the scope of the device. An example of this limited scope would be the provision of analog jacks for a FAX/ modem and a phone set near the TA in a home office environment. A block diagram of a POTS design is out- lined in Figure 28.

April 2000L8560 Low-Power SLIC with Ringing 30 Lucent Technologies Inc. Applications (continued) Power Ringing (continued) At the trip point, the internal current repeater will force IRTSP to be equal to IRTSN and VRTSP will be equal to VRTSN , which is –8.2 V. Thus, at the trip point: Thus: Solving for VDCOUT , the voltage at DCOUT at the ring trip point is given by: The loop current at ring trip is given by: ILOOP(TRIP) = (VDCOUT )/(βDCOUT ) For the L8560, the gain (β) at pin DCOUT is 41.67 V/A. Capacitors C2 and C4, along with resistors R2 and R4, respectively, form low-pass filters to filter the ac voltage seen at DCOUT before it is applied to the ring trip comparator input. The lower the pole of the filter, the less the ripple, but also the slower the state transition at NSTAT. Poles in the neighborhood of 2.5 Hz—3 Hz are suggested, as given by: f LP = fLP = In the reference designs discussed in the next section, the ring trip threshold is set for 50 mA with: R 1 = 210 kΩ R 2 = 124 kΩ C 2 = 0.1 µF R 3 = 562 kΩ R 4 = 351 kΩ C 4 = 0.1 µF Except for L8560CAU, the internal voltage for L8560CAU is –5.7 V. 133 kΩ should be used for R1. IRTSN R 3  8.2 V–()– R 1R 3 IRTSN IRTSP 08 . 2–()– R 4 R 3  V DCOUT 8.2 V+ R 1R 3 R 4 V DCOUT 8.2 R3 R 1+() R 1 R 3R 4 R 3R 4 R 3 (TRIP) 2πR 2C 2 2πR 4C 4

U-interface transceiver and the T7256 SCNT1 interface. † Required only for L8560A/C versions. Figure 33. POTS Interface with Balanced Ringing Using L8560 SLIC and T8503 Codec

Table 11. Parts List for Balanced Ringing Using T8503 Codec

• Required for L8560A/L8560C version only.

SLIC L8560 Subscriber line interface circuit (SLIC). Protector L7591 Secondary protection. Codec T8503 First-generation codec. R PT 30 Ω fusible Overcurrent protection. R PR 30 Ω fusible Overcurrent protection. C BAT1 0.1 µF, 20%, 100 V VBAT filter capacitor. C BAT2 0.1 µF, 20%, 100 V VBAT filter capacitor. C CC 0.1 µF, 20%, 10 V VCC filter capacitor. C F1 0.47 µF, 20%, 100 V With CF2, improves idle-channel noise. C F2 0.1 µF, 20%, 100 V With CF1, improves idle-channel noise. C BS 0.22 µF, 20%, 100 V Slows battery switch transition. C ST 0.1 µF, 20%, 10 V Loop stability. R ST 100 Ω , 1%, 1/8 W Loop stability. R PROG 14 kΩ , 1%, 1/8 W Sets dc loop current. R TG 4.32 kΩ , 1%, 1/8 W Sets internal transmit path gain to 19.2. C B2 0.1 µF, 20%, 10 V ac/dc separation capacitor. C C1 0.1 µF, 20%, 10 V dc blocking capacitor. C C2 0.1 µF, 20%, 10 V dc blocking capacitor. R T3 165 kΩ , 1%, 1/8 W With RGP and RRCV , sets ac termination impedance. R RCV 178 kΩ , 1%, 1/8 W With RGP and RT3, sets receive gain. R GP 41.2 kΩ , 1%, 1/8 W With RT3 and RRCV , sets ac termination impedance and receive gain. C GP 220 pF, 20%, 10 V Loop stability. C TG * 27 pF, 20%, 10 V Loop stability. R GP2 1.21 kΩ , 1%, 1/8 W Loop stability. R GN 30.1 kΩ , 1%, 1/8 W Compensates for input bias offset at RCVN/RCVP. R T6 60.4 kΩ , 1%, 1/8 W With RX, sets transmit gain in codec. R X 71.5 kΩ , 1%, 1/8 W With RT6, sets transmit gain in codec. R HB1 143 kΩ , 1%, 1/8 W Sets hybrid balance. R LCTH 8.25 kΩ , 1%, 1/8 W Sets loop closure (off-hook) threshold. R 1 (RTS2)† 210 kΩ , 1%, 1/8 W With R2, R3, and R4, sets ring trip threshold. R 2 (RTSN) 124 kΩ , 1%, 1/8 W With R1, R3, and R4, sets ring trip threshold. C 2 (CRTSN) 0.1 µF, 20%, 50 V With R2, sets pole of low-pass ring trip sense filter. R 3 (RTS3) 562 kΩ , 1%, 1/8 W With R1, R2, and R4, sets ring trip threshold. R 4 (RTSP) 351 kΩ , 1%, 1/8 W With R1, R2, and R3, sets ring trip threshold. C 4 (CRTSP) 0.1 µF, 20%, 10 V With R4, sets pole of low-pass ring trip sense filter.

Figure 34. Ring Trip Equivalent Circuit and pole at 2 Hz was implemented to prevent false ring trip.

• Required for L8560A/L8560C version only.

Figure 35. Basic Loop Start Application Circuit Using T7504 Codec and Bused Ringing

Table 12. Parts List for Loop Start with Bused Ringing and Ground Start Applications (continued) R GX 4.32 kΩ , 1%, 1/8 W Sets internal transmit path gain of 9.6. C B2 0.1 µF, 20%, 10 V ac/dc separation capacitor. R T3 174 kΩ , 1%, 1/8 W With RGP and RRCV , sets ac termination impedance. R RCV 100 kΩ , 1%, 1/8 W With RGP and RT3, sets receive gain. R GP 41.2 kΩ , 1%, 1/8 W With RT3 and RRCV , sets ac termination impedance and receive gain. C GP 220 pF, 20%, 10 V Loop stability. R GP2 1.21 kΩ , 1%, 1/8 W Loop stability. R GN 29.4 kΩ , 1%, 1/8 W Compensates for input bias offset at RCVN/RCVP. C C1 0.1 µF, 20%, 10 V dc blocking capacitor. C C2 0.1 µF, 20%, 10 V dc blocking capacitor. R T6 49.9 kΩ , 1%, 1/8 W With RX, sets transmit gain in codec. R X 75.0 kΩ , 1%, 1/8 W With RT6, sets transmit gain in codec. R HB1 75.0 kΩ , 1%, 1/8 W Sets hybrid balance. R LCTH 8.25 kΩ , 1%, 1/8 W Sets loop closure (off-hook) threshold. R TS1 402 Ω , 5%, 2 W Ringing source series resistor. R TS2 274 kΩ , 1%, 1/8 W With CRTS2 , forms first pole of a double pole, 2 Hz ring trip sense filter. C RTS1 0.022 µF, 20%, 5 V With RTSN and RTSP , forms second 2 Hz filter pole. C RTS2 0.27 µF, 20%, 100 V With RTS2 , forms first 2 Hz filter pole. R TSN 2 MΩ , 1%, 1/8 W With CRTS1 and RTSP , forms second 2 Hz filter pole. R TSP 2 MΩ , 1%, 1/8 W With CRTS1 and RTSN , forms second 2 Hz filter pole. C ICM 0.47 µF, 20%, 10 V Provides 60 Hz filtering for ring ground detection. R GDET 100 kΩ , 20%, 1/8 W Digital output pull-up resistor. R ICM2 71.5 kΩ , 1%, 1/8 W Sets ring ground detection threshold.

to program these values are also shown. Table 13. 600 Ω Design Parameters done from the PCM highway to the transmit port. feature and selection summary. hybrid balance are set internally.

ponents to synthesize a real termination impedance. Figure 37. Use these to synthesize real termination

1. The expression for ZHB becomes:

and VTX. This is a recommended approach.

1 R T3

1 R RCV

4040 Lucent Technologies Inc. Data Sheet April 2000L8560 Low-Power SLIC with Ringing Applications (continued) Design Examples (continued) Complex Termination Impedance Design Example Using L8560 Without Spare Op Amp Complex termination is specified in the form: 5-6396(F) To work with this application, convert termination to the form: 5-6398(F) where: R 1´ = R1 + R2 R 2´ = (R 1 + R2) C´ = C ac Interface Using First-Generation Codec R TGP /RTGS /CGS (ZTG ): These components give gain shaping to get good gain flatness. These components are a scaled version of the specified complex termina- tion impedance. Note for pure (600 Ω ) resistive terminations, compo- nents R TGS and CGS are not used. Resistor RTGP is used and is still 4.32 kΩ . R X/RT6: With other components set, the transmit gain (for complex and resistive terminations) RX and RT6 are varied to give specified transmit gain. R T3/RRCV /RGP : For both complex and resistive termina- tions, the ratio of these resistors set the receive gain. For resistive terminations, the ratio of these resistors set the return loss characteristic. For complex termina- tions, the ratio of these resistors set the low-frequency return loss characteristic. C N /RN1 /RN2 : For complex terminations, these compo- nents provide high-frequency compensation to the return loss characteristic. For resistive terminations, these components are not used and R CVN is connected to ground via a resistor. R HB : Sets hybrid balance for all terminations. Set ZTG —gain shaping: ZTG = RTGP || RTGS + CGS which is a scaled version of ZT/R (the specified termination resistance) in the R TGP must be 4.32 kΩ to set SLIC transconductance to

400 V/A

R TGP = 4.32 kΩ At dc, C TGS and C´ are open. R TGP = M x R1´ where M is the scale factor. M = It can be shown: R TGS = M x R2´ and C TGS = R 2 C R 1 R 1´ C´R 2´ R 1 R 2 R 2  2 4320 C ′

Figure 39. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown) work at the midband frequency of 1000 Hz. loss/gain due to the impedance transformation. X (dB) = TX (specified[dB]).

4242 Lucent Technologies Inc. Data Sheet April 2000L8560 Low-Power SLIC with Ringing Applications (continued) Design Examples (continued) Receive Gain Ratios of RRCV , RT3, RGP will set both the low-frequency termination and receive gain for the complex case. In the complex case, additional high-frequency compen- sation, via C N , RN1 , and RN2 , is needed for the return loss characteristic. For resistive termination, CN , RN1 , and RN2 are not used and RCVN is tied to ground via a resistor. Determine the receive gain, gRCV , taking into account the impedance transformation in a manner similar to transmit gain. R X (dB) = RX (specified[dB]) + 20 log R X (dB) = 20 log gRCV Then: gRCV = and low-frequency termination ZTER(low) = + 2R P ZTER(low) is the specified termination impedance assum- ing low frequency (C or C´ is open). R P is the series protection resistor. These two equations are best solved using a computer spreadsheet. Next, solve for the high-frequency return loss compen- sation circuit, CN , RN1 , and RN2 : C N R N2 = C G RTGP R N1 = RN2 There is an input offset voltage associated with nodes R CVN and RCVP . To minimize the effect of mismatch of this voltage at T/R, the equivalent resistance to ac ground at R CVN should be approximately equal to that at RCVP . Refer to Figure 40 on page 43 (with dc block- ing capacitors). To meet this requirement, RN2 = RGP || R T3. Hybrid Balance Set the hybrid cancellation via RHB . R HB = R EQ  1– R X

Figure 40. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex

1. This is because the codec is referenced to 2.5 V and the SLIC to ground—with the ac coupling, a dc bias at

T/R is eliminated and power associated with this bias is not consumed. PSPICE * model for the L8560 is available.

• PSPICE is a registered trademark of MicroSim Corporation.

April 2000L8560 Low-Power SLIC with Ringing 44 Lucent Technologies Inc. Outline Diagrams 32-Pin PLCC Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Lucent Technologies Sales Representative. 5-3813r2 (F) 0.10 SEATING PLANE

0.38 MIN

TYP1.27 TYP 0.330/0.533 143 0 13 21 14 20 12.446 ± 0.127 11.430 ± 0.076 PIN #1 IDENTIFIER ZONE 14.986 ± 0.127 13.970 ± 0.076 3.175/3.556

Lucent Technologies Inc. 45 Data Sheet April 2000 L8560 Low-Power SLIC with Ringing Outline Diagrams (continued) 44-Pin PLCC Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Lucent Technologies Sales Representative. 5-2506r.8(F) 4.57 MAX 1.27 TYP 0.53 MAX 0.10 SEATING PLANE

0.51 MIN

PIN #1 IDENTIFIER ZONE

16.66 MAX

17.65 MAX

16.66 MAX 17.65 MAX

April 2000L8560 Low-Power SLIC with Ringing Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. N o liability is assum ed as a result of their use or application. No rights under any patent accompa ny the sale of any such product(s) or information. Co pyright © 2000 Lucent Technologies Inc. All Rights Reserved April 2000 DS00 -172ALC (Replaces D S99-124ALC) For additional information, contact your M icroelectronics Group Account M anager or the following: IN TERNE T: http://www .lucent.com/micro E-M AIL: docm aster@mi cro.lucent.com N . AM ER ICA: M icroelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown , PA 18103 1-800-372-2447, FAX 610-712-4106 (In CAN AD A: 1-800-553-2448, FAX 610-712-4106) AS IA PACIFIC :M icroelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 C intech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 C HIN A: M icroelectronics Group, Lucent Technologies (C hina) C o., Ltd., A-F2, 23/F, Zao Fong U niverse Building, 1800 Zhong Shan Xi R oad, Shanghai 200233 P. R. Ch ina Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: M icroelectronics Group, Lucent Technologies Japan Ltd., 7-18, H igashi-Gotanda 2-chom e, Shinagaw a-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R OP E: D ata Requests: M ICR O ELECT R ONIC S GR OU P D ATALIN E: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:G ER MA N Y: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FR AN CE: (33) 1 40 83 68 00 (Paris), SWE D EN : (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (H elsinki), ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid)

Ordering Information

Device Code Description Package Comcode LU CL8 560AAU-D Low-power SLIC (Dry-bagged) 32-Pin PLCC 107957375 LU CL8 560AAU-DT Low -power SLIC (Tape and Reel, Dry-bagged) 32-Pin PLCC 107957383 LU CL8 560AP-D Low-power SLIC (Dry-bagged) 44-Pin PLCC 107891111 LU CL8 560AP-DT Low -power SLIC (Tape and Reel, Dry-bagged) 44-Pin PLCC 107891129 LU CL8 560CAU-D Low-power SLIC (Dry-bagged) 32-Pin PLCC 107953390 LU CL8 560CAU-DT Low -power SLIC (Tape and Reel, Dry-bagged) 32-Pin PLCC 107953408 LU CL8 560DAU-D Low-power SLIC (Dry-bagged) 32-Pin PLCC 108130576 LU CL8 560DAU-DT Low -power SLIC (Tape and Reel, Dry-bagged) 32-Pin PLCC 108130584 LU CL8 560EP-D Low-power SLIC (Dry-bagged) 44-Pin PLCC 108133000 LU CL8 560EP-DT Low -power SLIC (Tape and Reel, Dry-bagged) 44-Pin PLCC 108133018 LU CL8 560FAU-D Low-power SLIC (Dry-bagged) 32-Pin PLCC 108190885 LU CL8 560FAU-DT Low -power SLIC (Tape and Reel, Dry-bagged) 32-Pin PLCC 108190893 LU CL8 560GP-D Low-power SLIC (Dry-bagged) 44-Pin PLCC 108190935 LU CL8 560GP-DT Low -power SLIC (Tape and Reel, Dry-bagged) 44-Pin PLCC 108190943