L7585G AGERE | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 22

Technical content

Features

■ Low active power ■ Quiet tip/ring polarity reversal ■ Distortion-free on-hook transmission ■ 35 V to 60 V power supply operation ■ 14 operating states: — Forward battery active — Reverse battery active — Ground start (3) — Forward battery ring open — Reverse battery ring open — Reverse battery tip open — High impedance — Ringing (2) — Low current (2) — Disconnect ■ Self-test in all operating states ■ Independent, adjustable ac and dc parameters: — Switchhook detector threshold — Loop current limit — dc feed resistance — Termination impedance ■ Integrated ringing access relay ■ Integrated test-in relay ■ Integrated relay driver ■ Integrated ring trip detector ■ Thermal protection ■ 44-pin, metric quad flat package (MQFP)

Description

The L7585G Full-Feature, Low-Power Subscriber Loop Interface Circuit (SLIC) and Switch integrates the battery feed, test access relay, and ringing relay that are necessary to interface a codec to the tip and ring of a subscriber loop into one low-power, low-cost package. It is built using a 90 V complementary bipo- lar (CBIC) process and a 320 V Bipolar-CMOS- DMOS (BCDMOS) process. The device is available in a 44-pin MQFP package. The device can be connected directly to the Agere Systems Inc. T8531/T8536 16-Channel Programma- ble Codec Chip Set without the need for any ac inter- face components.

Figure 1. Architectural Diagram

Figure 2. 44-Pin Diagram (MQFP)

Table 1. Pin Descriptions imize the amount of PWB copper on all leads connected to this device for the lowest operating temperature. 1 CF1 I/O Filter Capacitor 1. Connect a 0.22 µF, 100 V capacitor from this pin to pin CF2. needed, the pin can be left open. needed, the pin can be left open. 4B G N D— Battery Ground. Ground return for the battery (VBAT ) supply. 5V BAT — Battery Supply. Negative high-voltage power supply. 6 VBAT — Battery Supply. Negative high-voltage power supply. 7 VSP — +10 V Supply. +10 V bias supply for switch circuitry. unaffected by data on pins B0—B5. 9C L K I Clock. Clock input. of this device enters thermal shutdown, NDET will be forced low. 11 DGND — Digital Ground. Ground return for VCCD and relay driver flyback current. low input on B5 is latched into the SLIC. 13 RTS I Ring Trip Sense. Sense input for the ring trip detector. nect this pin to pin PR through a 500 Ω current-limiting resistor. 15 RRNG I Ring Lead Ringing Supply. Connect this pin to the ringing supply. cuit. Connect to the ring of the loop through overvoltage protection. 19 PT I/O Protected Tip. The output of the tip driver and input to the transmit current sense circuit. Connect to the tip of the loop through overvoltage protection. 21 B5 I Bit 5. B0—B5 determine the state of the SLIC. See Operating States.

Table 1. Pin Descriptions (continued) imize the amount of PWB copper on all leads connected to this device for the lowest operating temperature. 22 B4 I Bit 4. B0—B5 determine the state of the SLIC. See Operating States. 23 B3 I Bit 3. B0—B5 determine the state of the SLIC. See Operating States. 24 B2 I Bit 2. B0—B5 determine the state of the SLIC. See Operating States. 25 B1 I Bit 1. B0—B5 determine the state of the SLIC. See Operating States. 26 B0 I Bit 0. B0—B5 determine the state of the SLIC. See Operating States. 27 VCCD — +5 V Digital dc Supply. +5 V supply for logic and switch circuitry. 28 DGND — Digital Ground. Ground return for VCCD . 29 VBAT — Battery Supply. Negative high-voltage power supply. 30 BGND — Battery Ground. Ground return for the battery (VBAT ) supply. from tip to ring. Connect a resistor from this pin to VITR. ential tip/ring current. A resistor from this pin to ITR sets the gain. 33 TXI I Transmit ac Input. Connect a 0.1 µF capacitor from this pin to VITR. pin TXI. The dc voltage is equal to the dc voltage on pin VRTX. reference for the transmit signal output VTX. ferential voltage on tip and ring. tial voltage on tip and ring. 38 AGND — Analog Ground. Ground return for VCCA . 39 V CCA — +5 V Analog dc Supply. +5 V supply for analog circuitry. 41 IPROG I Current-Limit Program Input. A resistor to DCOUT sets the dc current limit. 0.22 µF, 100 V capacitor from this pin to pin CF1.

allel data interface and chip select lead NCS. Table 2. B0—B3 Input State Coding Table 3. B4—B5 Input State Coding ■ Normal talk and forward battery feed state. ■ All circuits are powered up and active. ■ NDET reflects the status of the switchhook detector. ■ Ground start idle supervision state. receive port) in forward battery. ■ Pin PT is high impedance (>100 kΩ ). ring lead voltage only (see Table 6).

88 Agere Communications Inc. Data Sheet September 2001L7585G Full-Feature, Low-Power SLIC and Switch Operating States (continued) Ground Start/Tip Ground State ■ Ground start busy supervision state. ■ Same as ground start/tip open state but with SW1 closed. Forward Battery Ring Open State ■ Tip lead continuity test state (tone injected at the receive port) in forward battery. ■ Same as forward battery active state, but with SW4 and SW4a open, and the ring drive amplifier powered down. ■ Pin PR is high impedance (>100 kΩ ). ■ Tip current limit is twice the low-current active state current limit. ■ NDET indicates an off-hook when the tip current (flowing out of PT) is twice the value programmed for the switchhook detector in the forward battery active state. Ringing States (2) ■ Normal ringing state. ■ Tip and ring drive amplifiers are powered down. ■ SW1 and SW5 closed; SW2, SW2a, SW3, SW4, SW4a, and SW6 open. ■ NDET reflects the status of the ring trip detector. ■ Bit B3 indicates whether the ringing voltage applied to the ringing bus is either battery backed (B3 = 1) or earth backed (B3 = 0). Although B3 has no direct effect on the state of the SLIC, it can be used by the ring trip detector to enhance ring trip detection. Disconnect State ■ All circuits are powered up and active. ■ SW2, SW2a, SW4, and SW4a closed; SW1, SW3, SW5, and SW6 open. ■ PT and PR are at the same potential to deny current to the loop. Forward Battery Low-Current Active State ■ Normal talk and forward battery feed state. ■ All circuits are powered up and active. ■ Pin PT is positive with respect to pin PR (forward bat- tery). ■ SW2, SW2a, SW4, and SW4a closed; SW1, SW3, SW5, and SW6 open. ■ NDET reflects the status of the switchhook detector. ■ Current limit is lowered to approximately 0.66 times the normal limit. High-Impedance State ■ Disconnect state. ■ Tip and ring drive amplifiers are powered down (all bias currents off). ■ Pins PT and PR are high impedance (>100 kΩ ). ■ SW1, SW2, SW2a, SW3, SW4, SW4a, SW5, and SW6 open. ■ NDET is undefined. Reverse Battery Active State ■ Normal talk and reverse battery feed state. ■ Same as forward battery active state, but PR is posi- tive with respect to PT. Reverse Battery Tip Open State ■ Ring lead continuity test state (tone injected at the receive port) in reverse battery. ■ SW2 and SW2a open and the tip drive amplifier pow- ered down. ■ Pin PT is high impedance (>100 kΩ ). ■ Pin PR is held between –1.7 V and –2.3 V for PR currents less than ±20 mA. PR current limit is the SW4 break switch current limit (250 mA < I < 85 mA). ■ NDET indicates an off-hook when the ring current (flowing out of PR) is twice the value programmed for the switchhook detector in the reverse battery active state.

Agere Communications Inc. 9 Data Sheet September 2001 L7585G Full-Feature, Low-Power SLIC and Switch Operating States (continued) Ground Start/Tip Amplifier State ■ Current limiting is achieved by reducing ring lead voltage only. This state is the same as Ground Start/ Tip Open, but with SW2 and SW2A closed and the tip amplifier powered up. ■ Ring lead current limit is approximately the difference of the high-current active state limit and the current flowing out of the tip lead. ■ On-hook transmission not to exceed –3 dBm with up to 5 mA flowing out of the tip lead (maximum current flow into the tip lead is permissible). Larger signal and/or current may cause distortion. ■ NDET indicates an off-hook when the current flowing out of the tip plus the current flowing into the ring is twice the value programmed for the switchhook detector. Reverse Battery Ring Open State ■ Tip lead continuity test state (tone injected at the receive port) in reverse battery. ■ Same as reverse battery active state, but with SW4 and SW4a open, and the ring drive amplifier powered down. ■ Pin PR is high impedance (>100 kΩ ). ■ Tip current limit is twice the low-current active state current limit. ■ NDET indicates an off-hook when the tip current (flowing into PT) is twice the value programmed for the switchhook detector in the reverse battery active state. Reverse Battery Low-Current Active State ■ Normal talk and reverse battery feed state. ■ Same as forward battery active state, but PR is posi- tive with respect to PT. ■ Current limit is lowered to approximately 0.66 times the normal limit. Absolute Maximum Ratings (TA = 25 °C) Stresses exceeding the values listed under absolute maximum ratings may cause permanent damage to the device. This is an absolute stress rating only. Func- tional operation of the device at these or any other con- ditions in excess of those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum rating conditions for extended peri- ods of time may adversely affect device reliability. Note: Analog voltages are referenced to AGND, digital (logic) volt- ages are referenced to DGND, and battery voltages are ref- erenced to BGND. The IC can be damaged unless all ground connections are applied before and are removed after all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. Some of the known examples of conditions that cause such potentials during powering are the following: 1) an inductor connected to tip and ring that can force an overvoltage on V BAT through external components if the VBAT connection chatters; and 2) inductance in the VBAT lead that could resonate with the VBAT filter capacitor to cause a destructive overvoltage. Parameter Value Unit +5 V dc Supplies (VCCA and VCCD ) –0.5 to +7.0 V +10 V dc Bias Supply (VSP ) –0.5 to +15 V Office Battery Supply (VBAT ) –63 to +0.5 V Logic Input Voltage –0.5 to VDDD + 0.5 V Logic Input Clamp Diode Cur- rent, per Pin ±20 mA Logic Output Voltage –0.5 to VDDD + 0.5 V Logic Output Current, per Pin (excluding relay driver) ±35 mA Operating Temperature Range –40 to +125 °C Storage Temperature Range –40 to +125 °C Relative Humidity Range 5 to 95 %RH Ground Potential Difference (BGND to AGND) ±3 V Ground Potential Difference (DGND to AGND) ±3 V

10 Agere Communications Inc. Data Sheet September 2001L7585G Full-Feature, Low-Power SLIC and Switch

Electrical Characteristics

In general, minimum and maximum values are testing requirements. However, some parameters may not be tested in production because they are guaranteed by design and device characterization. Typical values reflect the design center or nominal value of the parameter; they are for information only and are not a requirement. Minimum and maximum values apply across the entire temperature range (–40 °C to +85 °C) and entire battery range (–35 V to –60 V). Unless otherwise specified, typical is defined as 25 °C, V CCA = +5.0 V, VCCD = +5.0 V, VSP = +10 V, VBAT = –48 V. Positive currents flow into the device. * Not to exceed 26 grams of water per kilogram of dry air. † This parameter is not tested in production; it is guaranteed by design and device characterization. 1. The ringing source may be either of the following: a) The ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. In this case, bit B3 will always be a 1 when ringing is applied. b) The ringing source consists of only the ac voltage (earth-backed ringing); the ringing return is the dc voltage. In this case, bit B3 will always be a 0 when ringing is applied. 2. NDET must also indicate ring trip when the ac ringing voltage is absent (<5 Vrms) from the ringing source. 3. Pretrip ringing must not be tripped by a 10 kΩ resistor in parallel with an 8 µF capacitor applied across tip and ring. Table 4. Operating Conditions and Powering Table 5. Ring Trip Detector

Table 6. Battery Feed Characteristics

  1. The longitudinal current is independent of dc loop current.
  2. Current limit, ILIM, is programmed by a resistor, RPROG , from pin IPROG to pin DCOUT . RPROG = 1.667 x (ILIM – 4); RPROG in kΩ and ILIM

current limit. The ground start ring lead ground current limit is approximately equal to the high current limit and has a slope of about 5 kΩ .

  1. In transmission applications, for compliance with TR-57, ground start ring lead I-V characteristics at high battery, it is expected that the

high-current active current limit will be set to 28 mA.

  1. Loop closure detector current, ILCD , is programmed by a resistor, RLCTH, from pin LCTH to pin DCOUT . RLCTH = 2.5 x ILCD ; RLCTH in
  2. dc feed resistance may be adjusted between 180 Ω and 600 Ω using a resistor divider between DCOUT and DCR. The open loop differen-

tial voltage may also be increased by applying a negative voltage to pin DCR. See dc Gains, pin DCR.

  1. DCOUT gain depends on the resistor RGX1 from pin VITR to pin ITR. This gain assumes 8250 Ω , the recommended value. Positive cur-

rent is defined as the differential current flowing from PT to PR.

  1. Positive voltage on pin DCR has no effect on the PT/PR voltage.
  2. At tip and ring, assuming 82.5 Ω protection resistors.
  3. At tip and ring with matched 82.5 Ω protection resistors when feedback is connected for either 600 Ω or 900 Ω termination impedance.

50 Hz to 1 kHz

200 Hz to 4 kHz

12 Agere Communications Inc. Table 7. Analog Signal Pins

  1. This parameter is not tested in production; it is guaranteed by design and device characterization.
  2. VTX offset is measured with respect to pin VRTX.
  3. Positive voltages from 0 V to V

Transmit direction is tip/ring to VTX. Receive direction is RCVP(N) to tip/ring. Table 8. Transmission Characteristics

  1. Set by external components in conjunction with the T7531A/T7536 codecs. Any complex impedance R1 + R2 || C between 200 Ω and
  2. Return loss and transhybrid loss are functions of device gain accuracies and the external hybrid circuit. Guaranteed performance assumes

1% tolerance external resistors and capacitors.

  1. This parameter is not tested in production; it is guaranteed by design and device characterization.
  2. VTX gain depends on the resistor RGX1 from pin VITR to pin ITR. This gain assumes an ideal 8250 Ω , the recommended value. Positive cur-

rent is defined as the differential current flowing from PT to PR. The transmit signal at VTX is measured with respect to pin VRTX.

200 Hz—500 Hz

500 Hz—3400 Hz

200 Hz—300 Hz

14 Agere Communications Inc. Table 9. Data Interface and Logic (Logic Inputs [CLK, NCS, and B0—B5] and Outputs [NDET])

  1. Unless otherwise specified, all logic voltages are referenced to DGND.
  2. This parameter is not tested in production; it is guaranteed by design and device characterization.

Table 10. Timing Requirements (CLK, B0—B5, and NCS)1, 2

  1. Unless otherwise specified, all times are measured from the 50% point of logic transitions.
  2. These parameters are not tested in production; they are guaranteed by design and device characterization.

Table 11. Relay Driver (RDO)

  1. Unless otherwise specified, all logic voltages are referenced to DGND.
  2. This parameter is not tested in production; it is guaranteed by design and device characterization.

1 Symbol Min Max Unit

Table 12. Ringing Return Access Switch (SW1)

  1. At 25 °C, maximum voltage rating has a temperature coefficient of +0.167 V/°C.
  2. This parameter is not tested in production; it is guaranteed by design and device characterization.
  3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of

induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization. Table 13. Test-In Access Switches (SW3 and SW6)

  1. At 25 °C, maximum voltage rating has a temperature coefficient of +0.167 V/°C.
  2. This parameter is not tested in production; it is guaranteed by design and device characterization.
  3. Test in access switches current limit will be > tip and ring break switches current limit.
  4. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of

induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization.

16 Agere Communications Inc. Table 14. Tip and Ring Break Switches (SW2 and SW4)

  1. At 25 °C, maximum voltage rating has a temperature coefficient of +0.167 V/°C.
  2. This parameter is not tested in production; it is guaranteed by design and device characterization.
  3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of

induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization. Table 15. Tip and Ring Feedback Switches (SW2a and SW4a)

  1. At 25 °C, maximum voltage rating has a temperature coefficient of +0.167 V/°C.
  2. This parameter is not tested in production; it is guaranteed by design and device characterization.
  3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of

induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization.

Table 16. Ringing Access Switch (SW5)

  1. This parameter is not tested in production; it is guaranteed by design and device characterization.
  2. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.
  3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/µs typical with no switch turn-on. In the case of

induced switch turn-off. In this case, no damage will occur for dV/dt up to 2000 V/µs as guaranteed by design and characterization. Figure 3. On-State Switch I-V Characteristics

1818 Agere Communications Inc. Data Sheet September 2001L7585G Full-Feature, Low-Power SLIC and Switch

Applications

The L7585 SLIC has integrated overvoltage tertiary protection diodes in the tip and ring paths. The device also has an integrated thermal shutdown circuit which places tip/ring drivers in a high-impedance state when the die temperature exceeds 160 °C. The SLIC requires the following to survive lightning and power cross requirements: ■ Fusible elements or PTCs ■ Current-limiting resistors ■ A secondary protector Thermal fuse/surge resistor modules that satisfy the various requirements can be purchased from MMC ™ . Protection resistors should have a tolerance of ±1% and a ratio tolerance of ±0.5%. The suppressor break- over voltage of the secondary protector should be set as low as possible. Select a value just above the maxi- mum peak ring signal and maximum battery voltage. NDET Under Fault Condition ■ The state of NDET is not guaranteed with loss of bat- tery. ■ In the ringing state, RRNG floating or with only dc on the ringing source, NDET will produce an off-hook because there are not zero crossings of ringing to cause an on-hook. ■ In the ringing state with only ac (>40 Vrms) on the ringing source, an on-hook will be produced after the second zero crossing of the ringing waveform, because there is no dc component to the ringing cur- rent. ■ In the ringing state, if the resistor between RSW and PR is open, there will likely be a large voltage at the ringing input (due to capacitive loading) and ring trip will be asserted after the second zero crossing of ringing. Because there is no guarantee of the load at PR in this condition, there can be no guarantee of the state on NDET in this condition. ■ If the device enters into thermal shutdown due to a fault that causes an off-hook, the off-hook indication will be stable as the device cycles in and out of ther- mal shutdown. If the fault does not cause an off- hook, NDET will cycle between on- and off-hook as the device cycles in and out of thermal shutdown. Power, Clocking, and Layout The SLIC requires +5 V (VCCA and VCCD ) and a nega- tive battery voltage (VBAT ) to operate. The integrated switches require a 10 V or 12 V supply (VSP ) and a TTL clock (CLK) to operate. CLK requires a frequency between 1.0 MHz to 2.048 MHz with a 50% duty cycle. SW1, SW3, and SW6 will not operate without CLK applied. A four- or six-layer board is recommended. Analog and battery grounds should be laid out as a plane and a layer, and tied together at the device. Digital ground can also be tied to this plane or run separately. V SP is referenced to DGND. VCC can be run as individual traces and can reside on the same layer as signal paths. V CCA and VCCD can be tied together at the SLIC. Placement of the talk battery is not critical. The ring bus should be on a separate layer from the SLIC/codec interface signal leads, and traces should run perpendicular if the traces must cross. TXI, VITR, and ITR are the sensitive nodes on the SLIC. Transmit runners should be run in pairs, and receive runners should be run in pairs between the SLIC and the codec. A channel-to-channel spacing should be main- tained.

Agere Communications Inc. 19 Data Sheet September 2001 L7585G Full-Feature, Low-Power SLIC and Switch Applications (continued) Ring Trip Ring trip is set by the value of RS1. The ring trip threshold at the ring trip inputs is ±2.5 V minimum, ±3.5 V maximum. A resistor value of 500 Ω , as shown in Figure 4, will set the ring trip current threshold to ±6.0 mA typical. Ring trip is asserted upon entering the ringing mode until the second zero crossing of ringing. This is either a positive-going zero crossing (between –40 V and –30 V at –50 V VBAT ) or a negative-going zero crossing (between –10 V and –20 V at –50 V VBAT ). The different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 V. Ring trip will not be asserted unless the ring trip thresh- old is exceeded for two zero crossings. This is either a positive-going zero crossing (between –40 V and –30 V at –50 V V BAT ) or a negative-going zero crossing (between –10 V and –20 V at –50 V VBAT ). The different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 V. Note that since the ringing voltage is monitored at RSW, one zero crossing can occur at switch turn-on depending on initial conditions. Ring trip is asserted immediately if the ring trip input is 15 V ± 3 V. False On-Hook Transients ■ If the L7585G is off-hook in the ground-start/tip open state, the ground-start/tip ground state, or the ground-start/tip amplifier state, due to an applied ring ground, and it is switched to the forward battery active state, it will not generate a false on-hook longer than 10 ms in duration. This applies for loop resistances of 0 Ω to 2000 Ω, providing that all of the following criteria are satisfied: — A loop closure is applied before the L7585G switches to the forward battery active state. — The loop closure resistance (telephone set) is less than 430 Ω . — The ring ground and loop closure are applied at the same end of the loop. — If the ring ground is removed while the L7585G is in the forward battery active state, then the ring ground resistance must be greater than 225 Ω when the dc current limit is 40 mA, or greater than 430 Ω when the dc current is 28 mA.

20 Agere Communications Inc.

  • Optional for quiet reverse battery.

† 4.096 MHz operation; for 2.048 MHz operation, tie SCKSEL to VSS . Figure 4. 16-Channel Line Card Solution

1 MHz

0 VRN0

Agere Communications Inc. 21 Data Sheet September 2001 L7585G Full-Feature, Low-Power SLIC and Switch Outline Diagram 44-Pin MQFP Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Agere Communications Sales Representative. 5-2111 (F) 10.00 ± 0.20 13.20 ± 0.20 10.00 ± 0.20 13.20 ± 0.20 PIN #1 IDENTIFIER ZONE 12 22

0.80 TYP

2.35 MAX 0.10 SEATING PLANE 1.95/2.10DETAIL B

0.25 MAX

0.30/0.45 0.20 M 0.130/0.230 DETAIL B 0.25 0.73/1.03

1.60 REF

September 2001L7585G Full-Feature, Low-Power SLIC and Switch Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2001 Agere Systems Inc. All Rights Reserved September 2001 DS01-313ALC (Replaces DS00-217ALC) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045

Ordering Information

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. MMC is a trademark of Microelectronic Modules Corporation. Device Part No. Description Package Comcode LUCL7585GBE-D Full-Feature, Low-Power SLIC and Switch 44-Pin MQFP (Dry Bag) 108559683 LUCL7585GBE-DT Full-Feature, Low-Power SLIC and Switch 44-Pin MQFP (Tape and Reel, Dry Bag) 108559691