L74VHC1GT50 LRC | Alldatasheet
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Technical content
LESHAN RADIO COMPANY, LTD. The L74VHC1GT50 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power supply. The L74VHC1GT50 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the L74VHC1GT50 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch, battery backup, hot insertion, etc. Noninverting Buffer / CMOS Logic Level Shifter with LSTTL–Compatible Inputs VL d VL d SOT–23/TSOP–5/SC–59 DT SUFFIX SC–70/SC–88A/SOT–353 DF SUFFIX MARKING DIAGRAMS Pin 1 d = Date Code Pin 1 d = Date Code Figure 1. Pinout (Top View) Figure 2. Logic Symbol
2 IN A
3 GND
4 OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. High Speed: t PD = 3.5 ns (Typ) at V CC = 5 V Low Power Dissipation: I CC = 2 mA (Max) at T A = 25°C TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V CMOS–Compatible Outputs: V OH > 0.8 V CC V OL < 0.1 V CC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 104; Equivalent Gates = 26 L74VHC1GT50
Figure 3. Failure Rate vs. Time Junction Temperature
- Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
not implied. Functional operation should be restricted to the Recommended Operating Conditions.
- Tested to EIA/JESD22–A114–A
- Tested to EIA/JESD22–A115–A
LESHAN RADIO COMPANY, LTD. L74VHC1GT50 AC ELECTRICAL CHARACTERISTICS C load = 50 pF, Input t r = t f = 3.0 ns T A = 25°C T A 85°C –55°C<T A <125°C Symbol Parameter Test Conditions Min Typ Max Min Max Min Max Unit t PLH , Maximum V CC = 3.3
0.3 V C
L = 15 pF 4.5 10.0 11.0 13.0 ns t PHL Propagation Delay, C L = 50 pF 6.3 13.5 15.0 17.5 Input A to Y V CC = 5.0
0.5 V C
L = 15 pF 3.5 6.7 7.5 8.5 C L = 50 pF 4.3 7.7 8.5 9.5 C IN Maximum Input 5 10 10 10 pF Capacitance Typical @ 25°C, V CC = 5.0 V C PD Power Dissipation Capacitance (Note 6) 12 pF 6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD V CC f in + I CC C PD is used to determine the no– load dynamic power consumption; P D = C PD V CC 2 f in + I CC V CC DC ELECTRICAL CHARACTERISTICS V CC T A = 25°C T A 85°C –55°C T A 125°C Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit V IH Minimum High–Level V Input Voltage 3.0 1.4 1.4 1.4 4.5 2.0 2.0 2.0 5.5 2.0 2.0 2.0 V IL Maximum Low–Level V Input Voltage 3.0 0.53 0.53 0.53 4.5 0.8 0.8 0.8 5.5 0.8 0.8 0.8 V OH Minimum High–Level V IN = V IH or V IL V Output Voltage I OH V IN = V IH or V IL V IN = V IH or V IL I OH = –4 mA 3.0 2.58 2.48 2.34 I OH = –8 mA 4.5 3.94 3.80 3.66 V OL Maximum Low–Level V IN = V IH or V IL V Output Voltage I OL V IN = V IH or V IL V IN = V IH or V IL I OL = 4 mA 3.0 0.36 0.44 0.52 I OL = 8 mA 4.5 0.36 0.44 0.52 I IN Maximum Input V IN = 5.5 V or GND 0 to5.5 0.1 1.0 1.0 µA Leakage Current I CC Maximum Quiescent V IN = V CC or GND 5.5 2.0 20 40 µA Supply Current I CCT Quiescent Supply Input: V IN Current I OPD Output Leakage V OUT = 5.5 V 0.0 0.5 5.0 10 µA Current
Figure 4. Switching Waveforms Figure 5. Test Circuit
74 VHC1G T50 DF T1 S
3000 Unit
74 VHC1G T50 DF T2 S
74 VHC1G T50 DF T4 S
74 VHC1G T50 DT T1 S
74 VHC1G T50 DT T3 S
LESHAN RADIO COMPANY, LTD. L74VHC1G T50 PACKAGE DIMENSIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. DIM A MIN MAX MIN MAX MILLIMETERS 1.80 2.200.071 0.087 INCHES B 1.15 1.350.045 0.053 C 0.80 1.100.031 0.043 D 0.10 0.300.004 0.012 G 0.65 BSC0.026 BSC J 0.10 0.250.004 0.010 K 0.10 0.300.004 0.012 N 0.20 REF0.008 REF S 2.00 2.200.079 0.087 B 0.2 (0.008) MM 12 3 A G S D 5 PL H C N J K −B− SC70−5/SC−88A/SOT−353 DF SUFFIX SOLDERING FOOTPRINT* mm inches SCALE 20:1 0.65 0.025 0.65 0.025 0.50 0.0197 0.40 0.0157 1.9 0.0748
LESHAN RADIO COMPANY, LTD. L74VHC1G T50 PACKAGE DIMENSIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. A AND B DIMENSIONS DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. DIM MIN MAX MIN MAX INCHESMILLIMETERS A 2.90 3.10 0.1142 0.1220 B 1.30 1.70 0.0512 0.0669 C 0.90 1.10 0.0354 0.0433 D 0.25 0.50 0.0098 0.0197 G 0.85 1.05 0.0335 0.0413 H 0.013 0.100 0.0005 0.0040 J 0.10 0.26 0.0040 0.0102 K 0.20 0.60 0.0079 0.0236 L 1.25 1.55 0.0493 0.0610 M 0 10 0 10 S 2.50 3.00 0.0985 0.1181 0.05 (0.002) 12 3 S A G L B D H C K M J __ _ _ SOT23−5/TSOP−5/SC59−5 DT SUFFIX 0.7 0.028 1.0 0.039 mm inches SCALE 10:1 0.95 0.037 2.4 0.094 1.9 0.074 SOLDERING FOOTPRINT*