KTS6027-2

KTS6027-2 INFINEON | Alldatasheet

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2 Band TV Tuner Mixer-Oscillator-PLL

with unbalanced IF-Amplifier KTS6027-2, KTS6029-2 Version 2.0 Specification July 2001

Edition 03.99 Published by Infineon Technologies AG Balanstraße 73,

81541 München

© Infineon Technologies AG 20.07.01. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits im- plemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. ABM ® , AOP® , ARCOFI® , ARCOFI® -BA, ARCOFI® -SP, DigiTape® , EPIC® -1, EPIC® -S, ELIC® , FALC® 54, FALC® 56, FALC® -E1, FALC® -LH, IDEC® , IOM® , IOM ® -1, IOM® -2, IPAT® -2, ISAC® -P, ISAC® -S, ISAC® -S TE, ISAC® -P TE, ITAC® , IWE® , MUSAC ® -A, OCTAT® -P, QUAT® -S, SICAT® , SICOFI® , SICOFI® - 2, SICOFI® -4, SICOFI® -4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. ACE ™ , ASM™ , ASP™ , POTSWIRE ™ , QuadFALC™ , SCOUT ™ are trademarks of Infineon Technologies AG. Revision History: Current Version: Preliminary Datasheet V 1.1, July 2000 Previous Version:Target Data Sheet Page (in previous Version) Page (in current Version) Subjects (major changes since last revision) all all version to 1.1, status to preliminary 4 - 2 4 - 2 circuit diagram modified 4 - 3 4 - 3 circuit diagram modified 5 - 2 5 - 2 Bus input/output SDA max changed to 6V, Bus input SCL max changed to 6V, ADC input added 5 - 3 5 - 3 new reference for ESD protection 5 - 5 5 - 5 Current consumption for LOW/MID band and HIGH band added, tbf’s replaced by data Charge Pump output voltage VCP = 1.3 V min 5 - 8 5 - 8 Oscillator phsase noise -85 dBc/Hz min, -89 dBc/Hz typ 5 - 9 5 - 9 Oscillator phsase noise -85 dBc/Hz min, -89 dBc/Hz typ Revision History: Current Version: Datasheet, V 2.0, July 2001 Previous Version:Preliminary Datasheet V 1.1, July 2000 Page (in previous Version) Page (in current Version) Subjects (major changes since last revision) all all version to 2.0, preliminary deleted 5 - 2 5- 2 definition of thermal properties changed 5 - 5 5 - 5 current consumtion changed

Product InfoWireless Components Specification, July 2001 Package KTS6027-2, KTS6029-2 Product Info General Description The KTS6027-2/KTS6029-2 is a 5 V mixer/oscillator and synthesizer for analog and digital TV and VCR tuners. Features General I Suitable for analog and digital ter- restrial TV tuner I Compatible with KTS6027-S or KTS6029-S in normal mode I New features in extended mode I Full ESD protection Mixer/Oscillator I High impedance mixer input for LOW/MID band I Low impedance mixer input for HIGH band I 4 pin oscillator for LOW/MID band I 4 pin oscillator for HIGH band IF-Amplifier I single ended IF preamplifier I 75 Ω output impedance PLL I PLL with short lock-in time I High voltage VCO tuning output I Fast I2C bus I 4 NPN bandswitch buffers I Internal LOW-MID/HIGH switch I Lock-in flag I Power-down reset I 4 programmable reference divider ratios: 24, 64, 80, 128 I 4 programmable charge pump cur- rents Application

Ordering Information

Type Ordering Code Package KTS6027-2 Q67037-A1162 ( tape and reel) P-TSSOP-28-1 KTS6029-2 Q67037-A1163 ( tape and reel) P-TSSOP-28-1 I The IC is suitable for NTSC tuners in TV- and VCR-sets or CATV set-top receivers for analog TV and D igital Video B roadcasting.

1 Table of Contents

2 Product Description

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

2.1 General Description

The KTS6027-2, KTS6029-2 device combines a digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV and VCR tuners. The PLL block with four selectable chip addresses forms a digitally programm- able phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 1024 MHz in increments of 31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a micropro- cessor via an I 2C bus. The device has four output ports. A flag is set when the loop is locked. It can be read by the processor via the I2C bus. The mixer-oscillator block includes two balanced mixers (one mixer with high- impedance input and one mixer with a balanced low-impedance input), two fre- quency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an IF amplifier, a low-noise reference voltage source, and a band switch.

2.2 Features

I Suitable for analog and digital terrestrial TV tuner I Compatible with KTS6027-S or KTS6029-S in normal mode I New features in extended mode I Full ESD protection Mixer/Oscillator I High impedance mixer input for LOW/MID band I Low impedance mixer input for HIGH band I 4 pin oscillator for LOW/MID band I 4 pin oscillator for HIGH band IF-Amplifier I single ended IF preamplifier I 75 Ω output impedance PLL I PLL with short lock-in time I High voltage VCO tuning output I Fast I2C bus I 4 NPN bandswitch buffers I Internal LOW-MID/HIGH switch

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 I Lock-in flag I Power-down reset I 4 programmable reference divider ratios: 24, 64, 80, 128 I 4 programmable charge pump currents

2.3 Application

I The IC is suitable for NTSC tuners in TV- and VCR-sets or CATV set-top receivers for analog TV and D igital Video B roadcasting.

2.4 Package Outlines

3 Functional Description

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

3.1 Pin Configuration

KTS6027-2_Pin_config Figure 3-1 KTS6027-2 Pin Configuration KTS6029-2_Pin_config Figure 3-2 KTS6029-2 Pin Configuration VCC MIXOUT SDA HIGHIN HIGHIN LOW/MIDIN MIXOUT PLLGND SCL AS XTAL PFM PMID PLOW OSCHIGHIN OSCHIGHOUT OSCHIGHOUT OSCHIGHIN OSCLOW/MIDIN OSCLOW/MIDOUT RFGND ADC IFOUT PHIGH VT CP KTS6027-2 OSCLOW/MIDOUT OSCLOW/MIDIN KTS6029-2 VCC MIXOUT SDA HIGHIN HIGHIN LOW/MIDIN MIXOUT PLLGND SCL AS XTAL PFM PMID PLOW OSCHIGHIN OSCHIGHOUT OSCHIGHOUT OSCHIGHIN OSCLOW/MIDIN OSCLOW/MIDOUT RFGND ADC IFOUT PHIGH VT CP OSCLOW/MIDOUT OSCLOW/MIDIN

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

3.2 Internal Pin Configuration

Table 3-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID HIGH 1 OSCHIGHIN 0.0 V 1.6 V

2 OSC-

0.0 V 2.8 V

3 OSC-

0.0 V 2.8 V 4 OSCHIGHIN 0.0 V 1.6 V

5 OSCLOW/

1.6 V 0.0 V

6 OSCLOW/

2.3 V 0.0 V

7 OSCLOW/

2.3 V 0.0 V

8 OSCLOW/

1.6 V 0.0 V 9 RFGND analog ground 0.0 V 0.0 V Note: Pin designation refers to KTS6027-2. KTS6029-2 has reversed pinning

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID HIGH

10 ADC VADC VADC

11 IFOUT 2.3 V 2.3 V 12 PHIGH 5.0 V V CE

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID HIGH

13 VT VT VT

14 CP 2.1 V 2.1 V

15 PLOW 5 V or VCE 5 V

16 PMID 5 V or VCE 5 V

17 PFM 5 V or VCE 5 V or VCE

18 XTAL 3.0 V 3.0 V

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID HIGH

19 AS VAS VAS

20 SCL n.a. n.a. 21 SDA n.a. n.a. 22 PLLGND digital ground 0.0 V 0.0 V

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID HIGH 23 MIXOUT 3.8 V 3.8 V 24 MIXOUT 3.8 V 3.8 V 25 VCC supply voltage 5.0 V 5.0 V 26 LOW/MIDIN 1.8 V 0.0 V 27 HIGHIN 0.0 V 0.9 V 28 HIGHIN 0.0 V 0.9 V Oscillator IF Amp. 2423 27 28

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

3.3 Block Diagram

KTS602729_block_diag Note: Pin designations in parenthesis refer to KTS6029-2 Figure 3-3 Block Diagram OSCHIGHOUT OSCHIGHIN OSCHIGHOUT RF Input HIGH RF Input LOW/MID Mixer HIGH Mixer LOW/MID Oscillator HIGH Oscillator LOW/MID SAW Driver Prog. Divider Phase/ Frequency Comparator Crystal Oscillator Reference Divider PortsI2C Bus OSCLOW /MIDIN OSCHIGHIN OSCLOW /MIDOUT RFGND ADC PHIGH IFOUT VT CP HIGHIN HIGHIN LOW /MIDIN VCC M IXOUT M IXOUT PLLGND SDA SCL AS XTAL PFM PMID PLOW fdiv FL OSCLOW /MIDOUT OSCLOW /MIDIN Lock Detector fref VCC LOW or MID LOW or MID HIGH HIGH HIGH ADC CP, CM, OS Charge Pump LOW or MID 123456789 1 0 1 1 1 2 1 3 1 4 28 27 26 25 24 23 22 21 20 19 18 17 16 15

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

3.4 Circuit Description

3.4.1 General

In the normal mode (see Table 5-7 Test modes on page 32 ) the IC is compatible with KTS6027-S / KTS6029-S. An extended mode makes a reference divider ratio of 24 (see Table 5-8 Reference divider ratio on page 32 ) and two additional charge pump currents (see Table 5-9 Charge pump current on page 33 ) available.

3.4.2 Mixer-Oscillator block

The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for LOW and / or MID band and HIGH band, an IF amplifier, a reference voltage source and a band switch. Filters between tuner input and IC separate the TV frequency signals into two bands. The band switching in the tuner front-end is done by using two or three port outputs. In the selected band the signal passes a tuner input stage with MOSFET amplifier, a double-tuned bandpass filter and is then fed to the bal- anced mixer input of the IC which has in case of LOW / MID a high-impedance input and in case of HIGH a low-impedance input. The input signal is mixed there with the signal from the activated on chip oscillator to the IF frequency which is filtered out at the balanced high-impedance output pair by means of a parallel tuned circuit. The following SAW preamplifier has a low output imped- ance to drive the SAW filter directly.

3.4.3 PLL block

The oscillator signal is internally DC-coupled as a differential signal to the pro- grammable divider inputs. The signal subsequently passes through a program- mable divider with ratio N = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency f ref = 31.25, 50, 62.5 or 166.7 kHz. This frequency is derived from an unbalanced, low-impedance 4 MHz crystal oscillator (pin XTAL) divided by R = 128, 80, 64 or 24. The phase detector has two outputs that drive two current sources of opposite polarity as charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the positive current source pulses for the duration of the phase difference. In the reverse case the negative current source pulses. If the two signals are in phase, the charge pump output (CP) goes into the high-impedance state (PLL is locked). An active low-pass fil- ter integrates the current pulses to generate the tuning voltage for the VCO

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 (internal amplifier, external pull-up resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state if the control bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuitry. TUNE may be switched off by the con- trol bit OS to allow external adjustments. If the VCO is not oscillating the PLL locks to a tuning voltage of 33 V . By means of the control bits CP, CM, T0 and T1 the pump current can be switched between four values by software. This programmability permits alter- ation of the control response time of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example. The software-switched ports PLOW, PMID, PHIGH and PFM are general-pur- pose open-collector outputs. The test bits T0 = 0 and T1 = 1 switches the test signals f ref (i.e.fXTAL / 64) and fdiv (divided input signal) to PLOW and PMID respectively. The lock detector resets the lock flag FL if the width of the charge pump current pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL = 1, the maximum deviation of the input frequency from the programmed fre- quency is given by ∆f = ± I P (KVCO / fXTAL ) (C1+C2) / (C1C2) where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscil- lator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-1 KTS6027-2 Evaluation Board on page 20). As the charge pump pulses at i.e. 62.5 kHz (= fref), it takes a maximum of 16 µs for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 µs for FL to be set after the loop regains lock.

3.4.4 I2C-Bus Interface

Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I 2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table ”Bit Allocation” ( see Table 5-4 Bit Allocation Read / Write on page 31 ) should be referred to the following description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowl- edge and then shifts out the status byte onto the SDA line. If the processor gen- erates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists the lock flag and the power-on flag. Four different chip addresses can be set by appropriate DC level at pin AS ( see Table 5-6 Address selection on page 32 ). While applying the supply voltage, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and when V CC falls below 3.2 V. It will be reset at the end of a READ operation.

4 Applications

Applications

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

4.1 KTS6027-2 Evaluation Board

Figure 4-1 KTS6027-2 Evaluation Board 1p2 1p2 1p2 1p2 2p7 2p2 2p2 2p7 56033k L1 L2 L3 120p BB659C BA892 3k3 100k47p BB659C 2k72k7 1k81k8 1:1*) 2p2 22p 22p 68p 68p 47n 220 220 4n7100p 18p 4n7 4n7 4n74n7 100p 4n7 4n7 18p + 33 V 22k

4 MHz

RGen = 75 Ω LOW/ MID VCC 10n RLoad = 75 Ω IFoutput 100n 220 RGen = 75 Ω 123456789 1 0 1 1 1 2 1 3 1 4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 KTS6027-2 4n7 PHIGH C1 2n2 47n 220 Table 4-1 Recommended band limits in MHz RF input Oscillator min max min max LOW 55.25 127.25 101 173 MID 133.25 361.25 179 407 HIGH 367.25 803.25 413 849 Table 4-1 Coils turns /c69 wire /c69 L1 1.5 2 mm 0.4 mm L2 3.5 2.5 mm 0.5 mm L3 9.5 2.5 mm 0.4 mm L4 12.5 3.5 mm 0.3 mm *) TOKO B4F Type 617DB-1023

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

4.2 KTS6029-2 Evaluation Board

Figure 4-2 KTS6029-2 Evaluation Board 1p2 1p2 1p2 1p2 2p7 2p2 2p2 2p7 C1 47n 2n2 56033k L1 L2 L3 120p BB659C BA892 3k3 100k47p BB659C 2k72k7 1k81k8 1:1*) 2p2 22p 22p 68p 68p 47n 220 220 4n7100p 18p 4n7 4n7 4n74n7 100p 4n7 4n7 18p + 33 V 22k RGen = 75 Ω LOW/ MID VCC 10n RLoad = 75 Ω IFoutput 100n 220 RGen = 75 Ω KTS6029-2 4n7 PHIGH 123456789 1 0 1 1 1 2 1 3 1 4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 220 Table 4-1 Recommended band limits in MHz RF input Oscillator min max min max LOW 55.25 127.25 101 173 MID 133.25 361.25 179 407 HIGH 367.25 803.25 413 849 Table 4-1 Coils turns /c69 wire /c69 L1 1.5 2 mm 0.4 mm L2 3.5 2.5 mm 0.5 mm L3 9.5 2.5 mm 0.4 mm L4 12.5 3.5 mm 0.3 mm *) TOKO B4F Type 617DB-1023

5 Reference

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.1 Electrical Data

5.1.1 Absolute Maximum Ratings

The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC may result. Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB = - 20°C ...TAmax Parameter 1). Symbol Limit Values Unit Remarks min max Supply voltage VCC -0.3 6 V Ambient temperature TA -10 TAmax 2). Junction temperature TJ +125 °C Storage temperature TStg -40 +125 °C Temperature difference junction to case 3). TJC 2 K PLL CP VCHGPMP -0.3 3 V ICHGPMP 1 mA Crystal oscillator pin XTAL VXTAL VCC V IXTAL -5 mA Bus input/output SDA VSDA -0.3 6 V Bus output current SDA ISDA(L) 5 mA open collector Bus input SCL VSCL -0.3 6 V Chip address switch AS VAS -0.3 VCC V VCO tuning output (loop filter) VT -0.3 35 V ADC inpur VADC -0.3 VCC V Port outputs PLOW, PMID, PHIGH, PFM VP -0.3 VCC V IP(L) -1 25 mA t max = 0.1 sec. at 5.5 V Total port output current ΣIP(L) 40 mA t max = 0.1 sec. at 5.5 V

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB = - 20°C ... + 85°C (continued) Parameter 1) Symbol Limit Values Unit Remarks min max Mixer-Oscillator Mix input LOW/MID Vi -0.3 3 V Mix inputs HIGH Vi 2 V Ii -5 6 mA VCO base voltage VB -0.3 3 V VCO collector voltage VC VCC V ESD-Protection 4). all pins VESD 2 kV 1). All values are referred to ground (pin), unless stated otherwise. Currents with a positive sign flow into the pin and currents with a negative sign flow out of pin. 2).The maximum ambient temperature depends on the mounting conditions of the package. Any application mounting must guarantee not to exceed the maximum junction temperature of 125 °C. As reference the tem- perature difference junction to case is given. 3).Referred to top center of package 4). According to EIA/JESD22-A114-B (HBM incircuit test), as a single device incircuit contact discharge test.

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.1.2 Operating Range

Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed. Table 5-2 Operating Range Parameter Symbol Limit Values Unit Test Conditions L Item min max Supply voltage VCC +4.5 +5.5 V Programmable divider factor N 256 32767 LOW/MID Mixer input frequency range fi 40 500 MHz HIGH Mixer input frequency range fi 350 900 MHz LOW/MID Oscillator frequency range fO 75 560 MHz HIGH Oscillator frequency rangefO 380 950 MHz Ambient temperature TAMB -20 TAmax 1). 1).see 5.1.1 Absolute Maximum Ratings on page 23

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.1.3 AC/DC Characteristics

AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC Symbol Limit Values Unit Test Conditions LI t e m min typ max Supply Supply voltage VCC 4.5 55 . 5 V Current consumption ICC 48 61 74 mA LOW/MID band 51 65 79 mA HIGH band Digital Unit PLL Crystal oscillator connections XTAL Crystal frequency fXTAL 3.2 4.0 4.8 MHz series resonance Crystal resistance R XTAL 10 100 Ω series resonance Oscillation frequencyfXTAL 3,99975 4,000 4,00025 MHz f XTAL = 4 MHz Input impedance ZXTAL -700 -900 -1100 Ω fXTAL = 4 MHz Charge pump output CP Output current, see Table 5-9 Charge pump current on page 33 ICPDH ± 430 ± 650 ± 860 µA VCP = 1.8 V ICPH ± 180 ± 250 ± 360 µA VCP = 1.8 V ICPDL ± 90 ± 125 ± 180 µA VCP = 1.8 V ICPL ± 35 ± 50 ± 70 µA VCP = 1.8 V Tristate current ICPZ ± 1 nA T0=1, T1=0 Output voltage VCP 1.3 2.5 VP L L l o c k e d Drive output VT (open collector) HIGH output current ITH 10 µA V TH = 33 V, T0 = 1, T1 = 0 LOW output voltage VTL 0.5 VI TL = 1.0 mA I2C-Bus Bus inputs SCL, SDA HIGH input voltage VIH 3 5.5 V LOW input voltage VIL 0 1.5 V HIGH input current IIH 10 µA V IH = VCC LOW input current IIL -10 µA V IL = 0 V

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC (continued) Symbol Limit Values Unit Test Conditions LI t e m min typ max Bus output SDA (open collector) HIGH output current IOH 10 µA V OH = 5.5 V LOW output voltage VOL 0.4 VI OL = 3 mA Edge speed SCL,SDA Rise time tr 300 ns Fall time tf 300 ns Clock timing SCL Frequency fSCL 0 400 kHz HIGH pulse width tH 0.6 µs LOW pulse width tL 1.3 µs Start condition Set-up time tsusta 0.6 µs Hold time thsta 0.6 µs Stop condition Set up time tsusto 0.6 µs Bus free tbuf 1.3 µs Data transfer Set-up time tsudat 0.1 µs Hold time thdat 0 µs Input hysteresis SCL, SDA Vhys 200 mV Pulse width of spikes which are suppressed tsp 0 50 ns Capacitive load for each bus line C L 400 pF Port outputs PLOW, PMID, PHIGH, PFM (open collector) HIGH output current IPOH 1 µA V POH = 5 V LOW output voltage VPOL 0.5 VI POL = 25 mA ADC port input HIGH input current IADCH 10 µA LOW input current IADCL -10 µA Address selection input AS HIGH input current IASH 50 µA V ASH = 5 V LOW input current IASL -50 µA V ASL = 0 V

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC (continued) Symbol Limit Values Unit Test Conditions LI t e m min typ max Analog Unit LOW/MID Band Section (including IF amplifier) Voltage gain G V 15 18 21 dB f RF = 55.25 to 361.25 MHz, fIF = 41,25 to

58.75 MHz

Mixer noise figure NF 91 1 dB f RF = 55.25 to 361.25 MHz Output voltage causing 0.8 % of crossmodulation in channel, see 5.4.6 on page 38 Vo 109 dBµV f RFw = 55.25 MHz Vo 109 dBµV f RFw = 361.25 MHz Input IP2 IP2 140 dBµV f RF1 = 55.25 MHz fRF2 = 111.00 MHz, PRF1 = PRF2 IP2 135 dBµV f RF1 = 361.25 MHz fRF2 = 723.00 MHz, PRF1 = PRF2 Input IP3 IP3 110 dBµV f RF1 = 55.25 MHz fRF2 = 60.75 MHz, fRF2 = 61.75 MHz, PRF1 = PRF2 = PRF3 IP3 110 dBµV f RF1 = 253.25 MHz fRF2 = 258.75 MHz, fRF2 = 259.75 MHz, PRF1 = PRF2 = PRF3 Output voltage caus- ing 1 dB compression Vo 115 dBµV f RF = 55.25 MHz Vo 115 dBµV f RF = 361.25 MHz Mixer input impedance R i 0.5 11 . 5 kΩ parallel equivalent circuit, fRF = 100 MHz C i 23 pF parallel equivalent circuit, fRF = 100 MHz Oscillator frequency shift, PLL unlocked ∆fOsc(V) 400 kHz V CC = 5 V ± 10 % Oscillator frequency drift, PLL unlocked ∆fOsc(T) 500 kHz ∆T = 25 °C Oscillator frequency drift, PLL unlocked ∆fOsc(t) 100 kHz t = 5 s up to 15 min after switching on

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC (continued) Symbol Limit Values Unit Test Conditions LI t e m min typ max Oscillator pulling, PLL unlocked Vi 100 108 dBµV ∆f = 10 kHz fRF = 55.25 MHz Vi 100 108 dBµV ∆f = 10 kHz fRF = 361.25 MHz Oscillator phase noise 1). Φ OSC -86 -89 dBc/Hz fm = 10kHz IF suppression aIF 15 20 dB V i = 80 dBµV HIGH Band Section (including IF amplifier) Voltage gain G V 26 29 32 dB f RF = 367.25 MHz to

801.25 MHz,

fIF = 41,25 to Mixer noise figure NF 69 dB f RF = 367.25 to

613.25 MHz

71 0 dB f RF = 619.25 to

801.25 MHz

causing 0.8 % of crossmodulation in channel, see 5.4.7 on page 39 Vo 109 dBµV f RFw = 403.25 MHz Vo 109 dBµV f RFw = 775.25 MHz Input IP2 IP2 130 dBµV f RF1 = 373.25 MHz fRF2 = 747.00 MHz, PRF1 = PRF2 Input IP3 IP3 99 dBµV f RF1 = 503.25 MHz fRF2 = 510.25 MHz, fRF2 = 512.25 MHz, PRF1 = PRF2 = PRF3 IP3 99 dBµV f RF1 = 775.25 MHz fRF2 = 780.75 MHz, fRF2 = 781.75 MHz, PRF1 = PRF2 = PRF3 Output voltage caus- ing 1 dB compression Vo 115 dBµV f RF = 503.25 MHz Vo 115 dBµV f RF = 799.25 MHz Mixer input impedance R i 14 20 26 Ω serial equivalent cir- cuit, fRF = 600 MHz Li 6 10 14 nH serial equivalent cir- cuit, fRF = 600 MHz Oscillator frequency shift, PLL unlocked ∆fOsc(V) 400 kHz V CC = 5 V ± 10 % Oscillator frequency drift, PLL unlocked ∆fOsc(T) 800 kHz ∆T = 25 °C

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC (continued) Symbol Limit Values Unit Test Conditions LI t e m min typ max Oscillator frequency drift, PLL unlocked ∆fOsc(t) 100 kHz t = 5 s up to 15 min after switching on Oscillator pulling, PLL unlocked Vi 100 108 dBµV ∆f = 10 kHz fRF = 367.25 MHz 100 108 dBµV ∆f = 10 kHz fRF = 801.25 MHz Oscillator phase noise 1) -86 -89 dBc/Hz fm = 10kHz IF suppression aIF 15 20 dB V i = 80 dBµV SAW preamplifier IF output impedance R IF 80 Ω serial equivalent circuit, f IF = 45.75 MHzLIF 7 nH Rejection at the IF outputs Divider interference rejection 2). Vo 30 dBµV Channel CH6 beat 3). INTCH6 70 dBc V RFpix = 80 dBµV VRFsnd = 80 dBµV Channel A-5 beat rejection 4). INTCHA5 70 dBc V RFpix = 80 dBµV I This value is only guaranteed in lab. 1). Measured in the evaluation board. (see Chapter 4) 2). This is the level of divider interferences close to the IF frequency. For example channel S3: fOSC = 158.15 MHz, 1/4 fOSC = 39.5375 MHz. Measured in the evaluation board. (see Chapter 4) 3). Channel 6 beat is the interfering product of fRFpix + fRFsnd - fOSC of channel 6 at 42 MHz. Measured in the evaluation board. (see Chapter 4) 4). Channel A-5 beat is the interfering product of fRFPIX + fRFSND - fOSC of channel A-5, fbeat = 45.5 MHz. The possible mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC . Measured in the evaluation board. (see Chapter 4)

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.2 Programming

Table 5-4 Bit Allocation Read / Write Byte MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB Ack Write Data Address Byte 11 00 0M A 1 MA0 0 A Progr. Divider Byte 1 0N 1 4 N13 N12 N11 N10 N9 N8 A Progr. Divider Byte 2 N7 N6 N5 N4 N3 N2 N1 N0 A Control Byte 1C P T1 T0 CM RSA RSB OS A Bandswitch Byte 1). xx xx P3 P2 P1 P0 A Read Data Address Byte 11 00 0M A 1 MA0 1 A Status Byte POR FL xx xA 2 A1 A0 A 1).see Table 5-10 Bandswitching on page 33 Table 5-5 Description of symbols Symbol Description MA0, MA1 Address selection bits (see Table 5-6 Address selection on page 32 ) N14 to N0 programmable divider bits: CP charge pump current: bit = 0: charge pump current = 50 µA bit = 1: charge pump current = 250µA T1, T0 test bits (see Table 5-7 Test modes on page 32 ) CM charge pump mode bit (see Table 5-9 Charge pump current on page 33 ) RSA, RSB reference divider bits (see Table 5-8 Reference divider ratio on page 32 ) OS tuning amplifier control bit: bit = 0: enable VT bit = 1: disable VT PLOW, PMID, PHIGH, PFM, see 5-10 on page 33 NPN ports control bits: bit = 0: NPN open-collector output is inactive bit = 1: NPN open-collector output is active A0, A1, A2 ADC bits (see Table 5-11 A/D converter levels on page 34 ) FL PLL lock flag bit = 1: loop is locked POR Power-on reset flag flag is set at power-on and reset at the end of READ operation x don‘t care

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 5-6 Address selection Voltage at AS MA1 MA0 (0...0.1) * VCC 00 (0.9...1) * VCC 11 Table 5-7 Test modes Test mode Mode T1 T0 Normal operation normal 1). 0 0 Charge pump output, CP is in high-impedance state 0 1 PMID = fdiv output, PLOW = fref output 1 0 Extended operation extended 1 1 1). In this mode the IC is compatible with KTS6027-S / KTS6029-S Table 5-8 Reference divider ratio Reference divider ratio Mode 1). T1 T0 RSA RSB fref 2). normal 0 0 x 0 50 kHz0 1 1 0 128 0 0 0 1 31.25 kHz0 1 1 0 0 0 1 1 62.5 kHz0 1 1 0 extended 1 1 0 0 50 kHz 128 0 1 31.25 kHz 24 1 0 166.7 kHz 64 1 1 62.5 kHz 1).see Table 5-7 Test modes on page 32 2). With a 4 MHz quartz.

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 5-9 Charge pump current Charge pump current Mode 1). CP T1 T0 CM 50 µA normal x 250 µA 1 x 50 µA extended 125 µA 0 1 250 µA 1 0 600 µA 1 1 1).see Table 5-7 Test modes on page 32 Table 5-10 Bandswitching Bit Designation P3 P2 P1 P0 Active Port Pin PHIGH 1). 12 0 00 0 PLOW 15 0 00 1 PMID 16 0 01 0 not used 0 01 1 PHIGH 12 0 10 0 PLOW, PFM 15, 17 0 10 1 PMID, PFM 16, 17 0 11 0 not used 0 11 1 PHIGH 12 1 00 0 PLOW, PFM 15, 17 1 00 1 PMID, PFM 16, 17 1 01 0 not used 1 01 1 PHIGH, PFM 12, 17 1 10 0 PLOW, PFM 15, 17 1 10 1 PMID, PFM 16, 17 1 11 0 not used 1 11 1 1). Default after power-on

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001 Table 5-11 A/D converter levels Voltage at ADC A2 A1 A0 (0.6...1)*VCC 10 0

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.3 I2C Bus Timing Diagram

Telegram examples: Start-ADB-DB1-DB2-CB-BB-Stop Start-ADB-CB-BB-DB1-DB2-Stop Start-ADB-DB1-DB2-Stop Start-ADB-CB-BB-Stop Abbreviations: Start= start condition ADB= address byte DB1= prog. divider byte 1 DB2= prog. divider byte 2 CB= Control byte BB= Bandswitch byte Stop= stop condition MA1 R/WMA0 1 1 Start Stop 0 0 0

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.4 Test Circuits

5.4.1 Gain (GV) test Set-up in LOW/MID

I Zi >> 50 Ω => Vi = 2 x Vmeas = 80 dBµV I Vi = Vmeas + 6dB = 80 dBµV I G v = 20 log(V0 / Vi)

5.4.2 Gain (GV) test Set-up in HIGH

I Vi = Vmeas = 70 dBµV I G v = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun) Device under Test IFOUTLOW/ MIDIN Vi 50 Ω 50 ΩV Vmeas RMS Votmeter 50 Ω spectrum analyser Vo Device under Test IFOUTHIGHIN Vi 50 Ω 50 ΩV Vmeas RMS Votmeter Balun 1:1 HIGHIN 50 Ω spectrum analyserVo

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.4.3 Matching circuit for optimum noise figure in LOW/MID

5.4.4 Noise Figure Test Set-up in LOW/MID

wire /c9066 0.5 mm coil /c9066 5.5 mm In Out 15p 22p 50 τ semi rigid cable 300 mm long 96 pF/m 33dB/100m In Out For fRF = 150 MHz I loss = 1.3 dB I image suppression = 13 dB For fRF = 50 MHz I loss = 0 dB I image suppression = 16 dB Device under Test IFOUTLOW/ MIDIN Noise Source NF = NFmeas - loss of matching circuit (dB) Matching Circuit IN OUT Noise Figure Meter

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.4.5 Noise Figure Test Set-up in HIGH

5.4.6 Cross modulation Test Set-up in LOW/MID band

I Zi >> 50 Ω => Vi = 2 x Vmeas I wanted output signal at fpix, Vo = 100 dBµV I unwanted output signal at fsnd , 80 % AM modulated with 1 kHz Device under Test IFOUTHIGHIN HIGHIN Balun 1:1 Noise Source loss of balun = 1 dB NF = NFmeas - loss of balun (dB) Noise Figure Meter Hybrid A B C D Device under Test IFOUTLOW/ MIDIN Vi 50 Ω 50 Ω 50 Ω unwanted signal source AM = 80 % wanted signal source 50 ΩVVmeas RMS Votmeter Vo

45.75 MHz

50 Ω modulation analyser 18 dB attenuator

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.4.7 Cross modulation Test Set-up in HIGH band

I wanted output signal at fpix, Vo = 100 dBµV I unwanted output signal at fsnd , 80 % AM modulated with 1 kHz

5.4.8 Measurement of fref and fdiv

MEAS_COF Hybrid A B C D Device under Test IFOUTHIGHIN HIGHIN Balun 1:1Vi 50 Ω 50 Ω 50 Ω unwanted signal source AM = 80 % wanted signal source 50 ΩVVmeas RMS Votmeter Vo 50 Ω modulation analyser 18 dB attenuator 5k 5k 18p Device under Test VVCC Counter Counter + 5 V Test Mode: T1 = 1, T0 = 0 fQ = fref * R R: reference divider ratio fVCO = fdiv * N N: divider ratio fref fdiv

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.5 Electrical Diagrams

5.5.1 Input admittance (S11) of the LOW/MID band mixer input

Y0 = 20mS Y_VHFMIX

5.5.2 Input impedance (S11) of the HIGH band mixer input

Z0 = 50 Ω (symmetrical) Zn_UHFMIX 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.5 20 0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 0.9 1 1 1.5 1.5

48.25 MHz

407.25 MHz

415.25 MHz

855.25 MHz

KTS6027-2, KTS6029-2 Wireless Components Specification, July 2001

5.5.3 Output admittance (S22) of the Mixer output

Y0 = 20mS Y_MIXOUT

5.5.4 Output impedance (S22) of the IF output

Z0 = 50 Ω UIFOUT 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.5 20 0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 0.9 1 1 1.5 1.5 Rdiff 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.5 200 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 0.9 1 1 1.5 1.5