KTD2026

KTD2026 KINETIC | Alldatasheet

Document overview

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• PDF pages: 21

Technical content

Features

• Ultra low dropout regulated current sinks  3-Channels: KTD2026  4-Channels: KTD2027
• 40mV typical at 10mA per channel Programmable LED setting using I2C control
• Individual channel control  On/Off Interval Time Control  Dimming Up/Down Time  Current Level Setting  RGB or RGBW LED Color Control
• 192 current levels: 24mA max, 0.125mA step
• ±5% current matching for max current
• Low supply current of 200μA typ.
• No noise, non-pulsating LED current
• Fast, smooth start-up
• VIN Range: 2.7V to 5.5V
• 0.1μA Shutdown Current
• Pb-free Package: UTDFN-8 1.5x1.5mm
• RoHS and Green Compliant
• -40°C to +85°C Temperature Range

Applications

• RGB indicator LEDs
• Flashing LEDs
• Mobile Phones
• Handheld Devices
• Digital Cameras Brief Description The KTD2026/7 are fully programmable, constant current RGB or RGBW LED drivers with a flexible control interface. The devices are ideally powered from one-cell lithium - ion/polymer, 3 -cell NiCd/NiMH/Alkaline batteries, or systems with 3.3V or 5V supplies. The independent programmable constant current sinks operate without external components. With an on-chip timing control unit, LED blink rate, fade-in and fade-out are user-adjustable resulting in unique color lighting patterns. Ten internal registers are programmed via the I2C interface with a built-in decoder allowing individual control of the three/four LED channels’ On/Off state and current level. A total of 192 current levels are available for each channel from 0.125mA to 24mA with a 0.125mA step. In shutdown mode, the quiescent current is reduced to less than 1μA. The driver is available in a low profile 8-pin 1.5mm x 1.5mm x 0.5mm Ultra-Thin DFN package. The packages are Pb- free, RoHS and Green compliant. Typical Application SDA SCLI2C Control SCL GND VIN VIN 2.7V to 5.5V 1.0uF KTD2026 STStatus Output I2C Control SDA GND VIN SDA VIN 2.7V to 5.5V 1.0µF SCL D3 D4 KTD2027 GND VIN CTRL VIN 2.7V to 5.5V 1.0µF EN KTD2022Enable ExpressWire Control I2C Control STStatus Output Constant Current RGB/White LED Driver with I2C Control

t KTD2026/KTD2027 April 2020 – Revision 04h Page 2 Company Confidential Pin Descriptions UTDFN 1.5x1.5, 8-pin Package Pin # Name Function KTD2026 KTD2027 1 -- ST Status open-drain logic output stays low (on state) during first half of the flash period (50% duty cycle) then goes to high-impedance (off) during second half of the flash period. An optional pull-up resistor can be connected from this pin to the supply. -- 1 D4 Regulated output current sink D4. Current level and ON/OFF selections are controlled by serial interface. 2 2 D3 Regulated output current sink D3. Current level and ON/OFF selections are controlled by serial interface. 3 3 D2 Regulated output current sink D2. Current level and ON/OFF selections are controlled by serial interface. 4 4 D1 Regulated output current sink D1. Current level and ON/OFF selections are controlled by serial interface. 5 5 VIN Input power for the IC. 6 6 SCL Clock of the I²C interface. 7 7 SDA Data of the I²C interface. 8 8 GND Ground pin. KTD2026 KTD2027 (Top View) (Top View) ST GND SDA SCL VIN KTD2026 GND SDA SCL VIN KTD2027

t KTD2026/KTD2027 April 2020 – Revision 04h Page 3 Company Confidential Absolute Maximum Ratings1 (TA = 25C unless otherwise noted) Symbol Description Value Units VIN, D2, D3, D4, ST Input voltage, Output pins -0.3 to 6.0 V SCL, SDA, D1 Control Interface pins and D1 sink pin -0.3 to VIN+0.3 V TJ Operating Temperature Range -40 to 150 C Ts Storage Temperature Range -65 to 150 C TLEAD Maximum Soldering Temperature (at leads, 10 sec) 300 C ESD HBM electrical static discharge 2.0 kV Thermal Capabilities Symbol Description Value Units UTDFN1.5x1.5-8 θJA Thermal Resistance – Junction to Ambient2 190 C/W PD Maximum Power Dissipation at TA ≤ 25C 0.526 W ΔPD/C Derating Factor Above TA = 25C -5.26 mW/C

Ordering Information

Address Marking3 Operating Temperature Package KTD2026EWE-TR 24mA 30h ETYYZ -40°C to +85°C UTDFN1.5x1.5-8 KTD2026BEWE-TR 24mA 31h GKYYZ -40°C to +85°C UTDFN1.5x1.5-8 KTD2026CEWE-TR 24mA 32h LYYYZ -40°C to +85°C UTDFN1.5x1.5-8 KTD2027EWE-TR 24mA 30h ESYYZ -40°C to +85°C UTDFN1.5x1.5-8 KTD2027BEWE-TR 24mA 31h LZYYZ -40°C to +85°C UTDFN1.5x1.5-8 1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time. 2. Junction to Ambient thermal resistance is highly dependent on PCB layout. Values are based on thermal properties of the device when soldered to an EV board. 3. “YYZ” is the date code and assembly code.

t KTD2026/KTD2027 April 2020 – Revision 04h Page 4 Company Confidential Electrical Characteristics4 Unless otherwise noted , t he Min and Max specs are applied over the full operation temp erature range of –40°C to +85°C, while Typ values are specified at room temperature (25C). VIN = 3.6V. Symbol Description Conditions Min Typ Max Units Power Supply VIN Input operating range 2.7 5.5 V VD_MIN Dx pin dropout voltage (90% of nominal current) All Channels set to 20mA 75 120 mV ISINK Output current accuracy All Channels set to 20mA -5.0 +5.0 % All channels set 0.125mA -5.0 +5.0 % Output current matching |ID - Iavg| max / Iavg All Channels set to 20mA -5.0 5.0 % IIN IC supply Current All 4 Channels set to 20mA 330 650 A All 3 Channels set to 20mA 300 A

1 Channel set to 20mA

Other channels OFF 260 A IQ IC quiescent Current Device on, All LEDs OFF, Reg4 = 0 190 A ISHDN Shutdown current VIN = VOUT = 5.5V5 0.1 1.0 A Control Pin Voltage Specifications (SCL, SDA) VIL Input Logic Low Threshold SDA, SCL 0.4 V VIH Input Logic High Threshold SDA, SCL 1.2 V I2C-Compatible Timing Specifications (SCL, SDA), see Figure 1 t1 SCL (Clock Period) 2.5 s t2 Data In Setup Time to SCL High 100 ns t3 Data Out Stable After SCL Low 0 ns t4 SDA Low Setup Time to SCL Low (Start) 100 ns t5 Setup time for STOP condition 600 ns tSHDN Shutdown Delay 600 s Thermal Shutdown TJ-TH IC junction thermal shutdown threshold 140 C IC junction thermal shutdown hysteresis 15 C 4. KTD2026/7 are guaranteed to meet performance specifications over the –40°C to +85°C operating temperature range by design, characterization and correlation with statistical process controls. 5. Depending on the Enable Control register Reg0[4-3] and the state of SCL and SDA inputs, the KTD202x enters shutdown mode.

Figure 1. I2C Compatible Interface Timing

t KTD2026/KTD2027 April 2020 – Revision 04h Page 6 Company Confidential Typical Characteristics VIN = 3.6V, C1 = 1F, KTD2026, TAMB = 25ºC unless otherwise specified. Quiescent Current with LEDs off Quiescent Current with LEDs on LED Current Regulation (at 20mA) Dropout Voltage LED Current Matching (2mA per channel) Input Logic Threshold Voltage 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Quiescent Current (mA) Input Voltage (V) 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Quiescent Current (mA) Input Voltage (V) LED Current Variation (%) Input Voltage (V) 0 20 40 60 80 100 120 140 160 180 200 LED Current (mA) Dx pin Voltage (mV) 20mA 10mA 5mA LED Current Variation (%) VIN (V) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Logic Threshold (V) Input Voltage (V) VIH VIL

t KTD2026/KTD2027 April 2020 – Revision 04h Page 7 Company Confidential Typical Characteristics VIN = 3.6V, C1 = 1F, TAMB = 25ºC unless otherwise specified. Linear Ramps Logarithmic-S Ramps Flashing LED, 2s period Flashing LED, extended falling ramp LED current transient 5mA to 20mA Shutdown Mode delay (Enable control SDA toggling)

configured independently to one of the 192-step current levels or turned off. when it is being ramped-up and down. setting register Reg 1 bit 7 to 1 or 0 respectively. channel can be configured to timer1 or timer2 with the Channel Control register Reg 4. Figure 2. Channel Timing Diagram

The timing diagrams for the four time slots are illustrated below. Figure 3. Timer Slot Timing Diagram

t KTD2026/KTD2027 April 2020 – Revision 04h Page 10 Company Confidential Timer Slot2 Example* Timer Slot3 Example* *Programming these patterns requires to write to several registers and therefore involves multiple I2C commands. Start Repeat at Tflash rate Timer Control: Example 2 Tslot1 Tslot2 Tslot3 Rest of Period Timer1 Timer1Timer2 Ch1 = 10 => Ch1=PWM1 Ch2 = 11 => Ch2=PWM2 Ch3 = 01 => Ch3=PWM2 Ch4 = 00 => Ch4=Always On TimerCtrl = 01 => PWM2 = Tslot2 Tslot4 Timer2 PWM2 PWM1 t1t0 t2 t3 t4 t0 = start t1 = Tim1 t2 = Tim1+Tfall t3 = Tim1+Tfall+Trise t4 = Tim1+Tim2+2*Tfall Note: PWM1 is always in Tslot1 Channel Control Register: Timer Slot Control Register: TimerCtrl = 10 => PWM2 = Tslot2 TimerCtrl = 01 Start Repeat at Tflash rate Timer Control: Example 1 Tslot1 Tslot2 Tslot3 Rest of Period Timer1 Timer1Timer2 Ch1 = 10 => Ch1=PWM1 Ch2 = 11 => Ch2=PWM2 Ch3 = 01 => Ch3=Always On Ch4 = 00 => Ch4=Always Off TimerCtrl = 10 => PWM2 = Tslot3 Tslot4 Timer2 PWM2 PWM1 t1t0 t2 t3 t4 t0 = start t1 = Tim1 t2 = Tim1+Tfall t3 = Tim1+Tim2+2*Tfall t4 = 2*Tim1+Tim2+3*Tfall Note: PWM1 is always in Tslot1 Channel Control Register: Timer Slot Control Register: TimerCtrl = 11 => PWM2 = Tslot3 TimerCtrl = 10 = > PWM2 = Tslot3

t KTD2026/KTD2027 April 2020 – Revision 04h Page 11 Company Confidential Each channel can be assigned to one of the 2 time slots, or always OFF or always ON. The Timer Slot Control register bits define the timing of the second PWM waveform. The Duty Cycle of each flash waveform is set by the timer and can be set with 8 -bit resolution (256 steps) between 0 and 100%. The period of the flash repetition rate can also be set with a 7-bit resolution up to 8 seconds (256ms steps starting at 64ms). The Flash repetition period is the same for all outputs. If the programmed total time of the Timers exceed the Flash repetition rate then the PWM2 slot will be terminated and the Timers reset to start position. This may cause the PWM2 signal to be instantly reduced to zero. Rise/Fall Times The Ramp-Up and Ramp -Down can be linear or S -shaped profile. The S-shape is the default. The ramp-up transitions from 0% to 100% of the Iset value (ON state) and ramp-down to 0% (OFF state). LED Basic Control The brightness setting of each channel is internally controlled by 48 current units of 0.5mA . Output current resolution is increased to an effective 0.125mA steps by interpolation based time division multiplexing (similar to PWM) by a digital interpolator and works on the 2 LSB units of the current setting. The Stay-Alive/Control Enable Bits are used to permit the Flash pattern to continue or be a one-shot.

Table 1. Register Map

t KTD2026/KTD2027 April 2020 – Revision 04h Page 13 Company Confidential Register Description Reg0 EN/RST Reg0 [2:0] Timer Slot Control / Reset Control TCtrl / Reset Modes Reg0[2:0] Function D2 D1 D0 0 0 0 TCtrl: Tslot1 0 0 1 TCtrl: Tslot2 0 1 0 TCtrl: Tslot3 0 1 1 TCtrl: Tslot4 1 0 0 Do Nothing (bit cleared) 1 0 1 Reset Registers only 1 1 0 Reset Main Digital only 1 1 1 Reset Complete Chip After power-up or VIN dropping below 2.7V, the device should be reset by writing Reg0 = 111 binary. All registers are then restored to their default reset values. After sending the command for complete chip reset Reg0[2:0]=111, a 200µs delay is recommended before the next command to allow the device to execut e the complete reset. Reg0 [4:3] Enable Control The device enable condition is defined by the two bits Reg0[4:3]. Four different conditions can trigger the device to turn ON depending on the two inputs SCL and SDA. Enable Control Reg0[4:3] Device ON Condition Device Enters Shutdown Mode Condition D1 D0 SCL SDA 0 0 High High Either SCL or SDA goes low 0 1 High SDA toggling Either SCL goes low or SDA stops toggling 1 0 High Don’t care SCL goes low 1 1 Always ON Device always ON Reg0 [6:5] Rise/Fall Time Scaling These two bits allow to scale the rise and fall times defined in Reg5 ramp rate register. For example, Reg0[6,5] = 01 (2x slower scaling) and Reg5 = 1, then the rise time = 96ms x 2 = 192ms. Rise/Fall Time Scaling Reg0[6:5] D1 D0 0 0 1x Normal 0 1 2x Slower 1 0 4x Slower 1 1 8x Faster Bit Reg0[7] must be kept to 0 and is not used in normal operation (reserved for factory test).

t KTD2026/KTD2027 April 2020 – Revision 04h Page 14 Company Confidential Reg1 Flash Period and Reg2/Reg3 ON Timer 1/2 The three registers Reg1, Reg2 and Reg3 allow configur ation of the blinking time for the two timer s 1/2, associated with PWM1 and PWM2 . Reg2 and Reg3 define the LED ON time as a percentage of the period defined in Reg1. The ON time (Ton) includes the ramp rise time as shown in Figure 2. For example, for Reg1 = 4 and Reg2 = 5, ON timer 1 is equal to 2% of 0.64s = 12.8ms Reg1[6-0] Flash Period Reg2/Reg3 Flash ON Timer 1/2 Dec Binary Period[s] Dec Binary Percentage of Period[%] 0 0000000 0.128 0 00000000 0.0% 1 0000001 0.384 1 00000001 0.4% 2 0000010 0.512 2 00000010 0.8% 3 0000011 0.640 3 00000011 1.2% 4 0000100 0.768 4 00000100 1.6% 5 0000101 0.896 5 00000101 2.0% 6 0000110 1.024 6 00000110 2.3% 7 0000111 1.152 7 00000111 2.7% 8 0001000 1.28 8 00001000 3.1% 9 0001001 1.408 9 00001001 3.5% 10 0001010 1.536 10 00001010 3.9% 11 0001011 1.664 11 00001011 4.3% 12 0001100 1.792 12 00001100 4.7% 13 0001101 1.92 13 00001101 5.1% 111 1101111 14.46 239 11101111 93.4% 112 1110000 14.59 240 11110000 93.8% 113 1110001 14.72 241 11110001 94.1% 114 1110010 14.85 242 11110010 94.5% 115 1110011 14.98 243 11110011 94.9% 116 1110100 15.10 244 11110100 95.3% 117 1110101 15.23 245 11110101 95.7% 118 1110110 15.36 246 11110110 96.1% 119 1110111 15.49 247 11110111 96.5% 120 1111000 15.62 248 11111000 96.9% 121 1111001 15.74 249 11111001 97.3% 122 1111010 15.87 250 11111010 97.7% 123 1111011 16.0 251 11111011 98.0% 124 1111100 16.13 252 11111100 98.4% 125 1111101 16.26 253 11111101 98.8% 126 1111110 16.38 254 11111110 99.2% 127 1111111 One Shot 255 11111111 99.6%

t KTD2026/KTD2027 April 2020 – Revision 04h Page 15 Company Confidential Reg1[7] Ramp Linear The default setting, bit Reg1[7] = 0, provides with a logarithmic-like S ramp up and down curve. By setting this bit to 1, the ramp becomes a simple linear up and down waveform. Reg4 LED Enable Control Register Reg4 sets the mode of each LED channel to either always ON/OFF or PWM1/PWM2. For example Reg4 = 00000001(binary), sets LED1 ON and other channels OFF. LED Enable (1/2/3/4) Dec Binary Function 0 00 Always OFF 1 01 Always ON 2 10 PWM1 3 11 PWM2 Reg5 Ramp Times The register Reg5 sets the rise and fall time durations for the LED current ramp transitioning between 0mA and the nominal current. The rise and fall ramp times are defined by 4 bits Reg5[3-0] and Reg5[7-4] respectively. For example, Reg5 = 4 and Reg0[6,5] = 0 (1x ramp scaling), then the rise time is equal to 512ms. Trise Reg5[3-0] Ramp Time [ms] Tfall Reg5[7-4] Ramp Scaling6 Dec Binary 00 slower slower faster 0 0000 (Default) 2 2 2 2 1 0001 128 256 512 16 2 0010 256 512 1024 32 3 0011 384 768 1536 48 4 0100 512 1024 2048 64 5 0101 640 1280 2560 80 6 0110 768 1536 3072 96 7 0111 896 1792 3584 112 8 1000 1024 2048 4096 128 9 1001 1152 2304 4608 144 10 1010 1280 2560 5120 160 11 1011 1408 2816 5632 176 12 1100 1536 3072 6144 192 13 1101 1664 3328 6656 208 14 1110 1792 3584 7168 224 15 1111 1920 3840 7680 240 6. There is only one Tramp Scaling register for both the rise and fall times.

t KTD2026/KTD2027 April 2020 – Revision 04h Page 16 Company Confidential Reg6, Reg7, Reg8, Reg9 LED Current Setting Registers Reg6 to Reg9 define the LED current setting for the channels D1 to D4 respectively. The LED current can be programmed to 192 levels between 0.125mA minimum and 24mA maximum with 0.125mA step. For example, 24mA is set by the code BF hexadecimal (191 decimal, 1011 1111 binary) or any higher code value. 10mA current is set by the code 4F hexadecimal (79 decimal, 0100 1111 binary) Iout (mA) Data Dec Data Hexa Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 17 Bit 07 0.125 0 (default) 00h (default) 0 0 0 0 0 0 0 0 0.25 1 01h 0 0 0 0 0 0 0 1 0.38 2 02h 0 0 0 0 0 0 1 0 0.50 3 03h 0 0 0 0 0 0 1 1 10.00 79 4Fh 0 1 0 0 1 1 1 1 10.13 80 50h 0 1 0 1 0 0 0 0 20.00 159 9Fh 1 0 0 1 1 1 1 1 20.13 160 A0h 1 0 1 0 0 0 0 0 23.88 190 BEh 1 0 1 1 1 1 1 0 24.00 191 BFh 1 0 1 1 1 1 1 1 24.00 192 C0h 1 1 0 0 0 0 0 0 24.00 254 FEh 1 1 1 1 1 1 1 0 24.00 255 FFh 1 1 1 1 1 1 1 1 7. The 2 LSB’s are timed division multiplexed (similar to PWM) by a digital interpolator. Minimum Iout unit is 0.5mA.

t KTD2026/KTD2027 April 2020 – Revision 04h Page 17 Company Confidential

Application Information

On the KTD2026/KTD2027, the ten internal registers Reg0 to Reg9 can be accessed via the I 2C interface. The I2C device address of KTD2026/KTD2027 is 0x30 hexadecimal or 110000 binary, KTD2026B device address is 0x31 hexadecimal or 110001 binary and KTD2026C device address is 0x32 hexadecimal or 110010 binary. The read and write commands allow to modify the content of each register . For further details on the I 2C protocol, please refer to the I2C−Bus Specification, document number 9398 393 40011, from Philips Semiconductors. The protocol for Write and Read is the following. Write: where S = START condition P = STOP condition Device Address = 0110000 (7 bits, MSB first) [KTD2026B=0110001, KTD2026C=0110010] Register Address = Reg0 - Reg9 address (8 bits) Data = data to read or write (8 bits) 1 = Read command bit 0 = Write command bit A = acknowledge (SDA low) A* = not acknowledge (SDA high) For example, the command to write KTD2026/KTD2027 register Reg4 (address 4) = 0, LEDs always OFF: Note: For the I2C Reset commands (“Reset Register only” and “Reset Complete Chip”), the last byte is followed by a “not acknowledge” (SDA high). For these two commands , the lack of acknowledge at the end of the command is to be ignored. Read: From slave (KTD2026/7) to master From master to slave (KTD2026/7) S Device Address Register Address1 A A Data A* P ‘1’ Read 7 bits 8 bits 8 bits S Device Address Register Address A A Data A P ‘0’ Write 7 bits 8 bits 8 bits S 0110000 00000100 A A 00000000 A P

The KTD2026/KTD2027 can wake-up from shutdown mode by toggling the SDA input. Figure 4. Wake-up from Shutdown Mode consumption can be set to “zero current” by putting the device into shutdown or sleep mode. LED3 (blue) is flashing. KTD2026 VIN pin current (IIN) = 260µA typical. To enter sleep mode: Write Enable Control mode register Reg0[4:3] = 01, for mode “SCL=High & SDA Toggling”. LEDs are now off. IIN = “zero” when there is no activity on the SDA line. (blue) is flashing. IIN = 260µA. lower forward voltage drop (VF). For example, the majority of vendors’ Blue LED’s VF at 5mA is 3.15V or below. for the lowest voltage possible. voltage at 24mA per channel. as when the LED current drops to 90% of the nominal programmed current level.

1. Minimum Wake-up Time (tWK_L): min.10µs
2. Delay between the last SDA rising edge and the beginning of a new command (tCD): 400µs min., 600µs max.

t KTD2026/KTD2027 April 2020 – Revision 04h Page 19 Company Confidential At 24mA, the typical VSINK can be as low as 75mV for each Dx pin. Since every LED has a slightly different VF at a given current, the minimum VIN is determined by the highest VF plus 75mV typical. For the case of 24mA programmed current and highest VF of 3.2V, VIN in can go as low as 3.275V without losing LED current regulation. When VIN drops further while the VSINK(MIN) remains constant, VF will be forced lower. As a result, the LED current will reduce according to each LED’s V-I curve. Recommended PCB Layout The input capacitor C1 should be mounted between the VIN pin and the ground pla ne close to the UTDFN package. The GND pin should be connected to the GND plane and to the center pad underneath the package. The package exposed pad should be soldered to the ground plane to improve the thermal dissipation.

t KTD2026/KTD2027 April 2020 – Revision 04h Page 20 Company Confidential Packaging Information UTDFN 1.5x1.5 – 8 pin Recommended Footprint D E L E2 0.200 e A Pin 1 Identifier C0.15x45º Top View Bottom View Side View b 2 3 58 7 6 K 0.0500 PIN 1 INDEX AREA 1.45 * Dimensions are in millimeters. 0.25 0.40 0.45 0.80 1.05 Dimension mm Min. Typ. Max. A 0.45 0.50 0.55 A3 0.127 REF. A1 0.00 0.02 0.05 b 0.15 0.20 0.25 D 1.45 1.50 1.55 D2 1.15 1.20 1.25 E 1.45 1.50 1.55 E2 0.65 0.70 0.75 e 0.40 BSC L 0.125 0.175 0.225 K 0.200 - -

t KTD2026/KTD2027 April 2020 – Revision 04h Page 21 Company Confidential Tape and Reel Specifications Reel Dimensions Tape Dimensions Kinetic Technologies cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Kineti c Technologies product. No intellectual property or circuit patent licenses are implied. Kinetic Technologies reserves the right to change t he circuitry and specifications without notice at any time. A T N C G Po DoP2 D1 P1 E F W Bo Ko Ao T Θ R Po DoP2 D1 P1 E F W Bo Ko Ao T Θ R Po DoP2 D1 P1 E F W Bo Ko Ao T Θ R D0P2P0 D1 P1 E F W T RB0 θ Dimension mm Min. Typ. Max. A 176 178 180 C 12.8 13.0 13.5 G 7.9 ─ 10.9 N 50 55 60 T ─ ─ 14.4 Dimension mm Min. Typ. Max. A0 1.65 1.70 1.75 B0 1.65 1.70 1.75 K0 0.65 0.70 0.75 P0 3.9 4.0 4.1 P1 3.9 4.0 4.1 P2 1.95 2.00 2.05 D0 1.5 1.55 1.6 D1 1.00 ─ ─ E 1.65 1.75 1.85 F 3.45 3.50 3.55 10P0 39.8 40.0 40.2 W 7.9 8.0 8.3 T 0.18 0.20 0.22 Θ 0° ─ 5° Θ2 0° ─ 5°