KTB8371CEIB-5C-TR

KTB8371 KINETIC | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 21

Technical content

Features

• Wide VIN Range: 4.7V to 17V
• Maximum Continuous Output Current: 5A
• I2C Control Interface
• Programmable Output Voltage from 0.8V to 5.5V
• Integrated High / Low-Side FETs (65mΩ / 35mΩ)
• Advanced Adaptive On-Time Control
• Fast Transient Response
• ±0.5% Feedback Voltage Reference
• Zero Shutdown Supply Current
• 50μA Non-Switching Operating Quiescent Current
• 80μA No Load Operating Quiescent Current
• High Efficiency in Light Load and Heavy Load.
• Programmable Switching Frequency with 500kHz, 1MHz, 1.5MHz, and 2MHz options
• Internal Soft-Start
• Programmable Forced CCM, Automatic CCM/PFM
• Built-in Cycle-by-Cycle Current Limit, Short Circuit Protection, Input UVLO, Output Under-Voltage Protection, Output Over-Voltage Protection, and Thermal Shutdown Protection
• Small 20-bump WLCSP (1.7mm x 2.0mm)

Applications

• CPU, GPU, AP, DSP, FPGA, VIO, VSYS
• HDD, LPDDR3, LPDDR4 Memory Power
• Tablets, Netbooks, Ultra-Books, Mobile Internet Devices, IoT, and Server.
• DSC, Drones, Gaming Consoles, TV Set Box

Description

The KTB8371 is 5A, 17V synchronous buck regulators with integrated high-side and low-side power FETs. The device operates over a wid e input voltage range to support a variety of applications with input voltage from regulated 5V and12V power rails and multicell batteries. KTB8371 employs Kinetic’s proprietar y advanced adaptive on -time (AOT) control for fast transient response and high output voltage accuracy. This control technique eliminates external loop compensation network and allows the use of ceramic output capacitors without ripple -generating circuitry . These features enable very small total solution size and make the KTB8371 easy to use. The device features an internal soft-start function to limit inrush current during start -up. The output voltage can be adjusted via I 2C with 3μs/step ramp -up/down rat e. The device has comprehensive built -in protection features including input voltage UVLO, high -side cycle- by-cycle peak current limit, low-side valley current limit, reverse current protection, short -circuit protection, output over-voltage protection, and thermal shutdown. KTB8371 are available in RoHS and Green compliant 20-bump 1.7mm x 2.0mm x 0.6mm wafer -level chip - scale package (WLCSP20). Typical Application Schematic CIN COUT VOUT VIN PVIN AVIN BST LXPGND VDD VDR VOUT SCL EN AGND CBST CDD CDR SDA

January 2021 – Revision 04a Page 2 of 21 Kinetic Confidential Pin Descriptions Pin # Pin Name Function A1, A2, A3, A4 PGND Power ground for buck regulator B1, B2, B3, B4 LX Inductor connection for buck regulator C1, C2, C3, C4 PVIN, AVIN Input Voltage Power and Sense Pins for buck regulator. Connect to a power rail ranges from 4.7V to 17V. D1 BST Boost capacitor for charge pump gate driver D2 SCL I2C clock digital input D3 EN Chip enable logic input D4 VDR Power stage driver voltage E1 VOUT Output voltage sense input E2 SDA I2C data digital I/O E3 VDD Analog circuit bias voltage E4 AGND Analog ground for analog circuit Pinout Diagram WW XXYY ZZZZ A B C D 1 2 3 4 LX PVIN, AVIN PVIN, AVIN E Top View PGND LX PVIN, AVIN PVIN, AVIN SCLBST SDAVOUT PGND PGND PGND LX LX EN VDR VDD AGND Top View 20-Bump 1.710mm x 2.063mm x 0.62mm Top Mark WW = Device ID Code, XX = Date Code YY = Assembly Code, ZZZZ = Serial Number

January 2021 – Revision 04a Page 3 of 21 Kinetic Confidential Absolute Maximum Ratings1 (TA = 25C unless otherwise noted) Description Value Units PVIN to PGND -0.3 to 18 V PGND to AGND -0.3 to 0.3 V LX to PGND -0.3 to (PVIN +0.3) V BST to LX -0.3 to 5.5 V VOUT, VDD, and VDR to AGND -0.3 to 5.5 V EN, SCL, SDA to AGND -0.3 to 5.5 V LX Continuous Current 7 ARMS Peak Current (2.5ms maximum) 10 APEAK Operating Junction Temperature Range -40 to 150 C Storage Temperature Range -55 to 150 C Maximum Soldering Temperature (at leads, 10 sec) 260 C ESD Ratings2 Symbol Description Value Units V(ESD) Electrostatic Discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins ±2000 V Charged device model (CDM), per JEDEC specification JESD22C101, all pins ±500 Thermal Capabilities3 Symbol Description Value Units ΘJA Thermal Resistance – Junction to Ambient 67.7 C/W PD Maximum Power Dissipation at TA = 25°C 1.85 W ∆PD /∆T Derating Factor Above TA = 25°C -14.77 mW/C

Ordering Information

Part Number Marking4 Default Settings5 Package VOUT Fsw Mode KTB8371AEIB-5C-TR OXXXYYZZZZ 5.0V 500kHz Auto-Skip WLCSP20 KTB8371BEIB-5C-TR PBXXYYZZZZ 3.3V 500kHz Auto-Skip WLCSP20 KTB8371CEIB-5C-TR PFXXYYZZZZ 1.8V 500kHz Auto-Skip WLCSP20 1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time. 2. ESD Ratings conform to JEDEC industry standards. Some pins may actually have higher performance. Ratings apply with chip en abled, disabled, or unpowered, unless otherwise noted. 3. Junction to Ambient thermal resistance is highly dependent on PCB layout. Values are based on thermal properties of the devi ce when soldered to an EV board. 4. XX = Date Code, YY = Assembly Code, ZZZZ = Serial Number. 5. The first released part is Vout = 3.3V. Please Contact a Kinetic Technologies representative regarding versions with other default settings.

January 2021 – Revision 04a Page 4 of 21 Kinetic Confidential Electrical Characteristics6 Unless otherwise noted , Typ values are specified at +25°C with V IN = 12V. The Min and Max specs are applied over the full operation temperature range of -40°C to +85°C and VIN = 4.7V to 17V. Symbol Description Conditions Min. Typ. Max. Units Supply Specifications PVIN Input Supply Operating Range 4.7 17 V VUVLO Under-Voltage Lockout Threshold VIN rising 3.35 4.25 4.7 V Hysteresis 500 mV IIN VIN Supply Current EN = High, VIN = 12V, Non-Switching 50 µA EN = High, VIN = 12V, Auto-Skip 80 µA EN = High, VIN = 12V, Forced-PWM 10 mA ISHDN Shutdown Supply Current EN = Low, TA = 25C 0.01 1 µA Logic Pin Specifications (EN) VIH Input Logic High (EN) 3.8 V VIL Input Logic Low (EN) 0.4 V II_LK Input Logic Leakage (EN) TA = 25C, VEN = 5V 0.01 1 µA I2C-Compatible Interface Specifications (SCL, SDA), see Figure 1 VIH Input Logic High Threshold 3.8 V VIL Input Logic Low Threshold 0.4 V VOL SDA Output Logic Low ISDA = 3mA 0.4 V t1 SCL clock period 2.5 µs t2 Data in setup time to SCL high 100 ns t3 Data out stable after SCL low 0 ns t4 SDA low setup time to SCL low (Start) 100 ns t5 SDA high hold time after SCL high (Stop) 100 ns Thermal Shutdown Specifications TJ_SHDN IC Junction Thermal Shutdown TJ rising 150 °C Hysteresis 20 °C Continue on page 5 6. Device is guaranteed to meet performance specifications over the -40C to +85C operating temperature range by design, characterization and correlation with statistical process controls.

January 2021 – Revision 04a Page 5 of 21 Kinetic Confidential

Electrical Characteristics

Unless otherwise noted , Typ values are specified at +25°C with V IN = 12V. The Min and Max specs are applied over the full operation temperature range of -40°C to +85°C and VIN = 4.7V to 17V. Buck Regulator Specifications VOUT KTB8371A Output Voltage Setting Range I2C Programmable, see VSEL Configuration Register(0x00[5:0]) 2.0 5.5 V KTB8371B Output Voltage Setting Range I2C Programmable, see VSEL Configuration Register(0x00[5:0]) 1.2 3.3 V KTB8371C Output Voltage Setting Range I2C Programmable, see VSEL Configuration Register(0x00[5:0]) 0.8 2.2 V VOUT_STEP KTB8371A Output Voltage Setting Step size 100 mV KTB8371B Output Voltage Setting Step size 60 mV KTB8371C Output Voltage Setting Step size 40 mV VOUT_acc Output Voltage DC Accuracy TA = 25C, FPWM -0.7 0.7 % IOUT_max Maximum Continuous Output Current 5 A Ipeak High-Side Switch Peak-Current Limiting Threshold 6.4 8 9.6 A Ivalley Low-Side Switch Valley-Current Limiting Threshold 6 7.5 9 A Irev Low-Side Reverse Current Limiting Threshold Forced PWM Mode -3 A Izcd Zero-Crossing-Detection Threshold Automatic Skip Mode 0 mA Rdson_h High-Side Switch On-Resistance 60 75 mΩ Rdson_l Low-Side Switch On-Resistance 30 40 mΩ RLX_DIS LX Active Discharge Resistance Auto discharge mode enable in Default Setting 200 Ω KAOT Adaptive-On-Time Constant tON = KAOT x (VOUT/VIN) 2100 ns Fsw Switching Frequency Default Fsw = 500kHz 500 kHz Default Fsw = 1000kHz 1000 Default Fsw = 1500kHz 1500 Default Fsw = 2000kHz 2000 tSS_DELAY VOUT Soft-Start Delay EN = Low to High 2 ms VOUT_RR VOUT Soft-Start Ramp Rate VOUT = 5V 8 mV/µs VOUT = 3.3V 4 VOUT = 1.8V 3 Figure 1. I2C Compatible Interface Timing

January 2021 – Revision 04a Page 6 of 21 Kinetic Confidential Typical Characteristics Unless otherwise noted, VIN = 12V, VOUT = 3.3V, fSW = 500kHz, and TA = 25°C. Efficiency (L1 = 2.2µH, fsw = 500kHz) Efficiency (L1 = 2.2µH, fsw = 500kHz) Efficiency (L1 = 2.2µH, fsw = 500kHz) No Load Input Supply Current vs VIN Switching Frequency vs. Output Current Line Regulation (VOUT = 5V, Auto-Skip Mode) 0.01 0.1 1 10 100 Efficiency vs. Ouput Current Efficiency ( % ) Output Current ( A ) VOUT=5.0V AUTO MODE VIN=7V VIN=12V VIN=17V 0.01 0.1 1 10 100 Efficiency vs. Ouput Current Efficiency ( % ) Output Current ( A ) VOUT=3.3V AUTO MODE VIN=7V VIN=12V VIN=17V 0.01 0.1 1 10 100 Efficiency vs. Ouput Current Efficiency ( % ) Output Current ( A ) VOUT=1.8V AUTO MODE VIN=7V VIN=12V VIN=17V

January 2021 – Revision 04a Page 7 of 21 Kinetic Confidential Typical Characteristics (continued) Unless otherwise noted, VIN = 12V, VOUT = 3.3V, fSW = 500KHz, and TA = 25°C. Line Regulation (VOUT = 3.3V, Auto-Skip Mode) Line Regulation (VOUT = 1.8V, Auto-Skip Mode) Load Regulation (VOUT = 5V, Auto-Skip Mode) Load Regulation (VOUT = 3.3V, Auto-Skip Mode) Load Regulation (VOUT = 1.8V, Auto-Skip Mode) Soft Start with EN (VIN = 5V, IOUT = 5.0A) IOUT 5V / div 2ms / div VOUT 2V / div LX 5V / div EN 5V / div

January 2021 – Revision 04a Page 8 of 21 Kinetic Confidential Typical Characteristics (continued) Unless otherwise noted, VIN = 12V, VOUT = 3.3V, fSW = 500kHz, and TA = 25°C. Shutdown with EN (VIN = 5V, IOUT = 5.0A) Output Active Discharge (VIN = 12V, IOUT = 0mA) Output Voltage Ripple (VIN = 12V, IOUT = 5A) Load Transient (0.1A-2.5A, Auto-Skip Mode) Load Transient (1.5A-4.5A, Auto-Skip Mode) Load Transient (0A-4.5A, Auto-Skip Mode) IOUT 5V / div 40µs / div VOUT 2V / div EN 5V / div LX 5V / div IOUT 20mA / div 20ms / div VOUT 2V / div LX 10V / div EN 5V / div LX 10V / div 20ms / div IL 2A / div VOUT AC Coupling 20mV / div IL 2A / div 100µs / div VOUT 100mV / div IL 2A / div 100µs / div VOUT 100mV / div IL 2A / div 100µs / div VOUT 200mV / div

January 2021 – Revision 04a Page 9 of 21 Kinetic Confidential Typical Characteristics (continued) Unless otherwise noted, VIN = 12V, VOUT = 3.3V, fSW = 500kHz, and TA = 25°C. Short Circuit Protection (Hiccup Mode) Output Short Protection Recovery (Hiccup Mode Recovery) Functional Description The KTB8371 is a highly efficient, high-performance, monolithic buck regulator that operates from an input voltage of 4.7V to 17.0V and can output up to 5A. It integrates the main switch, synchronous rectifier switch, PWM control circuitry, VOUT setting DAC, various protection features, and an I 2C serial interface to configure the output voltage, dynamic voltage scaling (DVS), control modes change, and software enable/disable function. Control Scheme The KTB8371 uses a proprietary adaptive on -time (AOT) PWM control scheme to maintain a nearly constant switching frequency as input voltage and output voltage vary . Compared to typical current -mode PWM schemes, the AOT control scheme provides quick response to line and load transients with excellent stability and wide bandwidth, thereby minimizing output voltage droop and soar for dynamic loads, even with minimal output capacitance. The adaptive on -time approximates fixed-frequency switching without using a fixed clock oscillator, which eliminates the need to wait for the next clock before responding to a load transient . The KTB8371 feedback loop also adds a proprietary, internal -compensated, integrating error ampli fier to remove the output voltage offset normally associated with other AOT, constant on-time (COT), and hysteretic architectures. Shutdown Mode When the EN pin is low, the KTB8371 buck is in shutdown mode and draws 0 supply current. Hardware Enable The KTB8371 buck regulator is turned on and off via hardware enable using the EN pin. The default register settings allow simple hardware control. For hardware enable, drive the EN pin high. For hardware disable, drive the EN pin low. Software Enable KTB8371 also can be enabled using I2C commands. For software enable/disable control, bring the chip’s EN pin to high first. After that, write 1 into the bit (0) of CONTL1 configuration register(0x05) to enable the buck, and write 0 to disable the buck. Refer I2C register map for detailed information. Soft-Start The KTB8371 buck contains soft-start circuitry to ramp up VOUT slowly in order to reduce inrush current at V IN and prevent the inductor current from reaching the peak current limit during startup. IL 5A / div 10ms / div VOUT 2V / div LX 10V / div IL 5A / div 20ms / div VOUT 2V / div LX 10V / div

in 40mV steps. The reference is controlled by VOUT[5:0] in the configuration register (0x00). The target voltage can be set according to the following Table 1. Table 1. Output Voltage Setting by VSEL Register(0x00[5:0])

January 2021 – Revision 04a Page 11 of 21 Kinetic Confidential Dynamic Voltage Scaling (DVS) For KTB8371, each time VREF is set to different value, Dynamic Voltage Scaling (DVS) is used to slew the output voltage to the new voltage according above table. The DVS slew rate is 12 µs/step ramp -up/down with each reference step 20mV. User should not change DIV register during the DVS. DIV register can only be changed when chip switching is disabled by setting “chipEnb” high. Chang DIV register value when chip is still switching can damage the chip. Forced-PWM vs. Auto-Skip Modes KTB8371 has two ways to control switching behavior – Forced-PWM mode and Auto-Skip mode. In Forced-PWM, the switching frequency remains nearly constant. This mode is helpful for applications that are noise sensitive. In Auto -Skip mode, the Buck converter transitions automatically between PWM switching at heavy loads and Skip/PFM switching at light loads. Auto-Skip mode is helpful for applications that need high efficiency at light loads. While skipping, single pulses are evenly spaced, resulting in the lowest output ripple and noise when compared to competing “pulse-grouping” or “burst mode” devices. The switching mo de is I 2C programmable using the FPWM bit (B2) in the CONTL0 configuration register (0x01). The default mode settings are factory trimmed, and several versions are available – see the Ordering Information section. Active Discharge When the KTB8371 buck is disabled, an active discharge feature can be achieved by connects an about 200ohm on-chip resistor (R LX_DIS) between the LX and PGND pins. This resistor discharges the output capacitor through the inductor. This discharge function can be enabled or disabled using the DISCH bit (B0) in the CONTL0 register (0x01) Register Reset The KTB8371 does NOT contain non-volatile memory for the register settings . When VIN rises above VUVLO, either at initial power up or after a temporary V IN droop below VUVLO, a Power-On Reset (POR) circuit resets all registers to their factory default settings. Thereafter, as long as V IN remains above V UVLO, the I2C registers can be written and read, and register contents are preserved, regardless if the buck is enabled or disabled. Internal Status Monitor The KTB8371 contains a MONITOR status register (0x04), which can be read to check the present status of the IC. The register has individual bits for the status of VIN power-OK, VOUT power-OK, over-temperature thermal shutdown, and boost low voltage. Refer to the MONITOR register (0x04) description for more details. Input Under-Voltage Lockout (UVLO) When the input voltage (VIN) is below the under-voltage lockout threshold (VUVLO), the buck is disabled. When V IN rises above VUVLO, either at initial power up or after a temporary V IN droop below VUVLO, a Power-On Reset (POR) circuit resets all registers to their factory default settings. After POR, and if the buck is enabled, the default soft - start ramp begins. Inductor Over-Current Protection (OCP) KTB8371 can protect the buck and the inductor during over -current faults. The current limits control the buck’s switching on a cycle-by-cycle basis and have a higher priority than the regulation threshold and adaptive on -time. During sustained over-current faults, the output voltage typically droops below the regulation threshold. Both high side FET and low side FET have OCP protection circuit. When either high side or low side FET conduct a current high than OCP threshold, a 50ns timing pulse will be triggered. During this 50ns, high side FET will be OFF and lowside FET will be ON. After this 50ns timing pulse, if low side FET’s current is still larger than its OCP threshold, low side FET will continue be ON and high side FET will be kept OFF. High side FET can only be ON again when low side FET’s current goes below its OCP threshold.

January 2021 – Revision 04a Page 12 of 21 Kinetic Confidential Hiccup Mode and Output Short-Circuit Protection (SCP) If above OCP event continuously (Eg. above 50ns timing pulses trigged within 2 µs) happened 8 times, the buck enters hiccup mode and pause all switching. After 20ms, the buck attempts to soft -start. If the fault persists, the buck once again enters hiccup mode and periodically re-attempts soft-start until the fault is removed. The low duty- factor during hiccup mode prevents the IC from getting hot. When BUCK output short happens, if OCP event continuously happened 8 times, the chip will enter hiccup mode. If not, but under voltage detected after chip reference ramp beyond 5 steps, chip will also enter hiccup mode. Thermal Shutdown Over-Temperature (OT) Over-temperature (OT) protection occurs if the die junction temperature exceeds the thermal shutdown threshold (TJ_SHDN). During thermal shutdown, the buck pauses all switching until the die temperature cools. Once cooled, the buck re-starts with the programmed soft-start ramp. The OT status is reflected in the MONITOR register. Trim Options The KTB8371 is factory trimmed using one -time programmable (OTP) registers. Standard versions are available for various default output voltage settings and modes – see the Ordering Information section. Contact a Kinetic Technologies representative regarding versions with other default settings or I2C slave addresses. I2C Interface Description I2C Serial Data Bus The KTB8371 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the bus is called a master, whereas the devices controlled by the master are known as slaves. A master de vice must generate the serial clock (SCL), control bus access and generate START and STOP conditions to control the bus. The KTB8371 operates as a slave on the I2C bus. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast m ode (400kHz maximum clock rate) are defined. The KTB8371 works in both modes. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined in Figure 2:

• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy Both data and clock lines remain HIGH. Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a S TART condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.

• Master generates start condition.
• Master sends 7-bit slave address (1100100) and 1-bit data direction ‘0’ for write.
• Slave sends acknowledge if the slave address is matched.
• Master sends 8-bit register address.
• Slave sends acknowledge.
• Master sends 8-bit data for that addressed register.
• Slave sends acknowledge.
• If master sends more data bytes, the register address will be incremented by one after each acknowledge.
• Master generate stop condition to finish the write cycle. I2C Read Cycle For I2C read cycle, data is transferred from a slave to a master. But to start the read cycle, master needs to write the register address first to define which register data to read. Figure 4 shows the steps of the I2C read cycle.

Figure 4. I2C Read Cycle

• Master generates start condition.
• Master sends 7-bit slave address (1100100) and 1-bit data direction ‘0’ for write.
• Slave sends acknowledge if the slave address is matched.
• Master sends 8-bit register address.
• Slave sends acknowledge.
• Master generates repeated start condition.
• Master sends 7-bit slave address (1100100) and 1-bit data direction ‘1’ for read.
• Slave sends acknowledge if the slave address is matched.
• Slave sends the data byte of that addressed register.
• If master sends acknowledge, the register address will be incremented by one after each acknowledge and the slave will continue to send the data for the updated addressed register.
• If master sends no acknowledge, the slave will stop sending the data.
• Master generate stop condition to finish the read cycle. Rs Device Address 1 A P ‘1’ Read 7 bits 8 bits S Device Address Register Address0 A A ‘0’ Write 7 bits 8 bits Data A* From Slave to Master From Master to Slave S = Start Rs = Repeated Start A = Acknowledge (SDA Low) A* = No Acknowledge (SDA High) P = Stop

January 2021 – Revision 04a Page 15 of 21 Kinetic Confidential I2C Registers I2C Slave Address Options7 7-Bit Address Write Address Read Address Bits 7 6 5 4 3 2 1 0 Default 0x64 0xC8 0xC9 1 1 0 0 1 0 0 R/𝑊̅ Alternate 1 0x65 0xCA 0xCB 1 1 0 0 1 0 1 R/𝑊̅ Alternate 2 0x66 0xCC 0xCD 1 1 0 0 1 1 0 R/𝑊̅ Alternate 3 0x67 0xCE 0xCF 1 1 0 0 1 1 1 R/𝑊̅ I2C Register Map Hex Address Name Type Access Default Reset B7 B6 B5 B4 B3 B2 B1 B0 0x00 VSEL Config R/W 0011 1010 ADDRESS[1:0] VOUT[5:0] 0x01 CONTL0 Config R/W 0000 0000 FSWSEL[1:0] Reserved FPWM HIQ DISCH 0x02 ID0 Status R 1010 0010 VENDOR[2:0] DIE_ID[4:0] 0x03 ID1 Status R 0000 xxxx RSVD[3:0] DIE_REV[3:0] 0x04 ID2 Status R xxxx xxxx FAULT OT Reserved BSTLOW PVINOK PGOOD 0x05 CONTL1 Control R/W 0000 0000 RSVD[5:0] REGRST BUCKENB Register contents are reset in hardware to their defaults values by VIN power-on reset. Additionally, most registers can be reset in software by writing 1 to the RESET bit ( B7) in the CONTL 1 register (0x05). Default Reset bits marked with lower-case “x” in the register map and register details tables depend upon the ordered part# suffix and die revision; please see the Ordering Information section. Upper-case “X” used elsewhere in the tables designates “don’t care”. VSEL Configuration Register Register Address 0x00 Bit Name Access Default Reset Description 7:6 ADDRESS [1:0] R/W 00 Chip I2C Address Selection. ADDRESS bits 7-Bit Address 00 0x64 01 0x65 10 0x66 11 0x67 5:0 VOUT[5:0] R/W 101101 (KTB8371C) Sets the nominal VOUT regulation voltage. VOUT Setting VOUT[5:0] default VOUT Range VOUT(step) VOUT(min) VOUT(max) KTB8371C 101101 0.8V 2.2V 40mV KTB8371B 110111 1.2V 3.3V 60mV KTB8371A 110010 2.0V 5.5V 100mV NOTE: to change VOUT to a particular value, refer to Table1 110111 (KTB8371B) 110010 (KTB8371A) 7. For Alternate 1/2/3 Slave Addresses, please contact a Kinetic Technologies representative.

January 2021 – Revision 04a Page 16 of 21 Kinetic Confidential CONTL0 Configuration Register Register Address 0x01 Bit Name Access Default Reset Description 7:6 FSWSEL[1:0] R/W 00 Switching Frequency control. 00 = 0.5MHz 01 = 1.0MHz 10 = 1.5MHz 11 = 2.0MHz 5:3 Reserved R 00

2 FPWM R/W 0

Forced-PWM Mode control. 0 = Auto-Skip at light loads; PWM at heavy loads 1 = Forced-PWM at all loads

1 HIQ R/W 0

High Quiescent Current Mode control. 0 = lowest quiescent current, but pulse-grouping in Skip Mode 1 = higher quiescent current for single-pulse PFM in Skip Mode

0 DISCH R/W 0

Active Discharge of COUT when regulator is disabled. 0 = the buck output is high impedance(about200k) when regulator is disabled. 1 = the buck output is discharged via an internal pull-down resistor when regulator is disabled. ID0 Data Register Register Address 0x02 Bit Name Access Default Reset Description 7:5 VENDOR[2:0] R 101 Vendor Identification 101 = Kinetic Technologies 4:0 DIE_ID[4:0] R 0 0010 Die Type Identification 0 0010 = KTB8371 ID1 Status Register Register Address 0x03 Bit Name Access Default Reset Description 7:4 RSVD[3:0] R 0000 Reserved. Always reads back as 0000. 3:0 DIE_REV[3:0] R xxxx Die Revision Identification 0000 = Rev. A

January 2021 – Revision 04a Page 17 of 21 Kinetic Confidential ID2 Data Register Register Address 0x04 Bit Name Access Default Reset Description

7 FAULT R x

Indicate the IC at the fault status or not, 0 = normal status 1 = fault status (Any fault happens, like OT,OV,UV…listed in below. This bit will go to 1 to indicate a fault.)

6 OT R x

Indicate the IC at the OTP status or not, 0 = normal status 1 = OTP happens 5-3 Reserved R x

2 BSTLOW R x

Indicate the IC at the Boost Low status or not, 0 = normal status 1 = Boost low voltage happens

1 PVINOK R x

Indicate the IC at the PVIN_OK status or not, 0 = normal status, VIN is OK 1 = Vin UV happens

0 POWERGOOD R x

Indicate the IC at the Power good status or not, 0 = normal states, out voltage is in good regulation 1 = out voltage is out of regulation CONTL1 Configuration Register Register Address 0x05 Bit Name Access Default Reset Description 7:2 RSVD[5:0] R 0000 0 Reserved. Always reads back as 0000 0.

1 RESET R/W 0

Software Reset to default register settings. 0 = No reset 1 = Resets all the user registers. The RESET bit always reads back as 0.

0 BUCKENB R/W 0

Software Buck Enable control. 0 = buck is software enabled, external EN pin must be in high condition 1 = buck is software disabled, external EN pin must be in high condition

supplier.) Larger physical case-sizes, good winding designs, and better magnetic materials can increase efficiency. Table 2 is a list of recommended inductors from leading suppliers. Table 2. Recommended Inductors characteristic of the capacitor. Table 3 is a list of recommended capacitors from leading suppliers. Table 3. Recommended Capacitors cable, add additional bypass capacitance where VIN first arrives to the PCB. capacitance compared to lower VOUT settings. Note: 33mΩ is a constant related to internal control circuit. time with respect to the switching cycle of the regulator.

effective capacitance of 16µF. Figure 5. Typical DC Bias Derating Characteristic an Example 15µF Ceramic Capacitor.

1. Connect the input capacitor CIN as close as possible to the VIN and PGND pins using top-side thick metal
2. Connect the ground terminals of output capacitors COUT as close as possible to the ground terminal of CIN

and the PGND pins using top-side metal.

1. Connect the Boost capacitor as close as possible to the Boost pin and Lx pin of the chip.
2. Connect the local top-side PGND island to the PCB ground plane using multiple parallel vias.
3. Do not connect the AGND pins directly to the top-side PGND. Instead, connect the AGND pins to the

PCB ground plane using their own vias.

1. Connect the inductor to the LX pins with a wide trace.
2. Connect the VOUT terminals of the inductor to the output capacitors with a wide and short trace.
3. Route the VOUT sense trace from COUT to the VOUT pin with care to keep it away from noisy traces,

especially the LX trace. Additionally, use ground fill to shield noise from coupling into the VOUT sense.

1. Depending upon PCB design rules, it may be possible to place filled micro-vias directly under WLCSP

bumps. If not, route short traces to nearby vias. Figure 6. Recommended PCB Layouts

January 2021 – Revision 04a Page 21 of 21 Kinetic Confidential Packaging Information WLCSP45-20 (1.750mm x 2.063mm x 0.62mm) Recommended Footprint 3 X 0.400mm A1 Corner Top Side Die Coating Top View Bottom ViewSide View 0.620 ± 0.045mm 0.025 ± 0.003mm 1.750mm ± 0.050mm 2.063mm ± 0.050mm

20 X Ø

0.27 ± 0.027mm 4 X 0.400mm 0.215 ± 0.022mm (NSMD Pad Type) * Dimensions are in millimeters. 0.40mm 0.40mm 0.22mm Copper Pad Diameter 0.32mm Solder Mask Opening 1.2mm 1.6mm Kinetic Technologies cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Kinetic Technologies product. No intellectual property or circuit patent licenses are implied. Kinetic Technologies reserves the right to change the circuitry and specifications without notice at any time.