KT8555 SAMSUNG | Alldatasheet
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Technical content
KT8555 TIME SLOT ASSIGNMENT CIRCUIT INTRODUCTION The KT8555 is a per channel Time Slot Assignment Circuit (TSAC) that produces 8-bit receive and transmit time slots for four 1 CHIP CODEC. Each frame synchronization pulse may be independently assigned to a time slot in a frame of up to 84 time slots.
FEATURES
l Single, 5V operation l Low power consumption: 5mW l Controls four 1 CHIP CODEC l Independent transmit and receive frame syncs enables l channel unidirectional mode l Up to 64 time slots per frame l Compatible with KT8554/7 CODECs l TTL and CMOS compatible PIN CONFIGURATION Fig. 1 Device Package Operating Temperature KT8555J 20-CERDIP - 20°C ~ + 125°C GND FSX3 CH0 CH1 RSYC/CH2 XSYC BCLK FSX1 FSR1 FSX0 FSR0 TSX DC CLKC CS 1110 KT8555 VCC FSR2 FSX2 FSR3 MODE 20-CERDIP
ORDERING INFORMATION
KT8555 TIME SLOT ASSIGNMENT CIRCUIT PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Pin No Symbol Description FSX0 FSX1 FSX2 FSX3 A frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made. FSR0 FSR1 FSR2 FSR3 A frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made. 5 TSX This pin pulls low during any active transmit time slot. (N-channel open drain) 6 DC The input for an 8 bit serial control word. X is the first bit clocked in. 7 CLKC The clock input for the control interface. 8 CS The active-low chip select for the control interface.
9 MODE
Mode 1 = Open or VCC Mode 2 = Gnd
10 GND Ground
11 BCLK The bit clock input (2.048 MHz) 12 XSYC The transmit TSO sync pulse input. Must be synchronous with BCLK.
13 RSYC /CH2
The transmit time slot 0 sync pulse input. Must be synchronous with BCLK. In mode 1 this input is the receive time slot 0 sync pulse, RSYC, which must be synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word. 14 CH1 The input for the NSB (next significant bit) of the channel select word.
15 CH0
The input for the LSB (last significant bit) of the channel select word, which defines the frame sync output affected by the following control word. 20 VCC Power supply pin. 5V ±5% Characteristic Symbol Value Unit Positive Supply Voltage Input Voltage Output Voltage Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 secs) VCC VI VO TOPR TSTG TLEAD 7.0 VCC + 0.3 ~ - 0.3 VCC + 0.3 ~ - 0.3 - 25 ~ 125 - 65 ~ 150 300 V V V
KT8555 TIME SLOT ASSIGNMENT CIRCUIT ELECTRICAL CHARACTERISTICS (Unless otherwise noted; VCC = 5.0V ±5%, Ta = 0°C ~70°C) Characteristic Symbol Test Conditions Min Typ Max Unit Operating Current ICC BCLK = 2.048MHz, all outputs open 1 1.5 mA Input Voltage High VIH 2.0 V Input Voltage Low VIL 0.7 V Input Current 1 II1 All Inputs Except Mode, VIL<VIN<VIH -1 1 µA Input Current 2 II2 Mode, VIN = 0V -100 µA Output Voltage High VOH FS X and FSR Outputs, IOH = 3mA 2.4 V FS X and FSR Outputs, IOL = 3mA 0.4 V TS X output, IOL = 3mA 0.4 V tR (CK) tF(CK) BCLK, CLKC 50 nS Delay to TSX Low tD (TSX L) C L = 50pF 140 nS Delay to TSX High tD (TSX H) R L = 1KΩ to V CC 30 100 nS Hold Time from BCLK to Frame Sync tH (BFS) 50 nS Set-Up Time from Frame Sync to BLCK tH (FSB) 30 nS Delay Time from BLCK Low to FXX/R 0-3 High or Low C L = 50pF 50 nS Hold Time from Channel Select to CLKC tH (CSC) 50 nS Set-Up Time from Channel Select to CLKC tSU (CSC) 30 nS Period of Clock tCK BCLK, CLKC 240 nS Width of Clock High tW (CKH) BCLK, CLKC 50 nS Width of Clock Low tW (CLK) BCLK, CLKC 50 nS Set-Up Time from D C to CLKC tSU (Dc C) 30 nS Hold Time from CLKC to DC tH (CDc) 50 nS Set-Up Time from CS to CLKC tSU (CC) 30 nS Hold Time from CLKC to CS tH (CC) 100 nS 1 2 3 4 5 6 7 8 1 2 CLK C CS CH0, CH1 AND CH2 DC BCLK XSYC OR RSY C FS X OR FS R TS X tHCD tH(CC) tSU(CC) tW(CKH) tW(CKL) tR(CK) tF(CK) tH(CC) tSU(CC) tSU(CSC) tH(CSC) tD tSU(DcC) tSU(FSB) tDT(SxL) tWCH tH(BFS) tFStRS tF(CK) tW(CKL) tR(CK) 3 4 5 6 7 8 tD(TSxH) MIN tD(TSxH) MAX tD OUTPUT CONTROL INTERFACE Output Voltage Low VOL Rise and Fall Time of Clock tD TIMING DIAGRAM
KT8555 TIME SLOT ASSIGNMENT CIRCUIT
APPLICATION INFORMATION
The KT8555 is a control interface which requires an 8 bit serial control word. Either one of the frame sync output group, FSX0 to FXX3 or FSR0 to FSR3, affected by the control word is defined by the two bits, X and R. Time slot selected from 0 to 63 is specified. A frame sync output is highly active for one time slot which is equivalent to 8 cycles of BCLK. Up to 64 time slots are allowed to form a frame. There are two operational mode. In mode 1, each channel of transmit and receive direction has different time slot assigned. This mode can be selected by either leaving pin 9 (MODE) opened or connecting it with VCC. In such a case, pin 13 is RSYC input defining the start of each receive frame while four output, FSR0 to FSR3, are assigned with respect to RSYC. On the other hand, start of each transmit frame is defined by XSYC input by which output FSX0 to FSX3, are assigned. XSYC and RSYC can be phase related. Channels from 0-3 are selected by the input CH0 and CH1 (refer to the table 1). X is the first bit clocked into DC input CONTROL DATA FORMAT TABLE 1. OPERATING CONTROL MODE 1 TABLE 2. OPERATING CONTROL MODE 2
KT8555 TIME SLOT ASSIGNMENT CIRCUIT APPLICATION CIRCUIT The KT8555 TSAC combined with any kind of 1 CHIP CODEC from KT8554/7 series can obtain data timing as illustrated in Fig. 3. Even though FSX output goes high before BCLK gets high, the DX output of the 1 CHIP CODEC remains in the TRI-STATE mode until both outputs are high. The eight bit period is shortened to avoid PCM data clash at PCM pre- highway. Alternatively, full 8 bits can be obtained by inverting the BCLK to the 1 CHIP CODEC devices, thereby rising edges of BCLK and FSX/R are aligned. Fig. 4 is typical timing of the control data interface. Fig. 5 is the typical application circuit at operating control mode 2. Fig. 3 Transmit Data Timing Fig. 4 Control Data Timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 BCLK XSYC FSX1 FSX2 DX TS X CLKC CH0, CH1 CS DC X R T5 T4 T3 T2 T1 T0 X R T5 T4
KT8555 TIME SLOT ASSIGNMENT CIRCUIT NOTE 4 : Time slot assign status T0 T1 T2 T3 T4 Time Slot NOTE 5 : Different time slot assign for RX and TX respectively also available. Fig. 5 Digital interface on a typical subscriber linecard KT8555 CH0 CH1 CH2 CS CLKC BCLK XSYC DC FSX0 FSX1 FSX2 FSX3 FSR0 FSR1 FSR2 FSR3 VCCGNDMODE CH0 CH1 CH2 CS CLKC BCLK XSYC DC 9 10 +5V 0.1µF KT8554/57 TSX CLKSEL BCLKX MCLKX DR FSX FSR VFXI+ VFXI- GSX DX VFRO PDN 5
1 CHIP CODEC #1
1 CHIP CODEC #2
1 CHIP CODEC #3
1 CHIP CODEC #4
1 CHIP CODEC #5
1 CHIP CODEC #6
1 CHIP CODEC #7
NOTE 1 : Dc Format NOTE 2 : X, R action status NOTE 3 : T5 action status Timesolt assign Time slot assign Time slot assign Time slot assign disable Action R X Normal operation Time slot assign disable Action MSB T5T4T3T2T1T0 LSB R X